Semiconductor structure and forming method

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a first wafer which is provided with a first bonding surface, the first bonding surface is provided with a first bonding mark, and the side wall of the edge of the first wafer is provided with a first positioning gap; the second wafer is bonded with the first wafer and is provided with a second bonding surface, the second bonding surface is provided with a second bonding mark, the side wall of the edge of the second wafer is provided with a second positioning notch, the second bonding surface faces the first bonding surface, the first bonding mark is aligned with the second bonding mark, and the second bonding mark is aligned with the second positioning notch; a pattern projected to the first bonding surface by the first positioning gap is not overlapped with a pattern projected to the first bonding surface by the second positioning gap; the performance of the finally formed semiconductor structure can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Integrated circuits are generally composed of a layer of semiconductor devices and multiple layers of interconnects. In the early days, the focus of improving the performance and expanding the functions of integrated circuits was on the transistor level, that is, to achieve higher speed, lower power consumption, and higher integration by reducing the critical dimension. In addition, traditional integrated circuit packaging is to place a chip (bare chip) or multiple chips (MCM) in a package. This packaging form is called 2D.

[0003] As the feature size of semiconductor processes continues to shrink, especially after entering the nanometer size range, semiconductor manufacturing technology becomes increasingly difficult, and traditional technology is getting closer and closer to the physical size limit. As a result, three-dimensional integrated circuits are born.

[0004] Three-dimensional Integrated Circuit (3D IC) stacks multiple homogeneous or heterogeneous chips or circuit modules in the vertical direction and uses through silicon vias (TSV) to achieve vertical electrical connection. It has many advantages such as high interconnection density, small size, low power consumption and large bandwidth.

[0005] However, the electrical performance of existing three-dimensional integrated circuits still needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above problems, the present invention provides a semiconductor structure, including: a first wafer, the first wafer having a first bonding surface, a first bonding mark on the first bonding surface, and a first positioning notch on the edge sidewall of the first wafer; a second wafer bonded to the first wafer, the second wafer having a second bonding surface, a second bonding mark on the second bonding surface, and a second positioning notch on the edge sidewall of the second wafer, the second bonding surface faces the first bonding surface, the first bonding mark is aligned with the second bonding mark, and a pattern projected from the first positioning notch to the first bonding surface does not overlap with a pattern projected from the second positioning notch to the first bonding surface.

[0008] Optionally, the first wafer has a first diameter, the first diameter passes through the central axis of the first positioning notch; the second wafer has a second diameter, the second diameter passes through the central axis of the second positioning notch, and the first diameter coincides with the second diameter or the first diameter is perpendicular to the second diameter.

[0009] Optionally, it also includes: a third wafer, the third wafer has a third bonding surface, the third bonding surface has a third bonding mark, and the edge side wall of the third wafer has a third positioning notch.

[0010] Optionally, it also includes a fourth wafer bonded to the third wafer, the fourth wafer having a fourth bonding surface, a fourth bonding mark on the fourth bonding surface, and a fourth positioning notch on the edge side wall of the fourth wafer; the fourth bonding surface faces the third bonding surface, the third bonding mark is aligned with the fourth bonding mark, and the pattern of the third positioning notch projected onto the third bonding surface does not overlap with the pattern of the fourth positioning notch projected onto the third bonding surface.

[0011] Optionally, the third wafer has a third diameter, the third diameter passes through the central axis of the third positioning notch; the fourth wafer has a fourth diameter, the fourth diameter passes through the central axis of the fourth positioning notch, and the third diameter coincides with the fourth diameter or the third diameter is perpendicular to the fourth diameter.

[0012] Optionally, the third wafer also has a fifth bonding surface opposite to the third bonding surface, and the fifth bonding surface has a fifth bonding mark; the first wafer also has a sixth bonding surface opposite to the first bonding surface, and the sixth bonding surface has a sixth bonding mark; the fifth bonding surface faces the sixth bonding surface, the fifth bonding mark is aligned and bonded with the sixth bonding mark, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

[0013] Optionally, the third wafer has a fifth diameter, which passes through the central axis of the third positioning notch; the first wafer has a sixth diameter, which passes through the central axis of the first positioning notch, and the fifth diameter coincides with the sixth diameter or is perpendicular to the sixth diameter.

[0014] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a first wafer, the first wafer having a first bonding surface and a first positioning notch located on the edge side wall; forming a first bonding mark on the first bonding surface; providing a second wafer, the second wafer having a second bonding surface and a second positioning notch located on the edge side wall; forming a second bonding mark on the second bonding surface; bonding the first bonding surface and the second bonding surface by aligning the first bonding mark and the second bonding mark, and after bonding, the pattern of the first positioning notch projected to the first bonding surface does not overlap with the pattern of the second positioning notch projected to the first bonding surface.

[0015] Optionally, the first wafer has a first diameter, the first diameter passes through the central axis of the first positioning notch; the second wafer has a second diameter, the second diameter passes through the central axis of the second positioning notch, and the first diameter coincides with the second diameter or the first diameter is perpendicular to the second diameter.

[0016] Optionally, the center of the first bonding mark has a first position coordinate reference value, the center of the second bonding mark has a second position coordinate reference value, the X-axis coordinate value of the first position coordinate reference value is an opposite number to the X-axis coordinate value of the second position coordinate reference value, and the Y-axis coordinate value of the first position coordinate reference value is the same as the Y-axis coordinate value of the second position coordinate reference value; or the Y-axis coordinate value of the first position coordinate reference value is an opposite number to the Y-axis coordinate value of the second position coordinate reference value, and the X-axis coordinate value of the first position coordinate reference value is the same as the X-axis coordinate value of the second position coordinate reference value.

[0017] Optionally, by aligning the first bonding mark and the second bonding mark, bonding the first bonding surface and the second bonding surface includes: respectively identifying the first positioning notch and the second positioning notch; after identification, establishing a first coordinate system according to the first wafer, and establishing a second coordinate system according to the second wafer; obtaining a first position coordinate value corresponding to the center of the first bonding mark according to the first coordinate system; obtaining a second position coordinate value corresponding to the center of the second bonding mark according to the second coordinate system; when the first position coordinate value is the same as the first position coordinate reference value, and the second position coordinate value is the same as the second position coordinate reference value, bonding the first bonding surface and the second bonding surface.

[0018] Optionally, the method further includes adjusting the first wafer when the first position coordinate value is different from the first position coordinate reference value; and adjusting the second wafer when the second position coordinate value is different from the second position coordinate reference value.

[0019] Optionally, after identification, the method of establishing the first coordinate system and the second coordinate system includes: using the first diameter of the central axis passing through the first positioning notch as the Y axis of the first coordinate system; using the first sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the first diameter as the X axis; using the second diameter of the central axis passing through the second positioning notch as the Y axis of the second coordinate system; using the second sub-diameter of the second wafer passing through the center of the second wafer and perpendicular to the second diameter as the X axis.

[0020] Optionally, after identification, the method of establishing the first coordinate system and the second coordinate system includes: using the first diameter of the central axis passing through the first positioning notch as the Y axis of the first coordinate system; using the first sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the first diameter as the X axis; using the second diameter of the central axis passing through the second positioning notch as the X axis of the second coordinate system; using the third sub-diameter of the second wafer passing through the center of the second wafer and perpendicular to the second diameter as the Y axis.

[0021] Optionally, the method further includes: providing a third wafer, the third wafer having a third bonding surface, the third bonding surface having a third bonding mark, and an edge sidewall of the third wafer having a third positioning notch.

[0022] Optionally, it also includes: providing a fourth wafer, the fourth wafer having a fourth bonding surface, and the edge side wall of the fourth wafer having a fourth positioning notch; forming a third bonding mark on the third bonding surface; forming a fourth bonding mark on the fourth bonding surface; bonding the third bonding surface and the fourth bonding surface by aligning the third bonding mark and the fourth bonding mark, and after bonding, the pattern of the third positioning notch projected onto the third bonding surface does not overlap with the pattern of the fourth positioning notch projected onto the fourth bonding surface.

[0023] Optionally, the third bonding surface has a third diameter, the third diameter passes through the central axis of the third positioning notch; the fourth bonding surface has a fourth diameter, the fourth diameter passes through the central axis of the fourth positioning notch, the third diameter coincides with the fourth diameter or the third diameter is perpendicular to the fourth diameter.

[0024] Optionally, the third wafer also has a fifth bonding surface opposite to the third bonding surface, and a fifth bonding mark is formed on the fifth bonding surface; the first wafer also has a sixth bonding surface opposite to the first bonding surface, and a sixth bonding mark is formed on the sixth bonding surface; by aligning the fifth bonding mark and the sixth bonding mark, the fifth bonding surface and the sixth bonding surface are bonded, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

[0025] Optionally, the fifth bonding surface has a fifth diameter, which passes through the central axis of the third positioning notch; the sixth bonding surface has a sixth diameter, which passes through the central axis of the first positioning notch, and the fifth diameter coincides with the sixth diameter or is perpendicular to the sixth diameter.

[0026] Optionally, the method for bonding the fifth bonding surface to the sixth bonding surface includes: identifying a first positioning notch and a third positioning notch; establishing a third coordinate system based on the third wafer and establishing a fourth coordinate system based on the first wafer; obtaining a third position coordinate value corresponding to the center of the fifth bonding mark and a fourth position coordinate value corresponding to the center of the sixth bonding mark according to the third coordinate system and the fourth coordinate system, respectively; when the third position coordinate value is the same as the third position coordinate reference value corresponding to the center of the fifth bonding mark, and the fourth position coordinate value is the same as the fourth position coordinate reference value corresponding to the center of the sixth bonding mark, flipping the third wafer or the first wafer to bond the first wafer to the third wafer, aligning the fifth bonding mark with the sixth bonding mark, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the semiconductor structure scheme of the present invention, a first bonding surface of the first wafer has a first bonding mark, and an edge side wall of the first wafer has a first positioning notch; a second bonding surface of the second wafer has a second bonding mark, and an edge side wall of the second wafer has a second positioning notch, the first bonding mark is aligned with the second bonding mark, the first bonding surface and the second bonding surface are bonded, and the pattern of the first positioning notch projected onto the first bonding surface and the pattern of the second positioning notch projected onto the first bonding surface do not overlap; in the subsequent alignment process of the exposure machine, the exposure machine can only identify the first positioning notch or the second positioning notch, and will not identify the first positioning notch and the second positioning notch at the same time, thereby avoiding the exposure machine being unable to effectively identify the positioning notch or having errors in identification due to shape changes of the positioning notches in the bonded wafer or slight dislocations between the positioning notches, and being unable to pre-align the bonded wafer or having offsets after alignment, further reducing the probability of alignment failure, reducing exposure failures, and improving the yield of the bonded wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a bonded wafer;

[0030] Figures 2 to 9 is a structural schematic diagram of the formation process of the semiconductor structure in the first embodiment of the present invention;

[0031] Figures 10 to 13 is a structural schematic diagram of the formation process of the semiconductor structure in the second embodiment of the present invention;

[0032] Figure 14 to Figure 15 It is a structural schematic diagram of the formation process of the semiconductor structure in the third embodiment of the present invention. DETAILED DESCRIPTION

[0033] As the background technology, the electrical performance of the three-dimensional integrated circuit in the prior art still needs to be improved. The following will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 The invention is a structural diagram of a bonding wafer; the invention comprises a first wafer 100 having a first positioning notch 101 thereon; a second wafer 102 having a second positioning notch 103 thereon; the first wafer 100 and the second wafer 102 are bonded to form a bonding wafer, and the shape of the first positioning notch 101 is aligned with the shape of the second positioning notch 103.

[0035] The inventor discovered that after actual bonding, there is a slight misalignment between the first positioning notch 101 and the second positioning notch 103. Thus, after the first wafer 100 and the second wafer 102 are bonded, when a patterning process is performed on the back of the first wafer 100 or the second wafer 102, due to the slight misalignment between the first positioning notch 101 and the second positioning notch 103, the exposure machine cannot align the bonded wafer according to the position of the first positioning notch 101 or the second positioning notch 103, and thus cannot straighten the bonded wafer, resulting in alignment failure and the inability to perform the patterning process, thereby reducing the yield of the bonded wafer.

[0036] On this basis, the present invention provides a semiconductor structure, which aligns a first bonding mark with a second bonding mark, bonds a first bonding surface with a second bonding surface, and a pattern of a first positioning notch projected onto the first bonding surface and a pattern of a second positioning notch projected onto the first bonding surface do not overlap; in the subsequent alignment process performed by an exposure machine, the exposure machine can only identify the first positioning notch or the second positioning notch, and will not identify the first positioning notch and the second positioning notch at the same time, thereby avoiding the exposure machine being unable to effectively identify the positioning notch or having errors in identification due to shape changes of the positioning notches in the bonded wafer or slight misalignments between the positioning notches, thereby avoiding the inability to pre-align the bonded wafer or the presence of offset after alignment due to the inability to pre-align the bonded wafer due to shape changes of the positioning notches in the bonded wafer or slight misalignments between the positioning notches, thereby further reducing the probability of alignment failure, reducing exposure failures, and improving the yield of the bonded wafer.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 9 It is a structural schematic diagram of the formation process of the semiconductor structure in the first embodiment of the present invention.

[0039] First embodiment

[0040] First, please refer to Figure 2 , providing a first wafer 200, the first wafer 200 having a first bonding surface 200a and a first positioning notch 201 located on an edge sidewall.

[0041] In this embodiment, the first positioning notch 201 is a notch sunken toward the edge of the first wafer 200 , and the first positioning notch 201 is in a triangular shape.

[0042] In other embodiments, the first positioning notch 201 may also be in a straight line shape or a right angle shape, etc. These shapes are inherent in the wafer for actual use and are not limited thereto.

[0043] In this embodiment, the first wafer 200 has a first diameter d1 , and the first diameter d1 passes through the top point of the first positioning notch 201 .

[0044] In this embodiment, the first diameter d1 passes through the central axis of the first positioning notch 201 .

[0045] Please refer to Figure 2 and Figure 3 , a first bonding mark 202 is formed on the first bonding surface 200a.

[0046] Figure 3 for Figure 2 Enlarged view of the dotted line part.

[0047] In this embodiment, the step of forming the first bonding mark 202 on the first bonding surface 200a includes: placing the first wafer 200 on an exposure machine, the exposure machine first identifies the first positioning notch 201, and finds the center of the first wafer 200 at the same time, and uses the line connecting the center of the first wafer and the vertex of the first positioning notch 201 as the Y-axis, and the diameter passing through the center of the first wafer 200 and perpendicular to the Y-axis as the X-axis, so that an initial first coordinate system is established. The process of establishing the initial first coordinate system is the process of aligning the first wafer, and the center of the first wafer 200 can be set to (0,0) at the same time; after aligning the first wafer 200, exposing to form a pattern on the first wafer 200, during the exposure process, each pattern can have a precise position, and one of the exposed patterns can be the first bonding mark 202.

[0048] In this embodiment, the precise position value of the center of the first bonding mark 202 during exposure is used as the first position coordinate reference value.

[0049] The shape of the first bonding mark 202 can be set according to actual needs.

[0050] refer to Figure 4 , providing a second wafer 300 , the second wafer 300 having a second bonding surface 300 a and a second positioning notch 301 located at an edge of the second wafer 300 .

[0051] In this embodiment, the second positioning notch 301 is a notch sunken toward the edge of the second wafer 300 , and the second positioning notch 301 is in a triangular shape.

[0052] In other embodiments, the second positioning notch 301 may also be in a straight line shape or a right angle shape, etc. These shapes are inherent in the wafer for actual use.

[0053] In this embodiment, the second wafer 300 has a second diameter d2 , and the second diameter d2 passes through the vertex of the second positioning notch 301 .

[0054] In this embodiment, the second diameter d2 passes through the central axis of the second positioning notch 301. Figure 4 and Figure 5 , a second bonding mark 302 is formed on the second bonding surface 300a.

[0055] Figure 5 for Figure 4 Enlarged view of the dotted line part.

[0056] Similarly, in this embodiment, the step of forming the second bonding mark 302 on the second bonding surface 300a includes: placing the second wafer 300 on the exposure machine, the exposure machine first identifies the second positioning notch 301, and finds the center of the second wafer 300 at the same time, and uses the line connecting the center of the second wafer and the vertex of the second positioning notch 301 as the Y-axis, and the diameter passing through the center of the second wafer 300 and perpendicular to the Y-axis as the X-axis, so that an initial second coordinate system is established. The process of establishing the initial second coordinate system is the process of aligning the second wafer, and the center of the second wafer 300 can be set to (0,0) at the same time; after aligning the second wafer 300, exposing to form a pattern on the second wafer 300, during the exposure process, each pattern can have a precise position, and one of the exposed patterns can be the second bonding mark 302.

[0057] In this embodiment, the precise position value of the center of the second bonding mark 302 during exposure is used as the second position coordinate reference value.

[0058] In this embodiment, the first wafer 200 is subsequently bonded to the second wafer 300. During the process of forming the pattern, the patterns on the first wafer 200 and the second wafer 300 are mirror-symmetric about an axis of symmetry, wherein the axis of symmetry is parallel to the first diameter and the second diameter.

[0059] In this embodiment, the X-axis coordinate value of the first position coordinate reference value is opposite to the X-axis coordinate value of the second position coordinate reference value, and the Y-axis coordinate value of the first position coordinate reference value is the same as the Y-axis coordinate value of the second position coordinate reference value.

[0060] In other embodiments, the Y-axis coordinate value of the first position coordinate reference value is opposite to the Y-axis coordinate value of the second position coordinate reference value, and the X-axis coordinate value of the first position coordinate reference value is the same as the X-axis coordinate of the second position coordinate reference value.

[0061] Align the first bonding mark and the second bonding mark. For the process of bonding the first bonding surface and the second bonding surface, please refer to Figures 6 to 9 .

[0062] Please refer to Figure 6 First, the first wafer 200 and the second wafer 300 are placed on the machine platform.

[0063] In this embodiment, the first positioning notch 201 faces downward, and the second positioning notch 301 faces upward.

[0064] Please refer to Figure 7 , identify the first positioning notch 201, and establish a first coordinate system, wherein the grid on the first wafer 200 represents a coordinate grid.

[0065] In this embodiment, the first coordinate system is established with the first diameter of the central axis passing through the first positioning notch 201 as the Y-axis of the first coordinate system; the first sub-diameter of the first wafer 200 passing through the center of the first wafer 200 and perpendicular to the first diameter is the X-axis, and the center position coordinates of the first wafer 200 are (0,0). It should be noted that the choice of the origin here can be determined according to actual needs.

[0066] In this embodiment, in the first coordinate system, a first position coordinate value corresponding to the center of the first bonding mark 202 is obtained.

[0067] In this embodiment, the first positioning notch 201 faces downward, and the second positioning notch 301 faces upward.

[0068] Please continue to refer to Figure 7 , identify the second positioning notch 301 and establish a second coordinate system, wherein the grid on the second wafer 300 represents a coordinate grid.

[0069] In this embodiment, the second coordinate system is established with the second diameter of the central axis passing through the second positioning notch as the Y-axis of the second coordinate system; the second sub-diameter of the second wafer 300 passing through the center of the second wafer 300 and perpendicular to the second diameter is taken as the X-axis, and the center position coordinates of the second wafer 300 are (0,0). It should be noted that the choice of the origin here can be selected according to actual needs.

[0070] In other embodiments, when the identified first positioning notch 201 is facing downward (or upward) and the second positioning notch 301 is facing left (or right), the method of establishing the first coordinate system and the second coordinate system also includes using the first diameter of the central axis passing through the first positioning notch as the Y-axis of the first coordinate system; using the first sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the first diameter as the X-axis; using the second diameter of the central axis passing through the second positioning notch as the X-axis of the second coordinate system; and using the third sub-diameter of the second wafer passing through the center of the second wafer and perpendicular to the second diameter as the Y-axis.

[0071] The settings of upward, downward, leftward, and rightward are based on a coordinate system and take the center of the wafer as a reference to locate the relative position of the notch.

[0072] In this embodiment, in the second coordinate system, a second position coordinate value corresponding to the center of the second bonding mark 302 is obtained.

[0073] In this embodiment, the placement positions of the first positioning notch 201 and the second positioning notch 301 before bonding are consistent with the placement positions of the first positioning notch 201 and the second positioning notch 301 during the process of forming the first bonding mark 202 and the second bonding mark 302 .

[0074] In this embodiment, the methods for establishing the initial first coordinate system and the first coordinate system are the same, and the methods for establishing the initial second coordinate system and the second coordinate system are also the same.

[0075] Please refer to Figure 8 , when the first position coordinate value is the same as the first position coordinate reference value, and the second position coordinate value is the same as the second position coordinate reference value, the first bonding surface 200a and the second bonding surface 300a are bonded, the first wafer 200 is flipped over to bond the first wafer 200 and the second wafer 300, the first bonding mark 202 is aligned with the second bonding mark 302, and the pattern of the first positioning notch 201 projected onto the first bonding surface 200a does not overlap with the pattern of the second positioning notch 301 projected onto the first bonding surface 200a.

[0076] Fig. 9 for Figure 8 Enlarged view of the dotted line portion.

[0077] In this embodiment, after bonding, the first diameter d1 coincides with the second diameter d2 .

[0078] In other embodiments, after bonding, the first diameter d1 and the second diameter d2 form a perpendicular relationship.

[0079] In this embodiment, the first positioning notch 201 and the second positioning notch 301 are respectively distributed on two sides of the bonding wafer, and there is no overlapping part.

[0080] In this embodiment, after the first wafer 200 and the second wafer 300 are bonded, the pattern of the first positioning notch 201 projected onto the first bonding surface 200a does not overlap with the pattern of the second positioning notch 301 projected onto the first bonding surface 200a. In the subsequent alignment process of the exposure machine, the exposure machine can only recognize the first positioning notch 201 or the second positioning notch 301, and will not recognize the first positioning notch 201 and the second positioning notch 301 at the same time, thereby avoiding the situation where the exposure machine cannot effectively identify the positioning notch or there is an error in the identification due to the shape change of the positioning notch in the bonded wafer or the pre-alignment of the bonded wafer or there is an offset after alignment, thereby further reducing the probability of alignment failure, reducing exposure failures, and improving the yield of the bonded wafer.

[0081] In other embodiments, when the first position coordinate value is different from the first position coordinate reference value, the first wafer 200 is adjusted; when the second position coordinate value is different from the second position coordinate reference value, the second wafer 300 is adjusted, and then the first wafer 200 is bonded to the second wafer.

[0082] Second embodiment

[0083] Figures 10 to 13 It is a structural schematic diagram of the formation process of the semiconductor structure in the second embodiment of the present invention.

[0084] The difference between the second embodiment and the first embodiment is that the second embodiment further includes a third wafer 400 .

[0085] Please refer to Fig.10 , also includes a third wafer 400.

[0086] In this embodiment, the third wafer 400 has a fifth bonding surface 400 a , on which a fifth bonding mark 402 is formed, and an edge sidewall of the third wafer 400 has a third positioning notch 401 .

[0087] In this embodiment, after the fifth bonding mark 402 is formed by exposure, the precise position value of the center of the fifth bonding mark 402 is used as the third position coordinate reference value.

[0088] In this embodiment, the third wafer 400 further has a third bonding surface 400 b opposite to the fifth bonding surface 400 a , and a third bonding mark 403 is formed on the third bonding surface 400 b .

[0089] In this embodiment, the third bonding mark 403 is on the third bonding surface 400b and cannot be seen from the fifth bonding surface 400a, so the third bonding mark 403 is represented by a dotted line.

[0090] In this embodiment, the fifth bonding surface 400 a has a fifth diameter d5 , and the fifth diameter d5 passes through the vertex of the third positioning notch 401 and the central axis of the third positioning notch 401 .

[0091] Please continue to refer to Figure 2 The first wafer 200 further has a sixth bonding surface 200 b opposite to the first bonding surface 200 a , and a sixth bonding mark 203 is formed on the sixth bonding surface 200 b .

[0092] In the present embodiment, the precise position value of the center of the sixth bonding mark 203 formed during exposure is used as the fourth position coordinate reference value.

[0093] In this embodiment, the sixth bonding mark 203 is on the sixth bonding surface 200 b and cannot be seen from the first bonding surface 200 a , so the sixth bonding mark 203 is indicated by a dotted line.

[0094] In this embodiment, the sixth bonding surface 200 b has a sixth diameter d6 , and the sixth diameter d6 passes through the vertex of the first positioning notch 201 and the central axis of the first positioning notch 201 .

[0095] The fifth bonding surface 400a and the sixth bonding surface 200b are bonded by aligning the fifth bonding mark 402 and the sixth bonding mark 203. For a process in which the pattern of the first positioning notch 201 projected onto the surface of the sixth bonding surface 200b does not overlap with the pattern of the third positioning notch 401 projected onto the sixth bonding surface 200b, please refer to Figures 11 to 13 .

[0096] Please refer to Fig.11 First, the first wafer 200 and the third wafer 400 are placed on the machine platform.

[0097] In this embodiment, the first wafer 200 is bonded to the second wafer 300 and then to the third wafer 400 .

[0098] In this embodiment, the first positioning notch 201 faces downward, and the third positioning notch 401 faces upward.

[0099] In other embodiments, the first positioning notch 201 faces downward and the third positioning notch 401 faces left; the first positioning notch 201 faces upward and the third positioning notch 401 faces right; the first positioning notch 201 faces upward and the third positioning notch 401 faces left; the first positioning notch 201 faces downward and the third positioning notch 401 faces right.

[0100] The first positioning notch 201 and the third positioning notch 401 will be identified.

[0101] Please refer to Fig.12 , identify the first positioning notch 201, and establish a fourth coordinate system, in which the grid on the first wafer 200 represents a coordinate grid.

[0102] In this embodiment, the fourth coordinate system is established with the sixth diameter of the central axis passing through the first positioning notch 201 as the Y-axis of the first coordinate system; the sixth sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the sixth diameter is the X-axis, and the center position coordinates of the first wafer are (0,0). It should be noted that the choice of the origin here can be selected according to actual needs.

[0103] In this embodiment, in the fourth coordinate system, a fourth position coordinate value corresponding to the center of the sixth bonding mark 203 is obtained.

[0104] In this embodiment, the X-axis coordinate value of the third position coordinate reference value is opposite to the X-axis coordinate value of the fourth position coordinate reference value, and the Y-axis coordinate value of the third position coordinate reference value is the same as the Y-axis coordinate of the fourth position coordinate reference value.

[0105] Please continue to refer to Fig.12 , identify the third positioning notch 401, and establish a third coordinate system, wherein the grid on the third wafer 400 represents a coordinate grid.

[0106] In this embodiment, the third coordinate system is established with the third diameter of the central axis passing through the third positioning notch 401 as the Y-axis of the third coordinate system; the third sub-diameter of the third wafer passing through the center of the third wafer and perpendicular to the third diameter is the Z-axis, and the center position coordinates of the third wafer are (0,0). It should be noted that the choice of the origin here can be selected according to actual needs.

[0107] In this embodiment, in the third coordinate system, a third position coordinate value corresponding to the center of the fifth bonding mark 402 is obtained.

[0108] Please refer to Fig.13 When the third position coordinate value is the same as the third position coordinate reference value and the fourth position coordinate value is the same as the fourth position coordinate reference value, flip the third wafer 400 or the first wafer 200 to bond the first wafer 200 to the third wafer 300, align the fifth bonding mark 402 with the sixth bonding mark 203, and the pattern of the first positioning notch 201 projected onto the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch 401 projected onto the sixth bonding surface.

[0109] In this embodiment, the fifth diameter coincides with the sixth diameter.

[0110] In other embodiments, the fifth diameter is perpendicular to the sixth diameter.

[0111] Third embodiment

[0112] Figure 14 to Figure 15 It is a structural schematic diagram of the formation process of the semiconductor structure in the third embodiment of the present invention.

[0113] The difference between the third embodiment and the second embodiment is that the third embodiment further includes a fourth wafer bonded to the third wafer 400 .

[0114] In this embodiment, the third wafer 400 and the fourth wafer 500 are bonded after the first wafer 200 and the third wafer 400 are bonded.

[0115] In other embodiments, the bonding between the third wafer 400 and the fourth wafer 500 is performed before the bonding between the third wafer 400 and the first wafer 200 .

[0116] Please refer to Fig.14 A fourth wafer 500 is provided. The fourth wafer 500 has a fourth bonding surface 500a. The edge sidewall of the fourth wafer 500 has a fourth positioning notch 501. A fourth bonding mark 502 is formed on the fourth bonding surface 500a.

[0117] In this embodiment, the fourth bonding surface 500 a has a fourth diameter, and the fourth diameter passes through the central axis of the fourth positioning notch.

[0118] Please refer to Fig.10 , a third bonding mark 403 is formed on the third bonding surface 400b.

[0119] Please refer to Fig.15 , the third bonding mark 403 and the fourth bonding mark 502 are used for alignment, and the third bonding surface 400b and the fourth bonding surface 500a are bonded. After bonding, the pattern of the third positioning notch 401 projected onto the third bonding surface 400b does not overlap with the pattern of the fourth positioning notch 501 projected onto the fourth bonding surface 500a.

[0120] In this embodiment, after the third wafer 400 and the fourth wafer 500 are bonded, the third diameter coincides with the fourth diameter.

[0121] In other embodiments, the third diameter is perpendicular to the fourth diameter.

[0122] In this embodiment, the bonding process of the third bonding surface 400 b and the fourth bonding surface 500 a is the same as the bonding process of the first bonding surface 200 a and the second bonding surface 300 a , and will not be described again here.

[0123] In this embodiment, after the first wafer 200, the second wafer 300, the third wafer 400 and the fourth wafer 500 are bonded, the first positioning notch 201, the second positioning notch 301, the third positioning notch 401 and the fourth positioning notch 501 are staggered and do not overlap, so that the exposure machine can only recognize one positioning notch during the alignment process. This can avoid the situation where the exposure machine is unable to effectively identify the positioning notch or there is an error in the identification due to the shape change of the positioning notch in the bonded wafer or the slight misalignment between the positioning notches, resulting in the inability to pre-align the bonded wafer or the presence of offset after alignment, further reducing the probability of alignment failure, reducing exposure failures, and improving the yield of bonded wafers.

[0124] In this embodiment, only the bonding between four wafers is listed, but it is not limited to four wafers. The actual number of wafers that need to be bonded depends on the actual process requirements.

[0125] In this embodiment, the bonding process between two wafers may refer to the bonding process between the first wafer 200 and the second wafer 300 or the bonding process between the third wafer 400 and the fourth wafer 500 , and the bonding process between the bonded wafer groups may refer to the bonding process between the first wafer 200 and the third wafer 400 .

[0126] Accordingly, please refer to Figure 8 The present invention also provides a semiconductor structure, including a first wafer 200, the first wafer 200 having a first bonding surface 200a, the first bonding surface 200a having a first bonding mark 202, and the edge sidewall of the first wafer 200 having a first positioning notch 201; a second wafer 300 bonded to the first wafer 200, the second wafer 300 having a second bonding surface 300a, the second bonding surface 300a having a second bonding mark 302, the edge sidewall of the second wafer 300 having a second positioning notch 301, the second bonding surface 300a facing the first bonding surface 200a, the first bonding mark 202 and the second bonding mark 302 are aligned, and the pattern of the first positioning notch 201 projected onto the first bonding surface 200a does not overlap with the pattern of the second positioning notch 301 projected onto the first bonding surface 200a.

[0127] In this embodiment, the first wafer 200 has a first diameter d1, and the first diameter d1 passes through the central axis of the first positioning notch 201; the second wafer 300 has a second diameter d2, and the second diameter d2 passes through the central axis of the second positioning notch 301, and the first diameter d1 coincides with the second diameter d2 or the first diameter d1 is perpendicular to the second diameter d2.

[0128] In this embodiment, during the subsequent alignment process of the exposure machine, the exposure machine can only identify the first positioning notch 201 or the second positioning notch 301, and will not identify the first positioning notch 201 and the second positioning notch 301 at the same time, thereby avoiding the situation where the exposure machine cannot effectively identify the positioning notch or there is an error in identification due to the shape change of the positioning notch in the bonding wafer or the slight misalignment between the positioning notches, resulting in the inability to pre-align the bonding wafer or the presence of offset after alignment, further reducing the probability of alignment failure, reducing exposure failures, and improving the yield of the bonding wafer.

[0129] In this embodiment, please refer to Fig.13 or Fig.14 , further comprising: a third wafer 400, the third wafer 400 having a third bonding surface 400b, the third bonding surface 400b having a third bonding mark 403, and an edge sidewall of the third wafer 400 having a third positioning notch 401.

[0130] In this embodiment, the third wafer 400 also has a fifth bonding surface 400a opposite to the third bonding surface 400b, and the fifth bonding surface 400a has a fifth bonding mark 402; the first wafer 200 also has a sixth bonding surface 200b opposite to the first bonding surface 200a, and the sixth bonding surface 200b has a sixth bonding mark 203; the fifth bonding surface 400a faces the sixth bonding surface 200b, the fifth bonding mark 402 is aligned and bonded with the sixth bonding mark 203, and the pattern of the first positioning notch 201 projected onto the surface of the sixth bonding surface 200b does not overlap with the pattern of the third positioning notch 401 projected onto the sixth bonding surface 200b.

[0131] In this embodiment, the pattern of the second positioning notch 301 projected onto the sixth bonding surface 200 b does not overlap with the pattern of the third positioning notch 401 projected onto the sixth bonding surface 200 b .

[0132] In this embodiment, the fifth bonding surface 400a has a fifth diameter d5, and the fifth diameter d5 passes through the central axis of the third positioning notch 401; the first wafer 200 has a sixth diameter d6, and the sixth diameter d6 passes through the central axis of the first positioning notch 201, and the fifth diameter d5 coincides with the sixth diameter d6 or the fifth diameter d5 is perpendicular to the sixth diameter d6.

[0133] In this embodiment, please refer to Fig.15 , also includes a fourth wafer 500 bonded to the third wafer 400, the fourth wafer 500 has a fourth bonding surface 500a, the fourth bonding surface 500a has a fourth bonding mark 502, and the edge sidewall of the fourth wafer 500 has a fourth positioning notch 501; the fourth bonding surface 500a faces the third bonding surface 400b, the third bonding mark 403 is aligned with the fourth bonding mark 502, and the pattern of the third positioning notch 401 projected to the third bonding surface 400b and the pattern of the fourth positioning notch 501 projected to the third bonding surface 400b do not overlap.

[0134] In this embodiment, the third wafer 400 has a third diameter d3 passing through the central axis of the third positioning notch 401 ; the fourth wafer 500 has a fourth diameter d4 passing through the central axis of the fourth positioning notch 501 , and the third diameter d3 coincides with the fourth diameter d4 .

[0135] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first wafer, wherein the first wafer has a first bonding surface, a first bonding mark is provided on the first bonding surface, and an edge sidewall of the first wafer has a first positioning notch; A second wafer bonded to the first wafer, the second wafer having a second bonding surface, the second bonding surface having a second bonding mark, the edge side wall of the second wafer having a second positioning notch, the second bonding surface facing the first bonding surface, the first bonding mark aligned with the second bonding mark, and a pattern projected from the first positioning notch to the first bonding surface and a pattern projected from the second positioning notch to the first bonding surface do not overlap.

2. The semiconductor structure according to claim 1, wherein: The first wafer has a first diameter, and the first diameter passes through the central axis of the first positioning notch; the second wafer has a second diameter, and the second diameter passes through the central axis of the second positioning notch, and the first diameter coincides with the second diameter or is perpendicular to the second diameter.

3. The semiconductor structure according to claim 1, wherein: Also includes: A third wafer, wherein the third wafer has a third bonding surface, a third bonding mark is provided on the third bonding surface, and a third positioning notch is provided on an edge sidewall of the third wafer.

4. The semiconductor structure according to claim 3, characterized in that It also includes a fourth wafer bonded to the third wafer, the fourth wafer having a fourth bonding surface, the fourth bonding surface having a fourth bonding mark, and the edge side wall of the fourth wafer having a fourth positioning notch; the fourth bonding surface faces the third bonding surface, the third bonding mark is aligned with the fourth bonding mark, and the pattern of the third positioning notch projected onto the third bonding surface does not overlap with the pattern of the fourth positioning notch projected onto the third bonding surface.

5. The semiconductor structure according to claim 4, characterized in that The third wafer has a third diameter, and the third diameter passes through the central axis of the third positioning notch; the fourth wafer has a fourth diameter, and the fourth diameter passes through the central axis of the fourth positioning notch, and the third diameter coincides with the fourth diameter or the third diameter is perpendicular to the fourth diameter.

6. The semiconductor structure according to claim 3, characterized in that The third wafer also has a fifth bonding surface opposite to the third bonding surface, and the fifth bonding surface has a fifth bonding mark; the first wafer also has a sixth bonding surface opposite to the first bonding surface, and the sixth bonding surface has a sixth bonding mark; the fifth bonding surface faces the sixth bonding surface, the fifth bonding mark is aligned and bonded with the sixth bonding mark, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

7. The semiconductor structure according to claim 6, wherein: The third wafer has a fifth diameter, and the fifth diameter passes through the central axis of the third positioning notch; the first wafer has a sixth diameter, and the sixth diameter passes through the central axis of the first positioning notch, and the fifth diameter coincides with the sixth diameter or the fifth diameter is perpendicular to the sixth diameter.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a first wafer, wherein the first wafer has a first bonding surface and a first positioning notch located on an edge sidewall; forming a first bonding mark on the first bonding surface; Providing a second wafer, wherein the second wafer has a second bonding surface and a second positioning notch located on an edge sidewall; forming a second bonding mark on the second bonding surface; The first bonding surface and the second bonding surface are bonded by aligning the first bonding mark and the second bonding mark. After bonding, the pattern of the first positioning notch projected onto the first bonding surface does not overlap with the pattern of the second positioning notch projected onto the first bonding surface.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first wafer has a first diameter, and the first diameter passes through the central axis of the first positioning notch; the second wafer has a second diameter, and the second diameter passes through the central axis of the second positioning notch, and the first diameter coincides with the second diameter or is perpendicular to the second diameter.

10. The method for forming a semiconductor structure according to claim 8, wherein: The center of the first bonding mark has a first position coordinate reference value, the center of the second bonding mark has a second position coordinate reference value, the X-axis coordinate value of the first position coordinate reference value is an opposite number to the X-axis coordinate value of the second position coordinate reference value, and the Y-axis coordinate value of the first position coordinate reference value is the same as the Y-axis coordinate value of the second position coordinate reference value; or the Y-axis coordinate value of the first position coordinate reference value is an opposite number to the Y-axis coordinate value of the second position coordinate reference value, and the X-axis coordinate value of the first position coordinate reference value is the same as the X-axis coordinate value of the second position coordinate reference value.

11. The method for forming a semiconductor structure according to claim 10, wherein: Bonding the first bonding surface and the second bonding surface by aligning the first bonding mark and the second bonding mark includes: Respectively identifying the first positioning notch and the second positioning notch; After the identification, a first coordinate system is established according to the first wafer, and a second coordinate system is established according to the second wafer; Acquire a first position coordinate value corresponding to the center of the first bonding mark according to the first coordinate system; Acquire a second position coordinate value corresponding to the center of the second bonding mark according to the second coordinate system; When the first position coordinate value is the same as the first position coordinate reference value, and the second position coordinate value is the same as the second position coordinate reference value, the first bonding surface and the second bonding surface are bonded.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method further includes adjusting the first wafer when the first position coordinate value is different from the first position coordinate reference value; and adjusting the second wafer when the second position coordinate value is different from the second position coordinate reference value.

13. The method for forming a semiconductor structure according to claim 11, wherein: After identification, the method of establishing the first coordinate system and the second coordinate system includes: Taking the first diameter of the central axis passing through the first positioning notch as the Y axis of the first coordinate system; Taking a first sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the first diameter as an X-axis; Taking the second diameter of the central axis passing through the second positioning notch as the Y axis of the second coordinate system; A second sub-diameter of the second wafer passing through the center of the second wafer and perpendicular to the second diameter is taken as an X-axis.

14. The method for forming a semiconductor structure according to claim 11, wherein: After identification, the method of establishing the first coordinate system and the second coordinate system includes: Taking the first diameter of the central axis passing through the first positioning notch as the Y axis of the first coordinate system; Taking a first sub-diameter of the first wafer passing through the center of the first wafer and perpendicular to the first diameter as an X-axis; Taking the second diameter of the central axis passing through the second positioning notch as the X-axis of the second coordinate system; A third sub-diameter of the second wafer passing through the center of the second wafer and perpendicular to the second diameter is taken as the Y axis.

15. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: A third wafer is provided. The third wafer has a third bonding surface. The third bonding surface has a third bonding mark. The edge sidewall of the third wafer has a third positioning notch.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: Providing a fourth wafer, wherein the fourth wafer has a fourth bonding surface, and an edge sidewall of the fourth wafer has a fourth positioning notch; forming a third bonding mark on the third bonding surface; forming a fourth bonding mark on the fourth bonding surface; The third bonding surface and the fourth bonding surface are bonded by aligning the third bonding mark and the fourth bonding mark. After bonding, the pattern of the third positioning notch projected onto the third bonding surface does not overlap with the pattern of the fourth positioning notch projected onto the fourth bonding surface.

17. The method for forming a semiconductor structure according to claim 16, wherein: The third bonding surface has a third diameter, and the third diameter passes through the central axis of the third positioning notch; the fourth bonding surface has a fourth diameter, and the fourth diameter passes through the central axis of the fourth positioning notch, and the third diameter coincides with the fourth diameter or the third diameter is perpendicular to the fourth diameter.

18. The method for forming a semiconductor structure according to claim 15, wherein: The third wafer also has a fifth bonding surface opposite to the third bonding surface, and a fifth bonding mark is formed on the fifth bonding surface; the first wafer also has a sixth bonding surface opposite to the first bonding surface, and a sixth bonding mark is formed on the sixth bonding surface; by aligning the fifth bonding mark and the sixth bonding mark, the fifth bonding surface and the sixth bonding surface are bonded, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

19. The method for forming a semiconductor structure according to claim 18, wherein: The fifth bonding surface has a fifth diameter, which passes through the central axis of the third positioning notch; the sixth bonding surface has a sixth diameter, which passes through the central axis of the first positioning notch, and the fifth diameter coincides with the sixth diameter or is perpendicular to the sixth diameter.

20. The method for forming a semiconductor structure according to claim 19, wherein: The method of bonding the fifth bonding surface to the sixth bonding surface includes: Identifying the first positioning notch and the third positioning notch; Establishing a third coordinate system according to the third wafer and establishing a fourth coordinate system according to the first wafer; acquiring a third position coordinate value corresponding to the center of the fifth bonding mark and a fourth position coordinate value corresponding to the center of the sixth bonding mark according to the third coordinate system and the fourth coordinate system respectively; When the third position coordinate value is the same as the third position coordinate reference value corresponding to the center of the fifth bonding mark, and the fourth position coordinate value is the same as the fourth position coordinate reference value corresponding to the center of the sixth bonding mark, flip the third wafer or the first wafer to bond the first wafer to the third wafer, align the fifth bonding mark with the sixth bonding mark, and the pattern of the first positioning notch projected to the surface of the sixth bonding surface does not overlap with the pattern of the third positioning notch projected to the sixth bonding surface.

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