Tunneling ohmic contact P-channel GaN MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure and preparation method thereof

Abstract

The invention discloses a tunneling ohmic contact P-channel GaN MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure and a preparation method thereof. The structure sequentially comprises a substrate, a nucleating layer, a buffer layer, a P-type channel layer, a P-type heavily doped layer and an N-type heavily doped layer from bottom to top. A plurality of vertical holes are formed in the N-type heavily doped layer and penetrate through the N-type heavily doped layer; a gate groove is arranged between the drain electrode and the source electrode, and a gate electrode is arranged in the gate groove. And the P-type heavily doped layer and the N-type heavily doped layer form a tunnel junction, so that ohmic contact is formed between the drain electrode and the P-type channel layer and between the source electrode and the P-type channel layer. The vertical holes enhance the activation of doped impurities in the P-type channel layer and the P-type heavily doped layer, and improve the hole concentration in the P-type channel layer and the P-type heavily doped layer, thereby reducing the ohmic contact between the drain electrode and the P-type channel layer, and between the source electrode and the P-type channel layer, and improving the conduction current and other performances of the P-channel MOSFET device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a tunneling ohmic contact P-channel GaN MOSFET device structure and a preparation method thereof. Background Art

[0002] Power electronic devices based on gallium nitride materials have the advantages of high power density output, high energy conversion efficiency, ultra-fast switching capability and low on-resistance, and are widely used in many fields. The gallium nitride complementary field effect transistor inverter realized by combining P-channel gallium nitride MOSFET devices with N-channel gallium nitride MOSFET devices is one of the important applications of gallium nitride.

[0003] However, the P-channel GaN MOSFET devices required for GaN complementary field effect transistor inverters still have a lot of problems to be solved, and ohmic contact resistance is one of them. In order to reduce the ohmic contact resistance, a P-channel transistor structure based on a tunnel junction has been proposed. This structure forms a tunnel junction by epitaxially growing a P-type heavily doped layer and an N-type heavily doped layer on a P-type channel layer. The drain electrode and the source electrode form an ohmic contact with the tunnel junction, which improves the contact characteristics of the metal and the semiconductor, enables the device to obtain a higher current density, and improves the current stability of the P-type GaN channel transistor.

[0004] However, in the preparation process of the P-channel transistor of the above structure, the N-type heavily doped layer will affect the Mg activation annealing step of the P-type channel layer and the P-type heavily doped layer. Some people also proposed that the N-type heavily doped layer can be epitaxially grown after the Mg activation annealing step, but this will also increase the complexity of the P-channel transistor process. Summary of the invention

[0005] In order to overcome the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a tunneling ohmic contact P-channel GaN MOSFET device structure and a preparation method thereof, so as to improve the on-current and other performances of the P-channel MOSFET device.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A tunneling ohmic contact P-channel GaN MOSFET device structure, comprising a substrate, a nucleation layer, a buffer layer, a P-type channel layer, a P-type heavily doped layer and an N-type heavily doped layer arranged in sequence from bottom to top;

[0008] The N-type heavily doped layer is provided with a plurality of vertical holes, and the vertical holes penetrate the N-type heavily doped layer; the drain electrode and the source electrode are arranged on the N-type heavily doped layer; a gate groove is arranged between the drain electrode and the source electrode, and the N-type heavily doped layer, the P-type heavily doped layer and a part of the P-type channel layer are removed from the gate groove, the gate electrode is arranged in the gate groove, and a gate dielectric layer is arranged between the surface of the gate groove and the gate electrode;

[0009] The P-type heavily doped layer and the N-type heavily doped layer form a tunnel junction, so that an ohmic contact is formed between the drain electrode and the P-type channel layer, and between the source electrode and the P-type channel layer.

[0010] In one embodiment, the nucleation layer, buffer layer, P-type channel layer, P-type heavily doped layer, and N-type heavily doped layer are group III nitride materials, and the doping concentration of the P-type heavily doped layer is much greater than the doping concentration of the P-type channel layer.

[0011] In one embodiment, the material of the substrate is any one or more of Si, SiC, sapphire, and diamond; the material of the nucleation layer is AlN, the material of the buffer layer is AlGaN or GaN, the material of the P-type channel layer is one or more of GaN and InGaN, the doping impurities are one or more of Mg and Zn, and the doping concentration is 1.0×10 17 -1.0×10 20 cm -3 The material of the P-type heavily doped layer is one or more of GaN and InGaN, and the doping impurities are one or more of Mg and Zn, with a doping concentration of 1.0×10 19 -1.0×10 20 cm -3 The material of the N-type heavily doped layer is one or more of GaN and InGaN, and the doping impurity is Si, with a doping concentration of 1.0×10 18 -1.0×10 20 cm -3 .

[0012] In one embodiment, the thickness of the nucleation layer is 10-300nm; the thickness of the buffer layer is 0.1-5μm, the thickness of the P-type channel layer is 5-30nm; the thickness of the P-type heavily doped layer is 10-100nm; the thickness of the N-type heavily doped layer is 5-100nm.

[0013] In one embodiment, the cross-section of the vertical hole is circular, elliptical or polygonal, and the spacing between adjacent vertical holes is 50 nm-2 μm. When the vertical holes are circular, the diameter is 50 nm-2 μm.

[0014] In one embodiment, the material of the drain electrode and the material of the source electrode include at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode includes at least two of Ti, Al, Ta, Mo, Au, and Ni.

[0015] In one embodiment, an isolation layer is further provided between the P-type heavily doped layer and the N-type heavily doped layer; the isolation layer is made of one or more materials selected from AlGaN and InGaN, and has a thickness of 1-10 nm.

[0016] In one embodiment, an N-type channel layer and a barrier layer are further arranged between the buffer layer and the P-type channel layer; the material of the N-type channel layer is unintentionally doped GaN, and the thickness is 10-500nm; the barrier layer is arranged on the N-type channel layer, and its material is one or more of AlGaN, InAlN, AlN, and the thickness is 3-20nm.

[0017] In one embodiment, the vertical hole only penetrates to the upper surface of the P-type heavily doped layer, or penetrates the N-type heavily doped layer and then etches part of the P-type heavily doped layer, or penetrates all the P-type heavily doped layers to the upper surface of the P-type channel layer, or penetrates all the P-type heavily doped layers and etches part of the P-type channel layer.

[0018] The present invention also provides a method for preparing the tunneling ohmic contact P-channel GaN MOSFET device, comprising the following steps:

[0019] S1, sequentially growing a nucleation layer, a buffer layer, a P-type channel layer, a P-type heavily doped layer and an N-type heavily doped layer on a substrate;

[0020] S2, doping the P-type channel layer, the P-type heavily doped layer and the N-type heavily doped layer;

[0021] S3, isolate the device;

[0022] S4, using a photolithography process to form a vertical hole on the N-type heavily doped layer, or the N-type heavily doped layer and the P-type heavily doped layer, or the N-type heavily doped layer, the P-type heavily doped layer and the P-type channel layer, and to form a gate groove between the source electrode region and the drain electrode region;

[0023] S5, annealing to activate the P-type channel layer and the P-type heavily doped layer;

[0024] S6, depositing a gate dielectric layer on the surface of the gate groove and the surface of the N-type heavily doped layer;

[0025] S7. Prepare a source electrode and a drain electrode at both ends of the surface of the N-type heavily doped layer, respectively, and deposit a gate metal on the surface of the gate dielectric layer to form a gate electrode.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention utilizes vertical holes in the structure of the P-type channel layer and the P-type heavily doped layer in the epitaxial N-type heavily doped layer, which not only retains the tunnel junction ohmic contact, but also reduces the area of ​​the P-type channel layer and the P-type heavily doped layer covered by the N-type heavily doped layer, and can use high-temperature and long-term annealing to achieve efficient activation of Mg impurities in the P-type channel layer and the P-type heavily doped layer, thereby increasing the device current and reducing the on-resistance of the device. In terms of preparation method, the present invention is compatible with existing processes, has outstanding effects, is simple in process, and has the advantages of both high performance and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a tunneling ohmic contact P-channel GaN MOSFET device structure provided in an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of another tunneling ohmic contact P-channel GaN MOSFET device structure provided by an embodiment of the present invention.

[0030] Figure 3 Schematic diagram of top view of some vertical holes.

[0031] Figure 4-Figure 8 A schematic diagram of a process of preparing a tunneling ohmic contact P-channel GaN MOSFET device provided in an embodiment of the present invention.

[0032] Explanation of the reference numerals: 1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-barrier layer; 6-P-type channel layer; 7-P-type heavily doped layer; 8-N-type heavily doped layer; 9-drain electrode; 10-source electrode; 11-gate electrode; 12-gate dielectric layer; 13-vertical hole; 14-groove. DETAILED DESCRIPTION

[0033] The present invention is described in detail below in conjunction with specific implementations, but the implementations of the present invention are not limited thereto.

[0034] Embodiment 1:

[0035] This embodiment provides a tunneling ohmic contact P-channel GaN MOSFET device structure, such as Figure 1 As shown, from bottom to top, it includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a P-type channel layer 6, a P-type heavily doped layer 7, and an N-type heavily doped layer 8. The nucleation layer 2, the buffer layer 3, the P-type channel layer 6, the P-type heavily doped layer 7, and the N-type heavily doped layer 8 are group III nitride materials. The doping concentration of the P-type heavily doped layer 7 is much greater than the doping concentration of the P-type channel layer 6.

[0036] The present invention provides a plurality of vertical holes 13 in the N-type heavily doped layer 8, and the vertical holes 13 vertically penetrate the N-type heavily doped layer 8. The drain electrode 9 and the source electrode 10 are arranged on the N-type heavily doped layer 8, and can cover a number of vertical holes 13, or can avoid the vertical holes 13, or fill the vertical holes 13 in the drain electrode region and the source electrode region with the drain electrode 9 and the source electrode 10.

[0037] In this embodiment, the drain electrode 9 and the source electrode 10 are arranged at both ends of the N-type heavily doped layer 8. A gate groove 14 is arranged between the drain electrode 9 and the source electrode 10, and the N-type heavily doped layer 8, the P-type heavily doped layer 7 and part of the P-type channel layer 6 are removed from the gate groove 14, and a gate electrode 11 is arranged, and a gate dielectric layer 12 is arranged between the surface of the gate groove 14 and the gate electrode 11.

[0038] According to the above structure, the P-type heavily doped layer 7 and the N-type heavily doped layer 8 form a tunnel junction, the tunnel junction and the drain electrode 9, and the tunnel junction and the source electrode 10 form an ohmic contact, that is, an ohmic contact is formed between the drain electrode 9 and the P-type channel layer 6, and between the source electrode 10 and the P-type channel layer 6.

[0039] The gate electrode 11 forms a Schottky contact with the N-type heavily doped layer 8 or forms a metal-insulating layer-semiconductor structure with the P-type channel layer 6 , the P-type heavily doped layer 7 , and the N-type heavily doped layer 8 through a layer of insulating medium below the gate electrode 11 .

[0040] The vertical hole 13 of the present invention reduces the area of ​​the P-type channel layer 6 and the P-type heavily doped layer 7 covered by the N-type heavily doped layer 8 while retaining the tunneling junction under the drain electrode 9 and the source electrode 10, thereby enhancing the activation of the doped impurities in the P-type channel layer 6 and the P-type heavily doped layer 7, and increasing the hole concentration in the P-type channel layer 6 and the P-type heavily doped layer 8, thereby reducing the ohmic contact resistance between the drain electrode 9 and the P-type channel layer 6, and between the source electrode 10 and the P-type channel layer 10, and improving the on-state current and other performances of the P-channel MOSFET device.

[0041] Compared with the traditional P-channel MOSFET device structure with a tunnel junction, the present invention adopts a vertical hole 13 to connect the P-type heavily doped layer 7 with the outside world, avoiding the N-type heavily doped layer 8 from affecting the P-type heavily doped layer 7 during the Mg activation annealing step, thereby improving the efficiency and quality of the Mg activation annealing process.

[0042] Embodiment 2:

[0043] In the solution of Example 1, the vertical hole 13 only penetrates the N-type heavily doped layer 8 , while in this embodiment, after penetrating the N-type heavily doped layer 8 , the vertical hole 13 continues to extend downward and etches a portion of the P-type heavily doped layer 7 .

[0044] Compared with the solution of Example 1, this embodiment can further enhance the activation of the doping impurities of the P-type heavily doped layer and increase the hole concentration in the P-type heavily doped layer 7 .

[0045] Embodiment 3:

[0046] In the solution of Example 2, after the vertical hole 13 penetrates the N-type heavily doped layer 8, it continues to extend downward and etches a portion of the P-type heavily doped layer 7. In this embodiment, the vertical hole 13 penetrates the P-type heavily doped layer 7. That is, the vertical hole 13 penetrates the N-type heavily doped layer 8 and the P-type heavily doped layer 7 from top to bottom to the upper surface of the P-type channel layer 6.

[0047] Compared with the solution of Example 2, this embodiment can connect the P-type channel layer 6, the P-type heavily doped layer 7 and the outside world, avoid the N-type heavily doped layer 8 from affecting the P-type channel layer 6 and the P-type heavily doped layer 7 during the Mg activation annealing step, and improve the efficiency and quality of the Mg activation annealing process.

[0048] Embodiment 4:

[0049] In the solution of Embodiment 3, the vertical hole 13 only penetrates the N-type heavily doped layer 8 and the P-type heavily doped layer 7. In this embodiment, after the vertical hole 13 penetrates the P-type heavily doped layer 7, it continues to extend downward and etches a portion of the P-type channel layer 6. At this time, the vertical holes at both ends of the P-type channel layer 6, the P-type heavily doped layer 7 and the N-type heavily doped layer 8 extend from the surface of the N-type heavily doped layer 8 to the inside of the P-type channel layer 6, as shown in FIG. Figure 2 shown.

[0050] Compared with the solution of Embodiment 3, this embodiment can further enhance the activation of the doped impurities in the P-type channel layer and increase the hole concentration in the P-type channel layer.

[0051] Example 5

[0052] On the basis of Embodiment 4, in this embodiment, an N-type channel layer 4 and a barrier layer 5 are further provided between the buffer layer 3 and the P-type channel layer 6. The material of the N-type channel layer 4 can be selected as unintentionally doped GaN with a thickness of 10-500nm; the barrier layer 5 is provided on the N-type channel layer 4, and its material can be selected as one or more of AlGaN, InAlN, and AlN with a thickness of 3-20nm.

[0053] In the present invention, in order to realize the tunneling junction, the P-type heavily doped layer 7 and the N-type heavily doped layer 8 are heavily doped; in order to form a two-dimensional hole gas channel in the P-type channel layer 6, light doping is performed. In addition, the doping concentration of the P-type heavily doped layer 7 is preferably much greater than the doping concentration of the P-type channel layer 6.

[0054] In an optional embodiment, the material of the substrate 1 of the present invention can be selected as any one or more of Si, SiC, sapphire, and diamond; the material of the nucleation layer 2 can be selected as AlN with a thickness of 10-300nm; the material of the buffer layer 3 can be selected as AlGaN or GaN with a thickness of 0.1-5μm.

[0055] In an optional embodiment, the material of the P-type channel layer 6 of the present invention can be selected from one or more of GaN and InGaN, and the doping impurities can be selected from one or more of Mg and Zn, with a doping concentration of 1.0×10 17 -1.0×10 20 cm -3 , with a thickness of 5-30nm; the material of the P-type heavily doped layer 7 can be selected from one or more of GaN and InGaN, and the doping impurities can be selected from one or more of Mg and Zn, with a doping concentration of 1.0×10 19 -1.0×10 20 cm -3 , with a thickness of 10-100 nm; the material of the N-type heavily doped layer 8 can be selected from one or more of GaN and InGaN, and the doping impurity can be selected from Si, with a doping concentration of 1.0×10 18 -1.0×10 20 cm -3 ; The thickness is 5-100 nm. Further, the material of the P-type channel layer 6 and the material of the P-type heavily doped layer 7 may be different.

[0056] The shape of the vertical holes 13 of the present invention is not particularly limited. In an optional embodiment, the cross-section of the vertical holes 13 can be circular, elliptical or polygonal, and the spacing between adjacent vertical holes 13 is 50 nm-2 μm. Figure 3 A case where the cross section is circular is shown. Figure 1 In the structure diagram observed from the top-down perspective, the vertical hole is not blocked by the drain electrode 9 and the source electrode 10. At this time, the diameter of the vertical hole is 50nm-2μm. The present invention adopts vertical holes to connect the P-type channel layer 6 and the P-type heavily doped layer 7 with the outside world, avoiding the N-type heavily doped layer 8 from affecting the P-type channel layer 6 and the P-type heavily doped layer 7 in the activation annealing step, thereby improving the efficiency and quality of the activation annealing process.

[0057] In an optional embodiment, the material of the source electrode 10 and the material of the drain electrode 9 of the present invention may be selected as at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode 11 may be selected as at least two of Ti, Al, Ta, Mo, Au, and Ni; further, the material of the source electrode 10 may be different from the material of the gate electrode 11.

[0058] In an optional embodiment, an isolation layer is further provided between the P-type heavily doped layer 7 and the N-type heavily doped layer 8. The isolation layer can be made of one or more of AlGaN and InGaN with a thickness of 1-10 nm, which can improve the tunneling efficiency.

[0059] Example 6

[0060] This embodiment provides a method for preparing the tunneling ohmic contact P-channel GaN MOSFET device in embodiment 5, and the corresponding preparation methods of embodiments 1, 2, 3, and 4 are similar thereto. Figure 4-Figure 8 , follow the steps below:

[0061] S1, select substrate 1 and clean the surface of substrate 1; specifically, at 1000° C., introduce hydrogen into the reaction chamber to remove pollutants on the surface of substrate 1 and form a microscopic step structure on the surface of substrate 1 to facilitate the growth of subsequent epitaxial layers, such as Figure 4 shown.

[0062] S2, using a metal organic chemical vapor deposition process, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a P-type channel layer 6, a P-type heavily doped layer 7 and an N-type heavily doped layer 8 are sequentially grown on a substrate 1 to obtain a stacked structure, such as Figure 5 shown.

[0063] S3 . Doping the P-type channel layer 6 , the P-type heavily doped layer 7 and the N-type heavily doped layer 8 .

[0064] S4. Using a photolithography process, use Cl2 / BCl3 to etch on the wafer surface to remove the P-type channel layer 6, the P-type heavily doped layer 7 and the N-type heavily doped layer 8 in some areas to isolate different devices on the wafer.

[0065] S5, using photolithography technology to make vertical holes 13 at both ends of the P-type channel layer 6, the P-type heavily doped layer 7 and the N-type heavily doped layer 8, and to make a gate groove 14 between the source electrode 10 region and the drain electrode 9 region, such as Figure 6 Specifically, on the surface of the N-type heavily doped layer 8, a photoresist is spin-coated, a photolithography machine is used to expose and develop the vertical holes, and then an etcher is used to etch out the vertical holes 13, and finally the photoresist is washed off.

[0066] S6, placing the wafer in air for annealing to activate the P-type channel layer 6 and the P-type heavily doped layer 7, and then using BOE to clean the oxide on the surface of the wafer.

[0067] S7, depositing a gate dielectric layer 12 on the surface of the gate groove 14 and the surface of the N-type heavily doped layer 8, such as Figure 7 shown.

[0068] S8, making a drain electrode 9, a source electrode 10 and a gate metal. Specifically, using an electron beam evaporation device, a source electrode 10 is deposited at one end of the N-type heavily doped layer 8, a drain electrode 9 is prepared at the other end, and a gate metal is deposited on the gate groove 14 and the surface of the N-type heavily doped layer 8 to form a gate electrode 11, such as Figure 8 shown.

[0069] The preparation method provided in the embodiment of the present invention adopts a tunnel junction P-channel transistor with a hole. Compared with the traditional tunnel junction P-channel transistor, the annealing activation step of the tunnel junction P-channel transistor with a hole can be performed after the epitaxial N-type heavily doped layer 8, and the P-type channel layer 6, the P-type heavily doped layer 7 and the N-type heavily doped layer 8 can be simultaneously epitaxially grown in one process.

[0070] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application; unless otherwise clearly specified and limited, the terms "install", "connect", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediary medium, and it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0071] The device includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device; in the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device that includes the elements.

[0072] The above description is only a specific implementation mode of the present application, which is convenient for those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined in this article can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in this article, but will conform to the widest scope consistent with the principles and novel features of the application in this article.

Claims

1. A tunneling ohmic contact P-channel GaN MOSFET device structure, characterized in that: It comprises a substrate (1), a nucleation layer (2), a buffer layer (3), a P-type channel layer (6), a P-type heavily doped layer (7) and an N-type heavily doped layer (8) which are arranged in sequence from bottom to top; The N-type heavily doped layer (8) is provided with a plurality of vertical holes (13), and the vertical holes (13) penetrate the N-type heavily doped layer (8); the drain electrode (9) and the source electrode (10) are arranged on the N-type heavily doped layer (8); a gate groove (14) is arranged between the drain electrode (9) and the source electrode (10), the N-type heavily doped layer (8), the P-type heavily doped layer (7) and a portion of the P-type channel layer (6) are removed from the gate groove (14), the gate electrode (11) is arranged in the gate groove (14), and a gate dielectric layer (12) is arranged between the surface of the gate groove (14) and the gate electrode (11); The P-type heavily doped layer (7) and the N-type heavily doped layer (8) form a tunnel junction, so that ohmic contacts are formed between the drain electrode (9) and the P-type channel layer (6), and between the source electrode (10) and the P-type channel layer (6).

2. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The nucleation layer (2), buffer layer (3), P-type channel layer (6), P-type heavily doped layer (7), and N-type heavily doped layer (8) are made of group III nitride materials, and the doping concentration of the P-type heavily doped layer (7) is much greater than the doping concentration of the P-type channel layer (6).

3. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The material of the substrate (1) is any one or more of Si, SiC, sapphire, and diamond; the material of the nucleation layer (2) is AlN, the material of the buffer layer (3) is AlGaN or GaN, the material of the P-type channel layer (6) is one or more of GaN and InGaN, the doping impurities are one or more of Mg and Zn, and the doping concentration is 1.0×10 17 -1.0×10 20 cm -3 The material of the P-type heavily doped layer (7) is one or more of GaN and InGaN, and the doping impurities are one or more of Mg and Zn, with a doping concentration of 1.0×10 19 -1.0×10 20 cm -3 The material of the N-type heavily doped layer (8) is one or more of GaN and InGaN, and the doping impurity is Si, and the doping concentration is 1.0×10 18 -1.0×10 20 cm -3 .

4. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The thickness of the nucleation layer (2) is 10-300 nm; the thickness of the buffer layer (3) is 0.1-5 μm; the thickness of the P-type channel layer (6) is 5-30 nm; the thickness of the P-type heavily doped layer (7) is 10-100 nm; and the thickness of the N-type heavily doped layer (8) is 5-100 nm.

5. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The cross section of the vertical hole (13) is circular, elliptical or polygonal, the spacing between adjacent vertical holes (13) is 50nm-2μm, and when circular, the diameter is 50nm-2μm.

6. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The material of the drain electrode (9) and the material of the source electrode (10) include at least two of Ti, Al, Ta, Mo, Au, and Ni; the material of the gate electrode (11) includes at least two of Ti, Al, Ta, Mo, Au, and Ni.

7. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: An isolation layer is also provided between the P-type heavily doped layer (7) and the N-type heavily doped layer (8); the material of the isolation layer is one or more of AlGaN and InGaN, and the thickness is 1-10 nm.

8. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1 or 7, characterized in that: An N-type channel layer (4) and a barrier layer (5) are also arranged between the buffer layer (3) and the P-type channel layer (6); the material of the N-type channel layer (4) is unintentionally doped GaN, with a thickness of 10-500 nm; the barrier layer (5) is arranged on the N-type channel layer (4), and its material is one or more of AlGaN, InAlN, and AlN, with a thickness of 3-20 nm.

9. The tunneling ohmic contact P-channel GaN MOSFET device structure according to claim 1, characterized in that: The vertical hole (13) penetrates only to the upper surface of the P-type heavily doped layer (7), or penetrates the N-type heavily doped layer (8) and then etches a portion of the P-type heavily doped layer (7), or penetrates the entire P-type heavily doped layer (7) to the upper surface of the P-type channel layer (6), or penetrates the entire P-type heavily doped layer (7) and etches a portion of the P-type channel layer (6).

10. The method for preparing the tunneling ohmic contact P-channel GaN MOSFET device according to claim 1, characterized in that: The steps include: S1, sequentially growing a nucleation layer (2), a buffer layer (3), a P-type channel layer (6), a P-type heavily doped layer (7) and an N-type heavily doped layer (8) on a substrate (1); S2, doping the P-type channel layer (6), the P-type heavily doped layer (7) and the N-type heavily doped layer (8); S3, isolate the device; S4, using a photolithography process to form a vertical hole (13) on the N-type heavily doped layer (8), or the N-type heavily doped layer (8) and the P-type heavily doped layer (7), or the N-type heavily doped layer (8), the P-type heavily doped layer (7) and the P-type channel layer (6), and to form a gate groove (14) between the source electrode region and the drain electrode region; S5, annealing to activate the P-type channel layer (6) and the P-type heavily doped layer (7); S6, depositing a gate dielectric layer (12) on the surface of the gate groove (14) and the surface of the N-type heavily doped layer (8); S7, preparing a source electrode (9) and a drain electrode (10) at both ends of the surface of the N-type heavily doped layer (8), and depositing a gate metal on the surface of the gate dielectric layer (12) to form a gate electrode (11).

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