Digital clock frequency multiplier circuit and digital clock frequency multiplier signal generation method

Abstract

The invention provides a digital clock frequency multiplication circuit and a digital clock frequency multiplication signal generation method. The digital clock frequency multiplication circuit comprises a frequency multiplication unit; the first numerical control delay chain is used for delaying a reference clock signal input to the frequency multiplication unit; the second numerical control delay chain is used for delaying the clock signal output by the frequency multiplication unit; the first digital calibration unit and the second digital calibration unit are used for respectively calibrating the delay time of the first numerical control delay chain and the delay time of the second numerical control delay chain according to an output signal of the second numerical control delay chain, and after calibration, the duty ratio of a reference clock signal input to the frequency multiplication unit can be stabilized at a first reference value. According to the invention, through feedback control of the delay time of the two numerical control delay chains by the two digital calibration units, stable and low-jitter frequency multiplication clock output is realized.

Description

Technical Field

[0001] The present application relates to the technical field of digital circuits, and in particular to a digital clock frequency multiplication circuit and a method for generating a digital clock frequency multiplication signal. Background Art

[0002] Digital clock frequency multiplication circuit is a commonly used circuit module in integrated circuits such as Universal Asynchronous Receiver / Transmitter (UART) interface and Phase-locked loop (PLL). For the Universal Asynchronous Receiver / Transmitter (UART) interface, the digital clock frequency multiplication circuit can increase the transmission baud rate of the Universal Asynchronous Receiver / Transmitter; and for the Phase-locked Loop (PLL) circuit, adding a digital clock frequency multiplication circuit to the input path of the reference clock can make the crystal oscillator frequency supported by the Phase-locked Loop (PLL) more diverse, thereby improving the flexibility and reusability of the overall circuit system.

[0003] However, the digital clock multiplication circuit may generate jitter during operation, that is, the frequency of the clock signal is unstable, which may cause instability and performance problems in other components in the system. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a digital clock frequency multiplication circuit and a digital clock frequency multiplication signal generation method, aiming to achieve low-jitter digital clock frequency multiplication operation.

[0005] According to a first aspect of the present application, a digital clock frequency multiplication circuit is provided, comprising:

[0006] A frequency multiplication unit performs frequency multiplication processing on a reference clock signal to generate a frequency multiplied clock signal;

[0007] a first digitally controlled delay chain, delaying the rising edge and the falling edge of the frequency-multiplied clock signal according to a first control code to generate a reference clock signal;

[0008] A second digitally controlled delay chain delays the rising edge or the falling edge of the initial reference clock signal according to a second control code;

[0009] a first digital calibration unit, generating the first control code according to the multiplied clock signal and the reference clock signal, wherein the first control code is used to calibrate the delay time of the first digitally controlled delay chain so as to maintain the clock period of the reference clock signal at a predetermined multiple of the clock period of the reference clock signal;

[0010] A second digital calibration unit generates the second control code according to the reference clock signal and the reference clock signal, wherein the second control code is used to calibrate the delay time of the second digitally controlled delay chain to stabilize the duty cycle of the reference clock signal input to the frequency multiplication unit at a first reference value.

[0011] Optionally, the first digital calibration unit is configured to:

[0012] The multiplied clock signal is sampled according to the reference clock signal, and the first control code is increased when one of the high level and the low level of the multiplied clock signal is sampled, and the first control code is decreased when the other of the high level and the low level of the multiplied clock signal is sampled.

[0013] Optionally, the second digital calibration unit is configured to:

[0014] The reference clock signal is sampled according to the base clock signal, and the second control code is increased when one of the high level and the low level of the reference clock signal is sampled, and the second control code is decreased when the other of the high level and the low level of the reference clock signal is sampled.

[0015] Optionally, the delay duration of the first digitally controlled delay chain for the rising edge and the falling edge of the frequency-multiplied clock signal is negatively correlated with the value of the first control code.

[0016] Optionally, the first digitally controlled delay chain is configured to delay the rising edge and the falling edge of the frequency-multiplied clock signal by the same time.

[0017] Optionally, the second control code includes a sign bit and a data bit;

[0018] The second numerically controlled delay chain is configured as:

[0019] When the sign bit of the second control code is positive, delaying the rising edge of the reference clock signal;

[0020] When the sign bit of the second control code is negative, delaying the falling edge of the reference clock signal;

[0021] The delay time length of the second digitally controlled delay chain for the rising edge or the falling edge of the reference clock signal is proportional to the size of the data bit of the second control code.

[0022] Optionally, an initial delay time of the first digitally controlled delay chain for the frequency-doubled clock signal is greater than a pulse width time of the frequency-doubled clock signal, and is less than a high-level duration time and a low-level duration time of the reference clock signal.

[0023] Optionally, a bandwidth ratio of feedback loops corresponding to the first digital calibration unit and the second digital calibration unit is greater than or equal to 8:1.

[0024] Optionally, the first digital calibration unit and the second digital calibration unit increase or decrease the corresponding control code based on a shift operation;

[0025] The difference between the number of shift bits of the first digital calibration unit and the second digital calibration unit when performing a shift operation is at least 3 bits.

[0026] Optionally, the first digital calibration unit includes:

[0027] A calibration input terminal connected to the output terminal of the frequency multiplication unit to receive the frequency multiplication clock signal;

[0028] A clock input terminal connected to the output terminal of the first digitally controlled delay chain, receiving the reference clock signal;

[0029] The output end is connected to the calibration control end of the first numerically controlled delay chain and outputs the first control code.

[0030] Optionally, the second digital calibration unit includes:

[0031] A calibration input terminal, receiving the reference clock signal;

[0032] A clock input terminal connected to the output terminal of the first digitally controlled delay chain, receiving the reference clock signal;

[0033] The output end is connected to the calibration control end of the second digital control delay chain, and outputs the second control code.

[0034] Optionally, the first digital calibration unit includes:

[0035] A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the first digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the first digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the multiplied clock signal according to the reference clock signal;

[0036] A reversible counter, whose clock input terminal is connected to the clock input terminal of the first digital calibration unit, and whose control terminal is connected to the output terminal of the D flip-flop, and the reversible counter is used to perform addition counting or subtraction counting according to the sampling result of the D flip-flop;

[0037] A shift register, wherein a clock input end is connected to a clock input end of the first digital calibration unit, a data input end is connected to an output end of the reversible counter, an output end of the shift register is connected to an output end of the first digital calibration unit, and the shift register is used to perform a shift operation on an output result of the reversible counter and output the first control code.

[0038] Optionally, the first digital calibration unit includes:

[0039] A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the first digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the first digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the multiplied clock signal according to the reference clock signal;

[0040] A decoding circuit, whose input end is connected to the output end of the D flip-flop, and the decoding circuit is used to compile the output level of the D flip-flop into a digital signal representing +1 or -1;

[0041] an integration circuit, wherein a first input terminal is connected to the output terminal of the decoding circuit, a second input terminal is connected to the clock input terminal of the first digital calibration unit, and the integration circuit is used to perform an integration operation on the output result of the decoding circuit;

[0042] A shift register, wherein a clock input end is connected to a clock input end of the first digital calibration unit, a data input end is connected to an output end of the integration circuit, an output end of the shift register is connected to an output end of the first digital calibration unit, and the shift register is used to perform a shift operation on an output result of the integration circuit and output the first control code.

[0043] Optionally, the second digital calibration unit includes:

[0044] A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the second digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the second digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the reference clock signal according to the reference clock signal;

[0045] A reversible counter, whose clock input terminal is connected to the clock input terminal of the second digital calibration unit, and whose control terminal is connected to the output terminal of the D flip-flop, wherein the reversible counter is used to perform addition counting or subtraction counting according to the sampling result of the D flip-flop;

[0046] A shift register, wherein a clock input end is connected to a clock input end of the second digital calibration unit, a data input end is connected to an output end of the reversible counter, an output end of the shift register is connected to an output end of the second digital calibration unit, and the shift register is used to perform a shift operation on an output result of the reversible counter and output the second control code.

[0047] Optionally, the second digital calibration unit includes:

[0048] A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the second digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the second digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the reference clock signal according to the reference clock signal;

[0049] A decoding circuit, whose input end is connected to the output end of the D flip-flop, and the decoding circuit is used to compile the output level of the D flip-flop into a digital signal representing +1 or -1;

[0050] an integration circuit, wherein a first input terminal is connected to the output terminal of the decoding circuit, a second input terminal is connected to the clock input terminal of the second digital calibration unit, and the integration circuit is used to perform an integration operation on the output result of the decoding circuit;

[0051] A shift register, a clock input end connected to the clock input end of the second digital calibration unit, a data input end connected to the output end of the integration circuit, an output end of the shift register connected to the output end of the second digital calibration unit, and the shift register is used to perform a shift operation on the output result of the integration circuit and output the second control code.

[0052] Optionally, the first digitally controlled delay chain comprises:

[0053] A first transistor and a second transistor connected in series between a power supply terminal and a reference ground, wherein control terminals of the first transistor and the second transistor receive the multiplied frequency clock signal;

[0054] a third transistor, a control terminal connected to the drain terminal of the first transistor, a source terminal and a drain terminal of the third transistor receiving the first control code, wherein the third transistor is not a single transistor, but a transistor array controlled by the first control code, and operates in a variable capacitance mode, and a total capacitance value thereof is inversely proportional to the value of the first control code, that is, the larger the value of the first control code, the smaller the capacitance;

[0055] A fourth transistor and a fifth transistor connected in series between a power supply terminal and a reference ground, wherein control terminals of the fourth transistor and the fifth transistor are connected to a drain terminal of the first transistor;

[0056] A drain terminal of the fourth transistor is connected to an output terminal of the first digitally controlled delay chain.

[0057] Optionally, the second digitally controlled delay chain comprises:

[0058] A sixth transistor, a first variable resistor, a second variable resistor and a seventh transistor are sequentially connected in series between a power supply terminal and a reference ground, and control terminals of the sixth transistor and the seventh transistor receive the reference clock signal;

[0059] an eighth transistor and a ninth transistor connected in series between the drain terminal of the sixth transistor and the drain terminal of the seventh transistor, wherein control terminals of the eighth transistor and the ninth transistor receive a sign bit of the second control code, and the drain terminal of the eighth transistor is connected to a first node, which is a common connection node of the first resistor and the second resistor;

[0060] The control ends of the first variable resistor and the second variable resistor receive the data bit of the second control code, and the resistance values ​​of the first variable resistor and the second variable resistor are positively correlated with the absolute value of the data bit of the second control code;

[0061] a tenth transistor and an eleventh transistor connected in series between a power supply terminal and a reference ground, wherein control terminals of the tenth transistor and the eleventh transistor are connected to the first node;

[0062] A drain terminal of the tenth transistor is connected to an output terminal of the second digitally controlled delay chain.

[0063] Optionally, the frequency-multiplied clock signal is a double-frequency clock signal;

[0064] The first benchmark value is 50%;

[0065] The predetermined multiple is 0.5.

[0066] Optionally, the frequency multiplication unit includes:

[0067] a delay unit, an input end of which is connected to an output end of the second digitally controlled delay chain;

[0068] An XOR gate logic circuit has a first input end connected to the output end of the delay unit, a second input end connected to the output end of the second digitally controlled delay chain, and an output end of the XOR gate logic circuit outputs the multiplied clock signal.

[0069] According to a second aspect of the present application, a method for generating a digital clock frequency multiplication signal is provided, comprising:

[0070] Performing a second delay process on a rising edge or a falling edge of an initial reference clock signal;

[0071] Performing frequency multiplication processing on the reference clock signal after delay processing to generate a frequency multiplied clock signal;

[0072] Performing a first delay process on the rising edge and the falling edge of the frequency-multiplied clock signal to generate a reference clock signal;

[0073] The delay time during the first delay processing is calibrated according to the reference clock signal and the multiplied clock signal, and the delay time during the second delay processing is calibrated according to the reference clock signal and the reference clock signal, so as to maintain the clock period of the reference clock signal at a predetermined multiple of the clock period of the reference clock signal and stabilize the duty cycle of the reference clock signal at a first reference value.

[0074] Optionally, the frequency-multiplied clock signal is a double-frequency clock signal;

[0075] The first benchmark value is 50%;

[0076] The predetermined multiple is 0.5.

[0077] The beneficial effects of this application include at least:

[0078] The embodiment of the present application adds two digital calibration units and two digitally controlled delay chains on the basis of the existing frequency multiplication circuit (i.e., the frequency multiplication unit), wherein the second digitally controlled delay chain delays the reference clock signal input to the frequency multiplication unit, and the first digitally controlled delay chain delays the clock signal output by the frequency multiplication unit. The first digital calibration unit and the second digital calibration unit calibrate the delay time of the first digitally controlled delay chain and the delay time of the second digitally controlled delay chain respectively according to the output signal of the first digitally controlled delay chain, so that after calibration, the duty cycle of the reference clock signal input to the frequency multiplication unit can be stabilized at the required first reference value, effectively avoiding the clock jitter of the frequency multiplication clock signal output by the frequency multiplication unit, and realizing a stable and low-jitter frequency multiplication clock output. At the same time, since the scheme of the present application mainly realizes the delay calibration of the corresponding delay chain through feedback control of the digital calibration circuit of the all-digital logic, the system has a simple structure, occupies a small area, and has good accuracy, reliability and robustness. By controlling the delay accuracy of the delay chain, the clock jitter of the doubled frequency generated by the frequency multiplication circuit can be controlled within the required range, and the jitter caused by changes in ambient temperature and power supply voltage can be automatically repaired.

[0079] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 A schematic diagram showing a digital clock frequency multiplication circuit system;

[0081] Figure 2 Show Figure 1 Schematic diagram of the clock jitter problem in the digital clock multiplication circuit;

[0082] Figure 3 A schematic diagram of an implementation of a digital clock frequency multiplication circuit provided according to an embodiment of the present application is shown;

[0083] Figure 4 Show Figure 3 A schematic diagram of an implementation of the first digital calibration unit;

[0084] Figure 5 Show Figure 3 A schematic diagram of an implementation of the second digital calibration unit;

[0085] Figure 6 Show Figure 3 Another implementation schematic diagram of the first digital calibration unit;

[0086] Figure 7 Show Figure 3 Another implementation schematic diagram of the second digital calibration unit;

[0087] Figure 8 Show Figure 3 A schematic diagram of an implementation of a delay unit in a first numerically controlled delay chain;

[0088] Fig. 9 Show Figure 3 A schematic diagram of an implementation of a delay unit in a second numerically controlled delay chain;

[0089] Fig.10 Show Figure 3 The timing diagram of the digital clock multiplication circuit in the initial stage;

[0090] Fig.11 A timing diagram showing calibration results of a digitally controlled delay chain when the duty cycle of a reference clock signal is greater than 50%;

[0091] Fig.12 A timing diagram showing calibration results of a digitally controlled delay chain when the duty cycle of a reference clock signal is less than 50%;

[0092] Fig.13 A schematic diagram showing simulation results of a digital clock frequency multiplication circuit provided according to an embodiment of the present application at a predetermined resolution of a digitally controlled delay chain;

[0093] Fig.14 A schematic flow chart of a method for generating a digital clock frequency multiplication signal provided in accordance with an embodiment of the present application is shown. DETAILED DESCRIPTION

[0094] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0095] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0096] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" herein is a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0097] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0098] See also Figure 1The figure shows a digital clock frequency multiplication circuit system based on XOR gate and delay chain in the prior art. The system includes a delay circuit 11 and an XOR gate logic circuit 12. The period of the input clock signal Fin of the system is T. After passing through the delay circuit 11, such as the delay chain (Delay-line), a delayed signal Fin_D is obtained. The delay amount of the delay circuit 11 is t. After the XOR gate logic circuit 12 performs an XOR operation on the input clock signal Fin and the delay signal Fin_D, a doubled output clock signal Fout is obtained. The pulse width of the output doubled clock signal Fout is equal to the delay time length of the delay circuit 11. The circuit system in the above implementation scheme is entirely composed of digital gate circuits, with a simple structure and good robustness, and is particularly suitable for situations with low input frequencies. However, this implementation scheme requires that the duty cycle of the input clock signal Fin is accurately 50%, otherwise the following will occur: Figure 2 The clock jitter problem shown in the figure is that the high level duration tEXTH and the low level duration tEXTL of the input clock signal Fin are not equal, which makes the period lengths of two adjacent clock cycles of the output double frequency clock signal Fout unequal. Therefore, when the signal input is Figure 1 Before implementing the digital clock frequency multiplication circuit system shown, the input clock signal must be calibrated to a 50% duty cycle.

[0099] Figure 3 The implementation diagram of the digital clock frequency multiplication circuit provided in the embodiment of the present application is shown, and the digital clock frequency multiplication circuit includes: a frequency multiplication unit 31, a first digitally controlled delay chain 34, a second digitally controlled delay chain 35, a first digital calibration unit 36 ​​and a second digital calibration unit 37.

[0100] The frequency multiplication unit 31 performs frequency multiplication processing on the reference clock signal Fin1 output by the second digitally controlled delay chain 35 to generate a frequency multiplied clock signal. The first digitally controlled delay chain 34 delays the rising edge and the falling edge of the frequency multiplied clock signal CK according to the first control code Dout1 to generate the reference clock signal CKD. The second digitally controlled delay chain 35 delays the rising edge or the falling edge of the initial reference clock signal Fin0 according to the second control code Dout2. The first digital calibration unit 36 ​​generates a first control code Dout1 according to the frequency multiplied clock signal CK and the reference clock signal CKD. The first control code Dout1 is used to calibrate the delay time of the first digitally controlled delay chain 34 to maintain the clock period of the reference clock signal CKD at a predetermined multiple of the clock period of the initial reference clock signal Fin0. The second digital calibration unit 37 generates a second control code Dout2 based on the initial reference clock signal Fin0, the reference clock signal Fin1 delayed by the second digitally controlled delay chain 35, and the reference clock signal CKD. The second control code Dout2 is used to calibrate the delay time of the second digitally controlled delay chain 35 to stabilize the duty cycle of the reference clock signal Fin1 input to the frequency multiplication unit 31 at a first reference value.

[0101] Specifically, the frequency multiplication unit 31 includes an input end and an output end; the first digitally controlled delay chain 34 and the second digitally controlled delay chain 35 each include an input end, a calibration control end and an output end; the first digital calibration unit 36 ​​and the second digital calibration unit 37 each include a calibration input end, a clock input end and an output end. In this embodiment, the input end of the second digitally controlled delay chain 35 receives the initial reference clock signal Fin0, and the output end of the second digitally controlled delay chain 35 is respectively connected to the input end of the frequency multiplication unit 31 and the calibration input end of the second digital calibration unit 37, so as to output the delayed reference clock signal Fin1 to the input end of the frequency multiplication unit 31 and the calibration input end of the second digital calibration unit 37, respectively; the output end of the frequency multiplication unit 31 is respectively connected to the input end of the first digitally controlled delay chain 34 and the calibration input end of the first digital calibration unit 36, so as to output the frequency multiplication clock signal CK to the input end of the first digitally controlled delay chain 34 and the calibration input end of the first digital calibration unit 36, respectively. input terminal; the output terminal of the first digital controlled delay chain 34 is connected to the clock input terminal of the first digital calibration unit 36 ​​and the second digital calibration unit 37 respectively, so as to output the reference clock signal CKD to the clock input terminals of the first digital calibration unit 36 ​​and the second digital calibration unit 37 respectively; the output terminal of the first digital calibration unit 36 ​​is connected to the calibration control terminal of the first digital controlled delay chain 34, so as to output the first control code Dout1 to the calibration control terminal of the first digital controlled delay chain 34; the output terminal of the second digital calibration unit 37 is connected to the calibration control terminal of the second digital controlled delay chain 35, so as to output the second control code Dout2 to the calibration control terminal of the second digital controlled delay chain 35.

[0102] exist Figure 3 In the example shown, the frequency multiplication unit 31 specifically includes: a delay unit 32 and an XOR gate logic circuit 33, wherein the input end of the delay unit 32 is connected to the input end of the frequency multiplication unit 31 (i.e., the output end of the second digitally controlled delay chain); the first input end of the XOR gate logic circuit 33 is connected to the output end of the delay unit 32, the second input end of the XOR gate logic circuit 33 is connected to the input end of the frequency multiplication unit 31 (i.e., the output end of the second digitally controlled delay chain), and the output end of the XOR gate logic circuit 33 is connected to the output end of the frequency multiplication unit 31 to output a multiplied clock signal.

[0103] It should be noted that Figure 3 The digital clock frequency multiplication circuit shown is an example of a frequency multiplication unit 31 performing a double frequency multiplication process on a reference clock signal Fin1. Figure 3 In the example shown, the frequency multiplier CK output by the frequency multiplier unit 31 is a double frequency clock signal of the reference clock signal Fin1, that is, the frequency fout of the frequency multiplier CK is equal to twice the frequency fin of the reference clock signal Fin1, which can be expressed as fout=2*fin. At this time, the first reference value is, for example, 50%, and the predetermined multiple is, for example, 0.5.

[0104] Of course, the present application solution can also be extended to obtain a multi-frequency clock signal, for example Figure 3 The output end of the frequency multiplication unit 31 shown is connected to one or more cascaded extended frequency multiplication units, each of which includes a delay unit of the extended frequency multiplication unit and an XOR gate logic circuit.

[0105] The first digital calibration unit 36 ​​is configured to: sample the multiplied clock signal CK according to the reference clock signal CKD, and increase the first control code Dout1 when one of the high level and the low level of the multiplied clock signal CK is sampled, and decrease the first control code Dout1 when the other of the high level and the low level of the multiplied clock signal CK is sampled. For example, the first control code Dout1 is increased when the high level of the multiplied clock signal CK is sampled, and the first control code Dout1 is decreased when the low level of the multiplied clock signal CK is sampled.

[0106] The delay time of the rising edge and the falling edge of the multiplied clock signal CK by the first digitally controlled delay chain 34 is negatively correlated with the value of the first control code Dout1. For example, the first digitally controlled delay chain 34 is configured to: when the value of the first control code Dout1 increases, reduce the delay time of the rising edge and the falling edge of the multiplied clock signal CK; when the value of the first control code Dout1 decreases, increase the delay time of the rising edge and the falling edge of the multiplied clock signal CK.

[0107] Furthermore, when the first digitally controlled delay chain 34 performs delay processing on the frequency-multiplied clock signal CK, the rising edge and the falling edge of the frequency-multiplied clock signal CK are delayed by the same time according to the first control code Dout1 .

[0108] The second digital calibration unit 37 is configured to sample the reference clock signal Fin1 according to the reference clock signal CKD, and increase the second control code Dout2 when one of the high level and the low level of the reference clock signal Fin1 is sampled, and decrease the second control code Dout2 when the other of the high level and the low level of the reference clock signal Fin1 is sampled. For example, the second control code Dout2 is increased when the high level of the reference clock signal Fin1 is sampled, and the second control code Dout2 is decreased when the low level of the reference clock signal Fin1 is sampled.

[0109] In this embodiment, the second control code Dout2 includes a sign bit (denoted as sigal) and a data bit (denoted as digital). The second digitally controlled delay chain 35 is configured to: when the sign bit sigal of the second control code Dout2 is positive, delay the rising edge of the reference clock signal Fin1; when the sign bit sigal of the second control code Dout2 is negative, delay the falling edge of the reference clock signal Fin1, and the delay time of the rising edge or falling edge of the reference clock signal Fin1 by the second digitally controlled delay chain 35 is proportional to the size of the data bit digital of the second control code Dout2.

[0110] The first digital calibration unit 36 ​​and the second digital calibration unit 37 have the same structure.

[0111] In some embodiments, the first digital calibration unit 36 ​​and the second digital calibration unit 37 both include a D flip-flop, a reversible counter, and a shift register, so that the high level and the low level of the input signal are sampled by the D flip-flop, the sampling result is counted and counted by the reversible counter, and the counting and statistical result is shifted by the shift register to obtain the corresponding control code.

[0112] In these embodiments, when specifically implemented, Figure 4As shown, the first digital calibration unit 36 ​​includes a D flip-flop 41 , an up / down counter 42 and a shift register 43 . Among them, the data input end of the D flip-flop 41 is connected to the calibration input end of the first digital calibration unit 36 ​​to receive the multiplied clock signal CK, the clock input end of the D flip-flop 41 is connected to the clock input end of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, and the D flip-flop 41 is used to sample the high level and low level of the multiplied clock signal CK according to the reference clock signal CKD; the clock input end of the reversible counter 42 is connected to the clock input end of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, the control end of the reversible counter 42 is connected to the output end of the D flip-flop 41, and the reversible counter 42 is used to perform corresponding addition counting or subtraction counting according to the sampling result of the D flip-flop 41; the clock input end of the shift register 43 is connected to the clock input end of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, the data input end of the shift register 43 is connected to the output end of the reversible counter 42, the output end of the shift register 43 is connected to the output end of the first digital calibration unit 36, and the shift register 43 is used to perform a shift operation on the output result of the reversible counter 42 to output the first control code Dout1.

[0113] like Figure 5 As shown, the second digital calibration unit 37 includes: a D flip-flop 51 , an up / down counter 52 and a shift register 53 . Among them, the data input end of the D flip-flop 51 is connected to the calibration input end of the second digital calibration unit 37 to receive the reference clock signal Fin1, the clock input end of the D flip-flop 51 is connected to the clock input end of the second digital calibration unit 37 to receive the reference clock signal CKD, and the D flip-flop 51 is used to sample the high level and low level of the reference clock signal Fin1 according to the reference clock signal CKD; the clock input end of the reversible counter 52 is connected to the clock input end of the second digital calibration unit 37 to receive the reference clock signal CKD, the control end of the reversible counter 52 is connected to the output end of the D flip-flop 51, and the reversible counter 52 is used to perform corresponding addition counting or subtraction counting according to the sampling result of the D flip-flop 51; the clock input end of the shift register 53 is connected to the clock input end of the second digital calibration unit 37 to receive the reference clock signal CKD, the data input end of the shift register 53 is connected to the output end of the reversible counter 52, the output end of the shift register 53 is connected to the output end of the second digital calibration unit 37, and the shift register 53 is used to perform a shift operation on the output result of the reversible counter 52 to output the second control code Dout2.

[0114] In these embodiments, the D flip-flops in the first digital calibration unit 36 ​​and the second digital calibration unit 37 sample and output the signals received at their data input terminals at the rising edge of the reference clock signal CKD, for example.

[0115] The up / down counters in the first digital calibration unit 36 ​​and the second digital calibration unit 37 are configured, for example, to perform addition counting when the corresponding D flip-flop outputs a high level, and to perform subtraction counting when the corresponding D flip-flop outputs a low level.

[0116] The shift registers in the first digital calibration unit 36 ​​and the second digital calibration unit 37 increase or decrease the corresponding control code based on the shift operation, for example, the output result of the reversible counter is right shifted by K bits to implement a division by 2K operation, where K is a non-zero integer.

[0117] In some preferred examples, in order to avoid the calibration processes of the first digital calibration unit 36 ​​and the second digital calibration unit 37 from influencing each other, it is necessary to set the bandwidth ratio of the feedback loops corresponding to the first digital calibration unit 36 ​​and the second digital calibration unit 37 to be greater than or equal to 8:1, for example, the shift registers in the first digital calibration unit 36 ​​and the second digital calibration unit 37 are set to differ by at least 3 bits in the number of shift bits when performing a shift operation.

[0118] In other embodiments, the first digital calibration unit 36 ​​and the second digital calibration unit 37 both include a D flip-flop, a decoding circuit, an integration circuit, and a shift register, so that the D flip-flop is used to sample the high level and low level of the input signal, and the decoding circuit is used to compile the high and low levels of the output of the D flip-flop representing the sampling result into a digital signal representing +1 or -1, and then the integration circuit and the shift register are used to perform integration and shift operations to obtain the corresponding control code. The functions of the first digital calibration unit 36 ​​and the second digital calibration unit 37 in this embodiment are basically the same as those of the aforementioned embodiment.

[0119] In these embodiments, when specifically implemented, Figure 6As shown, the first digital calibration unit 36 ​​includes: a D flip-flop 61, a decoding circuit 62, an integration circuit 63 and a shift register 64. Among them, the data input end of the D flip-flop 61 is connected to the calibration input end of the first digital calibration unit 36 ​​to receive the multiplied clock signal CK, the clock input end of the D flip-flop 61 is connected to the clock input end of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, and the D flip-flop 61 is used to sample the high level and low level of the multiplied clock signal CK according to the reference clock signal CKD; the input end of the decoding circuit 62 is connected to the output end of the D flip-flop 61, and the decoding circuit 62 is used to compile the output level of the D flip-flop 61 into a digital signal representing +1 or -1; the first input end of the integration circuit 63 is connected to the output end of the decoding circuit 62 The second input terminal of the integration circuit 63 is connected to the clock input terminal of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, and the integration circuit 63 is used to perform an integration operation on the output result of the decoding circuit 62; the clock input terminal of the shift register 64 is connected to the clock input terminal of the first digital calibration unit 36 ​​to receive the reference clock signal CKD, the data input terminal of the shift register 64 is connected to the output terminal of the integration circuit 63, and the output terminal of the shift register 64 is connected to the output terminal of the first digital calibration unit 36. The shift register 64 is used to perform a shift operation on the output result of the integration circuit 63 to output the first control code Dout1.

[0120] like Figure 7 As shown, the second digital calibration unit 37 includes: a D flip-flop 71, a decoding circuit 72, an integration circuit 73 and a shift register 74. Among them, the data input end of the D flip-flop 71 is connected to the calibration input end of the second digital calibration unit 37 to receive the reference clock signal Fin1, the clock input end of the D flip-flop 71 is connected to the clock input end of the second digital calibration unit 37 to receive the reference clock signal CKD, and the D flip-flop 71 is used to sample the high level and low level of the reference clock signal Fin1 according to the reference clock signal CKD; the input end of the decoding circuit 72 is connected to the output end of the D flip-flop 71, and the decoding circuit 72 is used to compile the output level of the D flip-flop 71 into a digital signal representing +1 or -1; the first input end of the integration circuit 73 is connected to the output end of the decoding circuit 72 The second input terminal of the integration circuit 73 is connected to the clock input terminal of the second digital calibration unit 37 to receive the reference clock signal CKD. The integration circuit 73 is used to perform an integration operation on the output result of the decoding circuit 72; the clock input terminal of the shift register 74 is connected to the clock input terminal of the second digital calibration unit 37 to receive the reference clock signal CKD, the data input terminal of the shift register 74 is connected to the output terminal of the integration circuit 73, and the output terminal of the shift register 74 is connected to the output terminal of the second digital calibration unit 37. The shift register 74 is used to perform a shift operation on the output result of the integration circuit 73 to output a second control code Dout2.

[0121] Further, Figure 8 A schematic diagram of an implementation of the first digital control delay chain 34 provided according to an embodiment of the present application is shown. Figure 8 In the example shown, the first digital control delay chain 34 includes: transistor Q11, transistor Q12, transistor Q13, transistor Q14 and transistor Q15. Among them, transistor Q11 and transistor Q12 are connected in series between the power supply terminal VCC and the reference ground, and the control terminals of transistor Q11 and transistor Q12 receive the multiplied clock signal CK; the control terminal of transistor Q13 is connected to the drain terminal of transistor Q11, and the source terminal and drain terminal of transistor Q13 receive the first control code Dout1; transistor Q14 and transistor Q15 are connected in series between the power supply terminal VCC and the reference ground, and the control terminals of transistor Q14 and transistor Q15 are connected to the drain terminal of transistor Q11; the drain terminal of transistor Q14 is connected to the output terminal of the first digital control delay chain 34, and outputs the reference clock signal CKD.

[0122] It should be noted that, in the present embodiment, transistor Q13 is not a single transistor, but a transistor array controlled by the first control code Dout1. The transistor array operates in a variable capacitance mode, and its total capacitance value is inversely proportional to the value of the first control code Dout1, that is, the larger the value of the first control code Dout1, the smaller the equivalent capacitance of the transistor array.

[0123] Optionally, in Figure 8 In the example shown, transistor Q11 and transistor Q14 are, for example, PMOS transistors, and transistor Q12, transistor Q13, and transistor Q14 are, for example, NMOS transistors. Of course, in other embodiments of the present application, transistor Q11, transistor Q12, transistor Q13, transistor Q14, and transistor Q15 may also be other types of combinations, as long as they can achieve the same function.

[0124] Further, Fig. 9 A schematic diagram of an implementation of the second digital control delay chain 35 provided according to an embodiment of the present application is shown. Fig. 9In the example shown, the second digital control delay chain 35 includes: transistor Q21, transistor Q22, transistor Q23, transistor Q24, transistor Q25, transistor Q26, variable resistor R1 and variable resistor R2. Among them, transistor Q21, variable resistor R1, variable resistor R2 and transistor Q22 are connected in series between the power supply terminal VCC and the reference ground in sequence, and the control terminals of transistor Q21 and transistor Q22 receive the initial reference clock signal Fin0; transistor Q23 and transistor Q24 are connected in series between the drain terminal of transistor Q21 and the drain terminal of transistor Q22, and the control terminals of transistor Q23 and transistor Q24 receive the sign bit sigal of the second control code Dout2, and the drain terminal of transistor Q23 is connected to the first node A, and the first node A is the variable resistor R1 and the variable resistor The control terminals of the variable resistor R1 and the variable resistor R2 receive the data bit digital of the second control code Dout2, and the resistance values ​​of the variable resistor R1 and the variable resistor R2 are positively correlated with the absolute value of the data bit digital of the second control code Dout2; the transistor Q25 and the transistor Q26 are connected in series between the power supply terminal VCC and the reference ground, and the control terminals of the transistor Q25 and the transistor Q26 are connected to the first node A; the drain terminal of the transistor Q25 is connected to the output terminal of the second digital control delay chain 35, and outputs the reference clock signal Fin1.

[0125] Optionally, in Fig. 9 In the example shown, transistor Q21, transistor Q23 and transistor Q25 are, for example, PMOS transistors, and transistor Q22, transistor Q24 and transistor Q26 are, for example, NMOS transistors. Of course, in other embodiments of the present application, transistor Q21, transistor Q22, transistor Q23, transistor Q24, transistor Q25 and transistor Q26 may also be other types of combinations, as long as they can achieve the same function.

[0126] For example, the following example is taken in which the first digital calibration unit 36 ​​and the second digital calibration unit 37 both include a D flip-flop, a reversible counter, and a shift register, and the first reference value is equal to 50%, and the predetermined multiple is equal to 0.5. Figure 3 , Figure 4 , Figure 5 , Fig.10 , Fig.11 , Fig.12 and Fig.13 The working process of the digital clock frequency multiplication circuit provided in the embodiment of the present application is described in detail.

[0127] In the initial stage of operation, the digital part of the digital clock frequency multiplication circuit is initialized, and the frequency multiplication unit 31 performs frequency multiplication processing on the reference clock signal Fin1 output by the second digital control delay chain 35 to generate a frequency multiplied clock signal CK. The initial delay time of the frequency multiplied clock signal CK after passing through the first digital control delay chain 34 is greater than the pulse width time of the frequency multiplied clock signal CK, and is less than the high level duration and low level duration of the reference clock signal Fin1.

[0128] In the initial stage of the circuit operation, the D flip-flop 41 of the first digital calibration unit 36 ​​samples the low level of the multiplied clock signal CK under the action of the reference clock signal CKD, such as Fig.10 As shown by the signal Kout1, during the initial calibration process of the delay time of the first digitally controlled delay chain 34, the reversible counter 42 of the first digital calibration unit 36 ​​begins to enter the subtraction counting process, and the counting result shifted and output by the shift register 43 will continue to decrease, thereby controlling the value of the first control code Dout1 to continue to decrease, and controlling the delay time of the first digitally controlled delay chain 34 to continue to increase, until the delay time of the first digitally controlled delay chain 34 increases to between the high level duration and the low level duration of the reference clock signal Fin1;

[0129] Before the initial calibration of the delay time of the first digital control delay chain 34 is completed, the D flip-flop 51 in the second digital calibration unit 37 will alternately sample the high level and the low level of the reference clock signal Fin0 under the action of the reference clock signal CKD. At this time, the up / down counter 52 of the second digital calibration unit 37 will alternately perform the process of adding 1 and subtracting 1. Fig.10 As shown in the signal Kout2, after being shifted and output by the shift register 53, the second control code Dout2 output by the second digital calibration unit 37 will remain unchanged or alternately jump on adjacent integers;

[0130] After the initial calibration of the delay time of the first digitally controlled delay chain 34 is completed, no matter what the duty cycle of the reference clock signal Fin0 input to the second digitally controlled delay chain 35 is, the signal Kout1 of the up / down counter 42 of the first digital calibration unit 36 ​​will alternate between plus 1 and minus 1, such as Fig.11 and Fig.12 As shown in the middle signal Kout1;

[0131] At this time, if the duty cycle of the reference clock signal Fin0 input to the second digital control delay chain 35 is greater than the first reference value (such as 50%), the D flip-flop 51 in the second digital calibration unit 37 will continue to sample the high level of the reference clock signal Fin0 under the action of the reference clock signal CKD. At this time, the reversible counter 52 of the second digital calibration unit 37 enters the addition counting process, such as Fig.11As shown in the signal Kout2, after being shifted and output by the shift register 53, the sign bit sigal of the second control code Dout2 is positive, and the absolute value of the data bit digital of the second control code Dout2 continues to increase, controlling the delay time of the rising edge of the reference clock signal Fin0 by the second digitally controlled delay chain 35 to continue to increase, thereby making the duty cycle of the reference clock signal Fin1 approach 50%;

[0132] If the duty cycle of the reference clock signal Fin0 input to the second digital control delay chain 35 is less than the first reference value (e.g., 50%), the D flip-flop 51 in the second digital calibration unit 37 will continue to sample the low level of the reference clock signal Fin0 under the action of the reference clock signal CKD. At this time, the reversible counter 52 of the second digital calibration unit 37 enters a subtraction counting process, such as Fig.12 As shown in the signal Kout2, after being shifted and output by the shift register 53, the sign bit sigal of the second control code Dout2 is negative, and the absolute value of the data bit digital of the second control code Dout2 continues to increase, controlling the delay time of the falling edge of the reference clock signal Fin0 by the second digitally controlled delay chain 35 to continue to increase, so that the duty cycle of the reference clock signal Fin1 approaches 50%;

[0133] When the second control code Dout2 output by the second digital calibration unit 37 changes, the delay time of the first digitally controlled delay chain 34 may no longer be between the high level duration and the low level duration of the reference clock signal Fin1. At this time, the first digital calibration unit 36 ​​will continue to calibrate the delay time of the first digitally controlled delay chain 34 until the delay time of the first digitally controlled delay chain 34 is again between the high level duration and the low level duration of the reference clock signal Fin1.

[0134] By analogy, the calibration process of the first digital calibration unit 36 ​​on the first digitally controlled delay chain 34 and the calibration process of the second digitally controlled delay chain 35 by the second digital calibration unit 37 will be performed alternately until the duty cycle of the reference clock signal Fin1 is equal to 50%, and the delay time of the first digitally controlled delay chain 34 is equal to 0.5 times the clock period of the reference clock signal Fin1, and the digital clock multiplication circuit system reaches a dynamic equilibrium state. At this time, the output timing of the digital clock multiplication circuit is as shown in 13, and the jitter time of the output multiplied clock signal CK will be controlled within the delay resolution range of the first digitally controlled delay chain 34 and the second digitally controlled delay chain 35.

[0135] In a further preferred example, when the ambient temperature or power supply voltage of the digital clock multiplication circuit changes and causes the delay time of the first digitally controlled delay chain 34 and the second digitally controlled delay chain 35 to change, the calibration process of the first digitally controlled delay chain 34 by the first digital calibration unit 36 ​​and the calibration process of the second digitally controlled delay chain 35 by the second digital calibration unit 37 will continue to alternate until the duty cycle of the reference clock signal Fin1 is equal to 50%, and the delay time of the first digitally controlled delay chain 34 is equal to 0.5 times the clock period of the reference clock signal Fin1, and the system reaches a dynamic equilibrium state.

[0136] As can be seen from the above, the embodiment of the present application adds two digital calibration units (a first digital calibration unit 36 ​​and a second digital calibration unit 37) and two digitally controlled delay chains (a first digitally controlled delay chain 34 and a second digitally controlled delay chain 35) on the basis of the frequency multiplication unit 31. The calibration process of the first digitally controlled delay chain 34 by the first digital calibration unit 36 ​​and the calibration process of the second digitally controlled delay chain 35 by the second digital calibration unit 37 are alternately performed, so that after calibration, the duty cycle of the reference clock signal Fin1 input to the frequency multiplication unit 31 can be stabilized at the required first reference value, effectively avoiding the clock jitter of the frequency multiplication clock signal CK output by the frequency multiplication unit 31, and realizing a stable and low-jitter frequency multiplication clock output. On this basis, since the present application scheme mainly realizes the delay calibration of the corresponding delay chain through the feedback control of the digital calibration circuit of the all-digital logic, the system has a simple structure, a small occupied area, and good accuracy, reliability and robustness. By controlling the delay accuracy of the delay chain, the doubled-frequency clock jitter generated by the frequency multiplication circuit can be controlled within the required range, and the jitter caused by changes in ambient temperature and power supply voltage can be automatically repaired.

[0137] Furthermore, the embodiment of the present application also provides a method for generating a digital clock frequency multiplication signal, which can be applied to the digital clock frequency multiplication circuit disclosed in any of the above embodiments. Fig.14 As shown, the method for generating a digital clock frequency multiplication signal includes executing the following steps:

[0138] In step 141, a second delay process is performed on a rising edge or a falling edge of an initial reference clock signal.

[0139] In step 142, the delayed reference clock signal is frequency-multiplied to generate a frequency-multiplied clock signal.

[0140] In step 143, a first delay process is performed on the rising edge and the falling edge of the frequency-multiplied clock signal to generate a reference clock signal.

[0141] In step 144, the delay time during the first delay processing is calibrated according to the reference clock signal and the multiplied clock signal, and the delay time during the second delay processing is calibrated according to the reference clock signal and the reference clock signal, so as to maintain the clock period of the reference clock signal at a predetermined multiple of the clock period of the reference clock signal and stabilize the duty cycle of the reference clock signal at a first reference value.

[0142] Optionally, in some embodiments, the multiplied clock signal generated by the digital clock multiplied signal generating method is a doubled clock signal. In this case, the first reference value is, for example, 50%, and the predetermined multiple is, for example, 0.5.

[0143] It should be noted that, in specific implementation, the specific implementation of each step in the digital clock frequency multiplication signal generating method described above and the technical effects that can be obtained can refer to any embodiment of the digital clock frequency multiplication circuit disclosed above, and will not be repeated here.

[0144] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A digital clock frequency multiplication circuit, comprising: A frequency multiplication unit performs frequency multiplication processing on a reference clock signal to generate a frequency multiplied clock signal; a first digitally controlled delay chain, delaying the rising edge and the falling edge of the frequency-multiplied clock signal according to a first control code to generate a reference clock signal; A second digitally controlled delay chain delays the rising edge or the falling edge of the initial reference clock signal according to a second control code; a first digital calibration unit, generating the first control code according to the multiplied clock signal and the reference clock signal, wherein the first control code is used to calibrate the delay time of the first digitally controlled delay chain so as to maintain the clock period of the reference clock signal at a predetermined multiple of the clock period of the reference clock signal; A second digital calibration unit generates the second control code according to the reference clock signal and the reference clock signal, wherein the second control code is used to calibrate the delay time of the second digitally controlled delay chain to stabilize the duty cycle of the reference clock signal input to the frequency multiplication unit at a first reference value.

2. The digital clock frequency multiplication circuit according to claim 1, wherein: The first digital calibration unit is configured to: The multiplied clock signal is sampled according to the reference clock signal, and the first control code is increased when one of the high level and the low level of the multiplied clock signal is sampled, and the first control code is decreased when the other of the high level and the low level of the multiplied clock signal is sampled.

3. The digital clock frequency multiplication circuit according to claim 2, wherein: The second digital calibration unit is configured to: The reference clock signal is sampled according to the base clock signal, and the second control code is increased when one of the high level and the low level of the reference clock signal is sampled, and the second control code is decreased when the other of the high level and the low level of the reference clock signal is sampled.

4. The digital clock frequency multiplication circuit according to claim 2, wherein: The delay time length of the first digitally controlled delay chain for the rising edge and the falling edge of the frequency-multiplied clock signal is negatively correlated with the value of the first control code.

5. The digital clock frequency multiplication circuit according to claim 4, wherein: The first digitally controlled delay chain is configured to delay the rising edge and the falling edge of the frequency-multiplied clock signal by the same time.

6. The digital clock frequency multiplication circuit according to claim 3, wherein: The second control code includes a sign bit and a data bit; The second numerically controlled delay chain is configured as: When the sign bit of the second control code is positive, delaying the rising edge of the reference clock signal; When the sign bit of the second control code is negative, delaying the falling edge of the reference clock signal; The delay time length of the second digitally controlled delay chain for the rising edge or the falling edge of the reference clock signal is proportional to the size of the data bit of the second control code.

7. The digital clock frequency multiplication circuit according to claim 4, wherein: An initial delay time of the first digitally controlled delay chain for the frequency-multiplied clock signal is greater than a pulse width of the frequency-multiplied clock signal, and is less than a high-level duration and a low-level duration of the reference clock signal.

8. The digital clock frequency multiplication circuit according to claim 3, wherein: A bandwidth ratio of a feedback loop corresponding to each of the first digital calibration unit and the second digital calibration unit is greater than or equal to 8:

1.

9. The digital clock frequency multiplication circuit according to claim 8, wherein: The first digital calibration unit and the second digital calibration unit increase or decrease the corresponding control code based on the shift operation; The difference between the number of shift bits of the first digital calibration unit and the second digital calibration unit when performing a shift operation is at least 3 bits.

10. The digital clock frequency multiplication circuit according to claim 1, wherein: The first digital calibration unit comprises: A calibration input terminal connected to the output terminal of the frequency multiplication unit to receive the frequency multiplication clock signal; A clock input terminal connected to the output terminal of the first digitally controlled delay chain, receiving the reference clock signal; The output end is connected to the calibration control end of the first numerically controlled delay chain and outputs the first control code.

11. The digital clock frequency multiplication circuit according to claim 1, wherein: The second digital calibration unit comprises: A calibration input terminal, receiving the reference clock signal; A clock input terminal connected to the output terminal of the first digitally controlled delay chain, receiving the reference clock signal; The output end is connected to the calibration control end of the second digital control delay chain, and outputs the second control code.

12. The digital clock frequency multiplication circuit according to claim 10, wherein: The first digital calibration unit comprises: A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the first digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the first digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the multiplied clock signal according to the reference clock signal; A reversible counter, whose clock input terminal is connected to the clock input terminal of the first digital calibration unit, and whose control terminal is connected to the output terminal of the D flip-flop, and the reversible counter is used to perform addition counting or subtraction counting according to the sampling result of the D flip-flop; A shift register, wherein a clock input end is connected to a clock input end of the first digital calibration unit, a data input end is connected to an output end of the reversible counter, an output end of the shift register is connected to an output end of the first digital calibration unit, and the shift register is used to perform a shift operation on an output result of the reversible counter and output the first control code.

13. The digital clock frequency multiplication circuit according to claim 10, wherein: The first digital calibration unit comprises: A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the first digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the first digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the multiplied clock signal according to the reference clock signal; A decoding circuit, whose input end is connected to the output end of the D flip-flop, and the decoding circuit is used to compile the output level of the D flip-flop into a digital signal representing +1 or -1; an integration circuit, wherein a first input terminal is connected to the output terminal of the decoding circuit, a second input terminal is connected to the clock input terminal of the first digital calibration unit, and the integration circuit is used to perform an integration operation on the output result of the decoding circuit; A shift register, wherein a clock input end is connected to a clock input end of the first digital calibration unit, a data input end is connected to an output end of the integration circuit, an output end of the shift register is connected to an output end of the first digital calibration unit, and the shift register is used to perform a shift operation on an output result of the integration circuit and output the first control code.

14. The digital clock frequency multiplication circuit according to claim 11, wherein: The second digital calibration unit comprises: A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the second digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the second digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the reference clock signal according to the reference clock signal; A reversible counter, whose clock input terminal is connected to the clock input terminal of the second digital calibration unit, and whose control terminal is connected to the output terminal of the D flip-flop, wherein the reversible counter is used to perform addition counting or subtraction counting according to the sampling result of the D flip-flop; A shift register, wherein a clock input end is connected to a clock input end of the second digital calibration unit, a data input end is connected to an output end of the reversible counter, an output end of the shift register is connected to an output end of the second digital calibration unit, and the shift register is used to perform a shift operation on an output result of the reversible counter and output the second control code.

15. The digital clock frequency multiplication circuit according to claim 11, wherein: The second digital calibration unit comprises: A D flip-flop, a data input terminal of which is connected to the calibration input terminal of the second digital calibration unit, a clock input terminal of the D flip-flop is connected to the clock input terminal of the second digital calibration unit, and the D flip-flop is used to sample the high level and the low level of the reference clock signal according to the reference clock signal; A decoding circuit, whose input end is connected to the output end of the D flip-flop, and the decoding circuit is used to compile the output level of the D flip-flop into a digital signal representing +1 or -1; an integration circuit, wherein a first input terminal is connected to the output terminal of the decoding circuit, a second input terminal is connected to the clock input terminal of the second digital calibration unit, and the integration circuit is used to perform an integration operation on the output result of the decoding circuit; A shift register, a clock input end connected to the clock input end of the second digital calibration unit, a data input end connected to the output end of the integration circuit, an output end of the shift register connected to the output end of the second digital calibration unit, and the shift register is used to perform a shift operation on the output result of the integration circuit and output the second control code.

16. The digital clock frequency multiplication circuit according to claim 1, wherein: The frequency-multiplied clock signal is a double-frequency clock signal; The first benchmark value is 50%; The predetermined multiple is 0.

5.

17. The digital clock frequency multiplication circuit according to claim 16, wherein: The frequency multiplication unit comprises: a delay unit, an input end of which is connected to an output end of the second digitally controlled delay chain; An XOR gate logic circuit has a first input end connected to the output end of the delay unit, a second input end connected to the output end of the second digitally controlled delay chain, and an output end of the XOR gate logic circuit outputs the multiplied clock signal.

18. A method for generating a digital clock frequency multiplication signal, comprising: Performing a second delay process on a rising edge or a falling edge of an initial reference clock signal; Performing frequency multiplication processing on the reference clock signal after delay processing to generate a frequency multiplied clock signal; Performing a first delay process on the rising edge and the falling edge of the frequency-multiplied clock signal to generate a reference clock signal; The delay time during the first delay processing is calibrated according to the reference clock signal and the multiplied clock signal, and the delay time during the second delay processing is calibrated according to the reference clock signal and the reference clock signal, so as to maintain the clock period of the reference clock signal at a predetermined multiple of the clock period of the reference clock signal and stabilize the duty cycle of the reference clock signal at a first reference value.

19. The method for generating a digital clock frequency multiplication signal according to claim 18, wherein: The frequency-multiplied clock signal is a double-frequency clock signal; The first benchmark value is 50%; The predetermined multiple is 0.5.

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