Analog-to-digital conversion system, automatic gain selection method and gain deviation calibration method

Abstract

The invention relates to the technical field of analog-to-digital conversion, and provides an analog-to-digital conversion system, an automatic gain selection method and a gain deviation calibration method. The analog-to-digital conversion system comprises a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module, wherein each of the main analog-to-digital converter and the auxiliary analog-to-digital converter comprises a sampling capacitor and a conversion capacitor array; the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample an input signal, and the auxiliary analog-to-digital converter preferentially pre-converts a sampled signal to obtain a pre-conversion result; and the gain selection module is used for determining the position of the current input signal corresponding to the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, thereby determining the number of sampling capacitors required to be accessed by the main analog-to-digital converter for sampling the current input signal so as to adjust the gain of the main analog-to-digital converter. According to the invention, each sampling point can be ensured not to cause ADC overload or precision reduction, and high-precision sampling of all signals can be ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital conversion system, an automatic gain selection method and a gain deviation calibration method. Background Art

[0002] In an analog-to-digital converter chip, it is usually necessary to add a signal conditioning circuit (such as an amplifier) ​​in front of the ADC (Analogue to Digital Converter) core to condition the signal to an amplitude suitable for conversion by the ADC.

[0003] like Figure 1 As shown, assume that the signal that the signal chain needs to process is a ±10V single-ended signal. The full scale of the ADC core is determined by VREF, that is, its differential full scale is ±VREF. If the signal that needs to be processed in the application is a ±5V single-ended signal. If the ±10V range is used, the signal can only occupy half of the dynamic range of the ADC core, which will cause the accuracy of the entire signal chain to drop by half. More extremely, if the signal that needs to be processed is a ±1V single-ended signal, when the same amplification factor as ±10V is used, the accuracy of the entire signal chain will drop to 1 / 10 of the original. To solve this problem, the gain of the amplifier in the signal chain can be set to be adjustable. Figure 1 For example, the gain of the amplifier is A = Rf / Rin. For input signals of different amplitudes, the gain of the amplifier can be adjusted to keep the signal chain at its best performance. For example, assuming VREF = 4V, the input signal amplitudes are ±10V, ±5V, and ±1V, respectively, the amplifier gains are 0.4, 0.8, and 4, respectively, and the amplifier output (differential) is ±4V.

[0004] In current analog-to-digital converter chips, the gain of the signal conditioning circuit can be adjusted to allow the signal chain to maintain high precision when processing different signals. However, before the chip starts analog-to-digital conversion, the gain of the signal conditioning circuit needs to be configured; when the conversion starts, if the gain is adjusted, it will take some time to stabilize due to the limited bandwidth of the amplifier. During this time, the output of the converter is wrong, neither matching the gain before adjustment nor the gain after adjustment; moreover, the existing analog-to-digital converter chip cannot adjust the gain of the amplifier according to the amplitude of the input signal to ensure that all signals can be sampled with high precision.

[0005] In the fields of communications, the system automatically adjusts the gain of the signal conditioning circuit by setting up an automatic gain control (AGC) circuit. Figure 2As shown in the figure, the DSP (digital signal processing) module behind the ADC core can determine whether the input signal exceeds the full scale of the analog-to-digital converter chip at this time, or whether the input signal is far less than the full scale of the analog-to-digital converter chip, by analyzing the amplitude of the data of the ADC core, so as to decide whether to reduce the gain of the signal conditioning circuit or increase the gain of the signal conditioning circuit. However, this method cannot guarantee that each conversion point of the analog-to-digital converter is optimal, because the system needs to determine the gain of the subsequent conversion point by judging the amplitude of the previous conversion result. This method is prone to inference errors in practical applications, causing some points to exceed or be far less than the full scale of the ADC core. Summary of the invention

[0006] In order to solve the above technical defects, the present invention provides an analog-to-digital conversion system and a gain deviation calibration method.

[0007] In one aspect, the present invention provides an analog-to-digital conversion system, comprising: a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module, wherein the main analog-to-digital converter and the auxiliary analog-to-digital converter both comprise a sampling capacitor and a conversion capacitor array;

[0008] The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result;

[0009] The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter corresponding to the current input signal according to the pre-conversion result of the auxiliary analog-to-digital converter, and determine the number of sampling capacitors that the main analog-to-digital converter needs to connect to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to adjust the gain of the main analog-to-digital converter;

[0010] The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0011] In the embodiment of the present invention, the main analog-to-digital converter includes n groups of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor.

[0012] In the embodiment of the present invention, the capacitance value of the conversion capacitor array of the main analog-to-digital converter is set in a form of successive approximation.

[0013] In the embodiment of the present invention, at least one redundant capacitor is provided in the conversion capacitor array of the main analog-to-digital converter.

[0014] In the embodiment of the present invention, the capacitance value multiple relationship of each capacitor in the conversion capacitor array of the main analog-to-digital converter is less than 2.

[0015] In the embodiment of the present invention, the auxiliary analog-to-digital converter includes at least one group of sampling capacitors and one group of conversion capacitor arrays, and each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor.

[0016] In an embodiment of the present invention, the number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter;

[0017] The number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter.

[0018] In an embodiment of the present invention, in the first stage working timing of the analog-to-digital conversion system, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage.

[0019] In the embodiment of the present invention, in the second stage working sequence of the analog-to-digital conversion system, when the sampling end signal is received, the connection between the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor and the common mode voltage is disconnected; after the connection between the upper plate of the sampling capacitor of the main analog-to-digital converter and the common mode voltage is disconnected, the connection between the upper plate of the conversion capacitor of the main analog-to-digital converter and the common mode voltage is disconnected;

[0020] After the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

[0021] In the embodiment of the present invention, in the third phase working sequence of the analog-to-digital conversion system, how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter is determined according to the pre-conversion result of the auxiliary analog-to-digital converter.

[0022] In an embodiment of the present invention, determining how many sampling capacitors in a main analog-to-digital converter are connected to a circuit of the main analog-to-digital converter according to a pre-conversion result of the auxiliary analog-to-digital converter includes: selecting a combination of sampling capacitors corresponding to a maximum gain according to a pre-conversion result of the auxiliary analog-to-digital converter and a proportional relationship between capacitance values ​​of the sampling capacitors, and connecting the combined sampling capacitors to the circuit of the main analog-to-digital converter.

[0023] In the embodiment of the present invention, in the fourth phase working sequence of the analog-to-digital conversion system, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion.

[0024] In the embodiment of the present invention, in the fifth stage working sequence of the analog-to-digital conversion system, the final conversion result is restored to a code value of a standard range through a recovery module.

[0025] In the embodiment of the present invention, in the sixth phase working sequence of the analog-to-digital conversion system, each capacitor of the main analog-to-digital converter and the auxiliary analog-to-digital converter is reset to enter the next sampling phase.

[0026] In the embodiment of the present invention, the conversion capacitor of the main analog-to-digital converter is a segmented capacitor, and the conversion capacitors of each segment are connected via a bridge capacitor.

[0027] In the embodiment of the present invention, the main analog-to-digital converter is a two-stage analog-to-digital converter, the conversion capacitor of the first-stage analog-to-digital converter has n bits, and the conversion capacitor of the second-stage analog-to-digital converter has m bits.

[0028] In an embodiment of the present invention, the system further comprises: a linear-to-logarithmic module, configured to convert the voltage of an input signal into a logarithmic voltage;

[0029] The auxiliary analog-to-digital converter converts the logarithmic voltage to obtain a logarithmic value conversion result.

[0030] In an embodiment of the present invention, the linear-to-logarithmic module includes: a first amplifier, a current mirror, a transistor and a second amplifier; the negative input terminal of the first amplifier is connected to the input signal, the output terminal of the first amplifier is connected to the input terminal of the second amplifier and the emitter of the transistor through the current mirror, and the base and collector of the transistor are grounded.

[0031] In the embodiment of the present invention, the current mirror includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the gate of the second transistor M2 and connected to the output end of the first amplifier; the source of the first transistor M1 and the source of the second transistor M2 are connected to the power supply end VDD, the drain of the first transistor M1 is grounded through the resistor R1, and the drain of the second transistor M2 is connected to the input end of the second amplifier and the emitter of the transistor.

[0032] In the embodiment of the present invention, the system further includes: an exponential conversion module, which is used to convert the logarithmic value conversion result obtained by the auxiliary analog-to-digital converter into a linear conversion result.

[0033] Another aspect of the present invention provides a method for automatically selecting a gain of the analog-to-digital conversion system, comprising:

[0034] The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result;

[0035] The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal is determined according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to realize the gain selection of the main analog-to-digital converter;

[0036] The recovery module is used to recover the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0037] Furthermore, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result, including:

[0038] In the sampling stage, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage;

[0039] At the end of sampling, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common mode voltage; after the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

[0040] Furthermore, the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, including: selecting a combination of sampling capacitors corresponding to the maximum gain based on the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of each sampling capacitor, and connecting the combined sampling capacitors to the circuit of the main analog-to-digital converter to achieve gain selection of the main analog-to-digital converter.

[0041] Furthermore, a recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter, including: after sampling, connecting the lower plate of the conversion capacitor of the main analog-to-digital converter to a reference voltage, and obtaining a final conversion result through successive approximation conversion; and restoring the final conversion result to a code value of the standard range through the recovery module.

[0042] Furthermore, after the voltage of the input signal is converted into a logarithmic voltage by the linear-to-logarithmic module, the logarithmic voltage is converted by the auxiliary analog-to-digital converter to obtain a logarithmic value conversion result;

[0043] The logarithmic conversion result obtained by the auxiliary analog-to-digital converter is converted into a linear conversion result through the exponential conversion module.

[0044] The present invention also provides a gain deviation calibration method for the above analog-to-digital conversion system, the method comprising:

[0045] Get the actual weight of the total sampling capacitor;

[0046] Get the actual weight of the highest weight capacitor of the conversion capacitor;

[0047] The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor;

[0048] Replace the original gain with the actual gain.

[0049] In the embodiment of the present invention, obtaining the actual weight of the total sampling capacitance includes:

[0050] In the sampling phase, the sampling capacitor to be calibrated is connected to the upper reference voltage, and the remaining capacitors are connected to the lower reference voltage;

[0051] Connect the sampling capacitor to be calibrated to the common mode voltage, convert it in a successive approximation manner, and obtain a digital code starting from the lowest bit;

[0052] Obtaining actual weights of the respective sampling capacitors according to the digital code starting from the least significant bit and the actual weights of the capacitors starting from the least significant bit;

[0053] The actual weights of the individual sampling capacitors are added together to obtain the actual weight of the total sampling capacitor.

[0054] In the embodiment of the present invention, obtaining the actual weight of the highest weight capacitor of the conversion capacitor includes:

[0055] During the sampling phase, the highest weight capacitor in the conversion capacitor is connected to the reference voltage;

[0056] After sampling, the highest weight capacitor in the conversion capacitor is connected to the common mode voltage, and the other capacitors in the conversion capacitor are successively converted to obtain the digital code of each bit;

[0057] According to the digital code of each bit and the actual weight of each capacitor, the actual weight of the highest weight capacitor of the conversion capacitor is obtained.

[0058] In the embodiment of the present invention, the ratio of the actual weight of the total sampling capacitor to the actual weight of the highest weight capacitor of the conversion capacitor is used as the actual gain.

[0059] The present invention also provides a chip, which includes the above analog-to-digital conversion system.

[0060] In the analog-to-digital conversion system of the present invention, in the sampling stage, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to preferentially pre-convert the sampled signal to obtain a pre-conversion result, and then the gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result, thereby determining the number of sampling capacitors that the main analog-to-digital converter needs to connect to sample the current input signal, and then adjusting the gain of the main analog-to-digital converter. The analog-to-digital conversion system of the present invention can automatically detect the amplitude of the input signal, and automatically adjust the gain of the ADC according to the amplitude of the input signal, so as to better utilize the dynamic range of the ADC, reduce quantization noise, and improve the accuracy of analog-to-digital conversion; because the judgment is made and the gain is adjusted at the current sampling point, rather than adjusting the gain by methods such as data statistics, the analog-to-digital conversion system of the present invention can ensure that each sampling point does not cause ADC overload or precision reduction, and ensure that all signals can obtain high-precision sampling, meeting the industrial field The demand for accuracy at each sampling point.

[0061] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0063] Figure 1 It is an existing analog-to-digital conversion structure;

[0064] Figure 2 It is another existing analog-to-digital conversion structure;

[0065] Figure 3 is an architecture diagram of an analog-to-digital conversion system provided in Embodiment 1 of the present invention;

[0066] Figure 4 1 is a schematic diagram of the structure of a main analog-to-digital converter (main ADC) of the analog-to-digital conversion system provided in Embodiment 1 of the present invention;

[0067] Figure 5 1 is a schematic structural diagram of an auxiliary analog-to-digital converter (Sub-ADC) of an analog-to-digital conversion system provided in Embodiment 1 of the present invention;

[0068] Figure 6 is a working timing diagram of the analog-to-digital conversion system provided in Embodiment 1 of the present invention;

[0069] Figure 7 Schematic diagram of the connection state of the main analog-to-digital converter (main ADC) in the sampling phase provided by the first embodiment of the present invention;

[0070] Figure 8 Schematic diagram of the connection state of the auxiliary analog-to-digital converter (Sub-ADC) provided in the sampling phase according to the first embodiment of the present invention;

[0071] Fig. 9 1 is a schematic diagram comparing the signal-to-noise ratio of the analog-to-digital conversion system provided by the first embodiment of the present invention and the signal-to-noise ratio of a traditional ADC;

[0072] Fig.10 is a structural diagram of an analog-to-digital conversion system provided in Embodiment 2 of the present invention;

[0073] Fig.11 is a schematic diagram of the structure of the analog-to-digital conversion system provided in Embodiment 3 of the present invention;

[0074] Fig.12 is a structural diagram of an analog-to-digital conversion system provided by a fourth embodiment of the present invention;

[0075] Fig.13 is a circuit schematic diagram of a linear-to-logarithmic module of an analog-to-digital conversion system provided in a fourth embodiment of the present invention;

[0076] Fig.14 is a structural diagram of an analog-to-digital conversion system provided in Embodiment 5 of the present invention;

[0077] Fig.15 is a structural diagram of an analog-to-digital conversion system provided by Embodiment 6 of the present invention;

[0078] Fig.16 is a flow chart of a gain deviation calibration method provided by Embodiment 7 of the present invention;

[0079] Fig.17 It is a signal connection diagram of an analog-to-digital conversion system corresponding to the sampling capacitor calibration of the gain deviation calibration method provided in the seventh embodiment of the present invention. DETAILED DESCRIPTION

[0080] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0081] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0082] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0083] As described in the background technology, in existing analog-to-digital converter chips, the automatic gain control (AGC) needs to determine the gain of the subsequent conversion point by judging the amplitude of the previous conversion result. In practical applications, this can easily lead to inference errors, causing some points to exceed or be far less than the full scale of the ADC core. As a result, it is impossible to ensure that each conversion point of the analog-to-digital converter is optimal, that is, it cannot guarantee that all signals can obtain high-precision sampling.

[0084] In view of the above problems, an embodiment of the present invention provides an analog-to-digital conversion system, including: a main analog-to-digital converter, an auxiliary analog-to-digital converter and a gain selection module. In the sampling stage, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result, and then the gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result, thereby determining the number of sampling capacitors that the main analog-to-digital converter needs to connect to sample the current input signal, and then adjusting the gain of the main analog-to-digital converter. The analog-to-digital conversion system of the present invention can automatically detect the amplitude of the input signal, and automatically adjust the gain of the ADC according to the amplitude of the input signal, so as to better utilize the dynamic range of the ADC, reduce quantization noise, and improve the accuracy of analog-to-digital conversion; because the judgment is made and the gain is adjusted at the current sampling point, rather than adjusting the gain by methods such as data statistics, the analog-to-digital conversion system of the present invention can ensure that each sampling point does not cause ADC overload or precision reduction, and ensure that all signals can obtain high-precision sampling, meeting the industrial field The demand for accuracy at each sampling point.

[0085] Embodiment 1

[0086] like Figure 3As shown, the analog-to-digital conversion system provided in this embodiment includes: a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module, the main analog-to-digital converter and the auxiliary analog-to-digital converter both include sampling capacitors and conversion capacitor arrays; the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result; the gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter corresponding to the pre-conversion result of the auxiliary analog-to-digital converter, and according to the position of the current input signal in the full scale of the main analog-to-digital converter corresponding to the current input signal, determine the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal, so as to adjust the gain of the main analog-to-digital converter; the recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to the result corresponding to the standard range of the main analog-to-digital converter.

[0087] like Figure 4 As shown, the main analog-to-digital converter of the analog-to-digital conversion system includes n groups of sampling capacitors and a group of conversion capacitor arrays, each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor, the n positive sampling capacitors are Csp1, Csp1, ..., Cspn, and the n negative sampling capacitors are Csn1, Csn1, ..., Csnn. The conversion capacitor array is arranged after the sampling capacitor, and the capacitance value of the conversion capacitor array is set in the form of successive approximation, for example, according to the capacitor array form of SAR ADC (successive approximation register ADC, successive approximation analog-to-digital converter). In this embodiment, the capacitance values ​​of the conversion capacitor array are 2 n *Cu, 2 (n-1) *Cu, 2 (n-2) *Cu, ..., 2*Cu, Cu. At least one redundant capacitor may be provided in the conversion capacitor array of the main analog-to-digital converter; or the capacitance value multiple relationship of each capacitor in the conversion capacitor array is less than 2, so as to improve the fault tolerance of conversion.

[0088] like Figure 5As shown, the auxiliary analog-to-digital converter of the analog-to-digital conversion system includes at least one group of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive sampling capacitor and a negative sampling capacitor. The number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter, and the number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter, that is, the accuracy of the auxiliary analog-to-digital converter is lower than the accuracy of the main analog-to-digital converter. The auxiliary analog-to-digital converter can select a low-precision SAR ADC with a low number of bits. In this embodiment, the positive sampling capacitor and the negative sampling capacitor are both one, and the capacitance values ​​of the sampling capacitor and the conversion capacitor are small. For example, the total capacitance of the auxiliary analog-to-digital converter (Sub-ADC) is less than 1pF. The capacitance in the main analog-to-digital converter (main ADC) needs to reach more than ten or even tens of pF due to the noise that affects the entire signal link.

[0089] During the sampling phase, the Sub-ADC samples together with the main ADC, and the Sub-ADC preferentially pre-converts the sampled signal to obtain the pre-conversion result. Based on the pre-conversion result, the Sub-ADC can determine where the current signal is approximately in the full scale, thereby determining how many sampling capacitors in the main ADC need to be connected to the circuit after the sampling is completed. Depending on the number of sampling capacitors used, the main ADC can achieve different gains, so that the current sampling point can be sampled as accurately as possible. For example, if the Sub-ADC finds that the current input signal is small, more sampling capacitors are connected to the circuit to achieve a large gain for the main ADC, so that the noise in the main ADC is smaller than the signal, and high-precision sampling is achieved; on the contrary, if the Sub-ADC finds that the current input signal is large, only fewer sampling capacitors are connected to the circuit, and the main ADC will have no gain, or have a reduction function, so that the main ADC will not be overloaded.

[0090] like Figure 6 As shown, the working process of ADC in the analog-to-digital conversion system provided in this embodiment mainly includes two stages of sampling and conversion, and specifically includes six working timing stages of step1, step2, step3, step4, step5, and step6.

[0091] like Figure 7 As shown, in the sampling phase step1 working sequence, the lower plates of the sampling capacitors Csp1, Csp2, ..., Cspn, Csn1, Csn2, ..., Csnn of the main ADC are connected to the input signals Vadc_p and Vadc_m, and the lower plates of all the conversion capacitors are connected to VCM (Common Mode Voltage).

[0092] like Figure 8As shown, in the sampling phase step 1 working sequence, the lower plates of the sampling capacitors Csp_aux and Csn_aux of the Sub-ADC are connected to the input signals Vadc_p and Vadc_m, and the lower plates of all the conversion capacitors are connected to VCM.

[0093] In the main ADC, the relationship between the sampling capacitors Csp1, Csp2, and Cspn can be 1:2:n. Different numbers of binary capacitors can also be inserted between the sampling capacitors. For example, if n is 4, Csp1:Csp2:Csp3:Csp4=1:2:4:8. The capacitors at the negative end of the ADC are also set in this ratio. Among them, Csp1 is set to 2*2^n*Cu as an example. In addition, a part of the conversion capacitors can also be selected to be added to the sampling capacitors during the sampling stage.

[0094] In Sub-ADC, the relationship between the sampling capacitor Csp_aux and the conversion capacitor is Csp_aux = 2 4 *Cu_aux, that is, the sampling capacitor is twice the maximum conversion capacitor. Similarly, a portion of the conversion capacitor can be selected and added to the sampling capacitor during the sampling phase. Due to the proportional relationship of the capacitors, the gain of the Sub-ADC is always kept at 1.

[0095] In step 2 working sequence, when receiving the external sampling end signal, the main ADC and Sub-ADC end sampling and then start successive approximation conversion. In the conversion phase, the upper plates of all capacitors (sampling capacitors and conversion capacitor arrays) of the Sub-ADC are disconnected from VCM, while the upper plate disconnection of the capacitors of the main ADC needs to be done step by step. In the conversion phase, the main ADC first disconnects the switch SW_s(1:n) to freeze the input signal on the sampling capacitor, and then disconnects the upper plate of the conversion capacitor from VCM.

[0096] In this embodiment, the main ADC and the Sub-ADC adopt a capacitor switching SAR ADC (successive approximation register ADC, successive approximation analog-to-digital converter) or a monotonically switched SAR ADC. After disconnecting the upper plate of the capacitor in sequence, disconnect the connection between the lower plate of the capacitor and the ADC input signal. Since the SAR ADC adopts the sampling method of the lower plate sampling (the upper plate is disconnected first and the lower plate is disconnected later), the accuracy reduction caused by the switch charge injection can be effectively avoided. After the sampling capacitor is disconnected from the input signal, the sampling capacitor is connected to VCM. Among them, VCM=1 / 2*VREFP, VREFP (upper reference voltage) can be selected as 4V or other voltages, and VREFN (lower reference voltage) is generally 0V.

[0097] In this embodiment, a VCM-based Sub-ADC is used as an example for illustration, but other capacitor switching methods are also protected if they are consistent with the method in this application, including but not limited to SAR ADC with traditional capacitor switching method and SAR ADC with monotonic switching. After sampling is completed, the Sub-ADC prioritizes successive approximation conversion to obtain the pre-conversion result code_Sub. Taking the 5-bit Sub-ADC as an example, after sampling is completed, for the VCM-based ADC structure, a comparison can be performed immediately, and the result is recorded as d4; if d4=1, it means that Vadc_p>Vadc_m, at this time, the lower plate of the highest bit of the P-end conversion capacitor is connected to the upper reference voltage VREFP, and the lower plate of the highest bit of the N-end conversion capacitor is connected to the lower reference voltage VREFN. Then the comparator makes a comparison and obtains d3~d0 in a successive approximation manner. The Sub-ADC obtains the conversion result code_Sub= <d4:d0>; The 5-bit Sub-ADC can determine where the current input signal is in the full scale.

[0098] In step 3, the conversion result code_Sub of Sub-ADC determines how many sampling capacitors in the main ADC are connected to the main ADC circuit. For the main ADC, different numbers of sampling capacitors reconnected to the circuit will form different gains. In practice, the gain of the main ADC can also be realized as a decimal by setting the capacitors to a decimal relationship.

[0099] In this embodiment, a combination of sampling capacitors corresponding to the maximum gain is selected according to the conversion result of the Sub-ADC and the proportional relationship between the capacitance values ​​of each sampling capacitor, and the sampling capacitors of the combination are connected to the main ADC circuit. Taking the ratio of sampling capacitors Csp1:Csp2:Csp3:Csp4=1:2:4:8 as an example, the relationship between the sampling capacitors reconnected to the circuit in the main ADC and the gain of the main ADC is as follows:

[0100] Reconnect the sampling capacitor Main ADC gain Csp1 1 Csp2 2 Csp1+Csp2 3 Csp3 4 Csp3+Csp1 5 Csp3+Csp2 6 Csp3+Csp2+Csp1 7 Csp4 8 Csp4+Csp1 9 Csp4+Csp2 10 Csp4+Csp2+Csp1 11 Csp4+Csp3 12 Csp4+Csp3+Csp1 13 Csp4+Csp3+Csp2 14 Csp4+Csp3+Csp2+Csp1 15

[0101] When selecting a magnification factor, select less than The maximum gain is as follows:

[0102]

[0103]

[0104] Referring to the above table, in step 3, different sampling capacitors are connected to the main ADC circuit according to the selected gain to achieve the corresponding amplification factor.

[0105] In step 4 working sequence, the main ADC can control the lower plate of the conversion capacitor in the main ADC to connect the reference voltage VREFP and VREFN according to the result of the comparator in a successive approximation manner, and obtain the final conversion result Code_main through the conversion of successive approximation. In other embodiments, the result of Sub-ADC (5bit) can also be directly loaded into the first 5bit of the main ADC after calculation, that is, Code_main (n:n-5) = code_Sub*gain, gain represents gain; the subsequent capacitors are then converted in a normal successive approximation manner, and Code_main can also be obtained in the end. In this way, the conversion speed of the main ADC can be accelerated and the conversion power consumption can be reduced. Redundant capacitors can also be set in the main ADC. If the Sub-ADC has some errors, the reasonable redundant bits in the main ADC can absorb the errors of the first 5bits and obtain the correct final result.

[0106] In step 5 working sequence, the final conversion result can be restored to the code value of the standard range through the recovery module (dynamic range restorer), and the calculation formula is: Code_final = Code_main / gain.

[0107] In step 6 working sequence, the user can read the final data Code_final, reset the capacitors of the main ADC and Sub-ADC, restore to the sampling mode, and enter the next sampling stage.

[0108] The analog-to-digital conversion system of the present invention can fully utilize the full scale of the main ADC. For the entire signal chain, when the input signal is small, the energy equivalent to the input end of the quantization noise will not increase compared to the traditional method. Fig. 9 As shown, the signal-to-noise ratio (SNR) of a conventional ADC decreases as the input signal decreases. In the analog-to-digital conversion system of the present invention, if the noise of the comparator and other circuits in the ADC accounts for a small proportion, the signal-to-noise ratio of the ADC will not decrease as the input signal decreases.

[0109] Embodiment 2

[0110] In one embodiment, as the number of bits of the main ADC increases, a smaller capacitor can be used to achieve a higher resolution by means of capacitor segmentation or amplifiers. Fig.10 As shown in FIG. 1 , the conversion capacitor array of the main ADC is a segmented capacitor. Through the bridge capacitor Cc, the conversion capacitor array of the main ADC is divided into two segments, the front segment is n bits, and the rear segment is m bits. This method can achieve a high number of bits under the condition that the capacitor ratio is not too different. In addition, the capacitor array can be divided into more segments through more bridge capacitors Cc, thereby achieving a higher resolution.

[0111] Embodiment 3

[0112] like Fig.11 As shown, this embodiment provides a two-stage analog-to-digital conversion system, wherein a two-stage ADC is formed by an inter-stage amplifier, wherein the conversion capacitor of the first-stage ADC has n bits, and the conversion capacitor of the second-stage ADC has m bits. Redundant capacitors can be added to the first-stage ADC or the second-stage ADC. The two-stage ADC can expand the accuracy of the ADC and realize an n+m-bit ADC.

[0113] Embodiment 4

[0114] Since multiple conversion results corresponding to the same gain may occur during the conversion process of the Sub-ADC, the performance of the Sub-ADC is not fully utilized. Therefore, an embodiment of the present invention provides a logarithmic ADC.

[0115] like Fig.12 As shown, in Fig.10 Based on the segmented ADC shown in the figure, a linear-to-logarithmic conversion module and an exponential conversion module are added. The corresponding relationship between the conversion result code_Sub of the Sub-ADC and the amplification factor is as follows:

[0116] code_Sub Magnification 8～15-8～-15 1 5～7-5～-7 2 4-4 3 3-3 4 2-2 7 1-1 15

[0117] In a specific example, the voltage data Vin is converted by a linear-to-logarithmic module. For example, the amplitudes of different gears are converted to logarithmic voltages according to the formula Vlog=ln(vin)*5.77. Then, after sub-ADC conversion, the logarithmic conversion result code_log is obtained, and then the ADC gain can be set accordingly according to the table below.

[0118] code_Sub(code_line) code_log Magnification 8～15-8～-15 12～15-12～-15 1 5～7-5～-7 9～11-9～-11 2 4-4 7～8-7～-8 3 3-3 5～6-5～-6 4 2-2 3～4-3～-4 7 1-1 -2～2 15

[0119] In the above table, code_Sub is the conversion result of the sub-ADC before taking the logarithm, and code_log is the conversion result of the sub-ADC after taking the logarithm. It can be seen from the above table that after taking the logarithm, the value range of Code_Sub corresponding to each magnification factor becomes more uniform, so the accuracy requirement of Sub_ADC can be relaxed. In addition to taking the logarithm, other methods including table lookup can be used to improve the numerical change of accuracy.

[0120] In addition, the digital code conversion of the sub-ADC can be restored to the code consistent with that before logarithmic conversion through the exponential conversion module, that is, code_line=exp(code_log / 5.77); the aforementioned dynamic range restorer can also be used for code recovery.

[0121] like Fig.13 As shown, the linear-to-logarithmic module includes a first amplifier AMP1, a current mirror, a transistor B1, and a second amplifier AMP2. The negative input terminal of the first amplifier AMP1 is connected to the input signal VIN, the positive input terminal of the first amplifier AMP1 is grounded through a resistor R1, the output terminal of the first amplifier AMP1 is connected to the input terminal of the second amplifier AMP2 and the emitter of the transistor B1 through a current mirror, and the base and collector of the transistor B1 are grounded. The current mirror includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the gate of the second transistor M2 and connected to the output terminal of the first amplifier AMP1, the source of the first transistor M1 and the source of the second transistor M2 are connected to the power supply terminal VDD, the drain of the first transistor M1 is grounded through a resistor R1, and the drain of the second transistor M2 is connected to the input terminal of the second amplifier AMP2 and the emitter of the transistor B1.

[0122] The feedback circuit formed by the first amplifier AMP1 and the first transistor M1 loads the input signal VIN on the resistor R1, thereby forming a current passing through the first transistor M1, and the current I=VIN / R1. Because the second transistor M2 is in a mirror relationship with the first transistor M1, the current passing through M2 is equal to the current passing through M1.

[0123] Among them, the voltage of the emitter of transistor B1 is:

[0124]

[0125] Where, Vt = 26mV, Is is the saturation current of the transistor;

[0126] By properly setting the gain of the second amplifier AMP2, we can obtain:

[0127]

[0128] Embodiment 5

[0129] For the main ADC, as the amplification factor increases, the capacitance added to the capacitor array increases.

[0130] The voltage of the least significant bit (LSB) converted by the main ADC is:

[0131]

[0132] Wherein, Cs is the total sampling capacitance used in the current conversion, Convst is the sum of the total conversion capacitance, and Cu is the minimum unit capacitance in the conversion capacitance.

[0133] As the gain increases, Cs will gradually increase, and V_LSB will become very small. In a high-resolution ADC, the noise of the comparator may become much larger than V_LSB, causing the comparison results of the lowest few bits of the ADC to be submerged by the noise and unable to produce correct results.

[0134] In view of the above problems, this embodiment provides a two-stage analog-to-digital conversion system, which is improved based on the analog-to-digital conversion structure of the third embodiment. Fig.14 As shown in the figure, the analog-to-digital conversion system reduces the number of bits of the first-stage ADC, and can reduce the number of bits n to 2 or even 0, that is, after the sampling capacitor completes the sampling, it is directly converted by the second-stage ADC behind the amplifier. In this way, the noise of the comparator will hardly affect the performance of the ADC.

[0135] Embodiment 6

[0136] like Fig.15 As shown, this embodiment provides an analog-to-digital conversion system, which divides the sampling capacitor (each Cs) into two equal capacitors. During the sampling phase, the upper plates of half of the sampling capacitors are connected to the power supply terminal VDD, and the upper plates of the other half of the sampling capacitors are connected to VSS. After the sampling is completed, all the upper plates are connected together, and no additional VCM voltage is required, and the voltage of the upper plate is VDD / 2. In the analog-to-digital conversion system of this embodiment, the VCM voltage is not used in the sampling phase, and the sampling phase has zero power consumption, which saves power consumption.

[0137] The analog-to-digital conversion system of the above embodiment can also be improved to a structure of P-terminal and N-terminal, and the P-terminal and N-terminal are operated single-ended at the initial stage of conversion. A single-ended ADC is placed on each of the P-terminal and N-terminal, and the main capacitor array capacitance of the P-terminal or N-terminal is independently controlled, so as to achieve different gains at the positive and negative ends and process any common-mode input signal.

[0138] The analog-to-digital conversion system provided by the embodiment of the present invention uses an auxiliary analog-to-digital converter with lower precision to modify the sampling capacitor size after pre-conversion at the current sampling point to realize ADCs with different gains, and processes and recovers data through a recovery module. When input signals of different amplitudes are boosted on the entire system, the dynamic range of the signal chain is improved.

[0139] Compared with a fixed-gain signal chain, the present invention can automatically detect the signal input amplitude and automatically adjust the gain of the ADC, thereby better utilizing the dynamic range of the ADC, reducing quantization noise, and improving the accuracy of analog-to-digital conversion.

[0140] Compared with traditional automatic gain control, the present invention makes a judgment and adjusts the gain at the current sampling point, rather than adjusting the gain through methods such as data statistics. This can ensure that each sampling point does not cause ADC overload or accuracy reduction, and is very suitable for industrial fields and other analog-to-digital conversion systems that require accurate data at each sampling point.

[0141] Based on the analog-to-digital conversion system provided in the above embodiment, an embodiment of the present invention also provides a method for automatically selecting a gain of the analog-to-digital conversion system, the method comprising:

[0142] The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result;

[0143] The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal is determined according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to realize the gain selection of the main analog-to-digital converter;

[0144] The recovery module is used to recover the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

[0145] Furthermore, the auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to preferentially pre-convert the sampled signal to obtain a pre-conversion result, which specifically includes: in the sampling stage, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common-mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common-mode voltage; at the end of sampling, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common-mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common-mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common-mode voltage; after the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common-mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain the pre-conversion result.

[0146] Furthermore, the number of sampling capacitors required to be connected to the main analog-to-digital converter for sampling the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, specifically including: selecting a combination of sampling capacitors corresponding to the maximum gain based on the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of each sampling capacitor, and connecting the combined sampling capacitors to the circuit of the main analog-to-digital converter, thereby realizing the gain selection and adjustment of the main analog-to-digital converter.

[0147] Furthermore, a recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter, specifically including: after sampling, connecting the lower plate of the conversion capacitor of the main analog-to-digital converter to a reference voltage, and obtaining a final conversion result through successive approximation conversion; and restoring the final conversion result to a code value of the standard range through the recovery module.

[0148] Furthermore, the voltage of the input signal can be converted into a logarithmic voltage through a linear-to-logarithmic module, and then the logarithmic voltage can be converted through an auxiliary analog-to-digital converter to obtain a logarithmic conversion result; the logarithmic conversion result obtained by the auxiliary analog-to-digital converter can be converted into a linear conversion result through an exponential conversion module.

[0149] Embodiment 7

[0150] In the integrated circuit manufacturing process, capacitors may have random mismatches during the manufacturing process. The sampling capacitors and conversion capacitors in the analog-to-digital conversion system will have random deviations. The deviation between the sampling capacitor and the conversion capacitor will cause the gain to deviate from the ideal value; the deviation between the conversion capacitors will cause the linearity of the ADC to decrease, and these deviations need to be calibrated.

[0151] This embodiment provides a calibration method for the gain deviation caused by the deviation between the sampling capacitor and the conversion capacitor. Fig.16 As shown, the method comprises the following steps:

[0152] The first step is to obtain the actual weight of the total sampling capacitor;

[0153] The second step is to obtain the actual weight of the highest weight capacitor of the conversion capacitor;

[0154] The third step is to obtain the ratio between the actual sampling capacitance and the conversion capacitance according to the actual weight of the total sampling capacitance and the actual weight of the highest weight capacitance of the conversion capacitance, which is used as the actual gain. The calculation formula is:

[0155]

[0156] Where gain_cal is the actual gain, Cs_cal is the actual weight of the total sampling capacitors, and C_msb_cal is the actual weight of the highest weight (MSB) capacitor of the conversion capacitor.

[0157] The fourth step is to use the actual gain to replace the original gain in the process of restoring the result to the code value of the standard range through the recovery module (dynamic range restorer), that is, to use gain_cal to replace the gain in the calculation formula Code_final=Code_main / gain of the recovery module.

[0158] In the first step above, since the weight of the sampling capacitor is usually large, it is necessary to calibrate the sampling capacitors Cs1 to Csn in sequence. If the weight of one sampling capacitor is greater than the sum of the weights of all conversion capacitors, the sampling capacitor can be divided into several for calibration and then superimposed. The specific method for obtaining the actual weight of the total sampling capacitor is: refer to Fig.17 , take the calibration of sampling capacitors Csp1 and Csn1 as an example, in the sampling stage, the input signal is not connected to the main ADC, the sampling capacitor to be calibrated is connected to VREFP (upper reference voltage), and the remaining capacitors are connected to VREFN (lower reference voltage); then, the upper plate is disconnected, and the sampling capacitors Csp1 and Csn1 to be calibrated are connected to VCM, and the low-bit ADC is converted in a successive approximation manner to obtain a digital code starting from the lowest bit. The actual weight Cs1_cal of the sampling capacitor Cs1 (i.e. Csp1+Csn1) is:

[0159]

[0160] Among them, d i It is a digital code that starts from the lowest bit, that is, the digital code of the least significant bit (LSB for short); C i The actual weight of the capacitor starting from the lowest bit (the lowest bits (such as 1 to 7) are not calibrated, and the latter (capacitors above 8) may be calibrated weights). For example, C1 represents the actual weight of capacitor Cu, C2 represents the actual weight of capacitor 2*Cu, and Cn represents the actual weight of capacitor 2 n *Actual weight of Cu.

[0161] The weights of Csp2 and Csn2, and finally Cspn and Csnn are calibrated in sequence, and the actual weight Cs2_cal of Cs2 (ie, Csp2+Csn2) and the actual weight Csn_cal of Csn (ie, Cspn+Csnn) can be obtained.

[0162] Finally, the actual weight values ​​of all sampling capacitors decided to be used after conversion by the auxiliary analog-to-digital converter are added together to obtain the actual weight Cs_cal of the total sampling capacitor.

[0163] In the second step above, the actual weight of the highest weight capacitor of the conversion capacitor is obtained in a similar way to the actual weight of the total sampling capacitor. Specifically, during the sampling phase, the lower plates of all sampling capacitors are connected to VCM, and the highest weight (MSB) capacitor 2 in the conversion capacitor to be calibrated n *The lower plate of Cu is connected to the reference voltage VREFP and VREFN; after sampling, the lower plate of the MSB capacitor is restored to VCM, and the following capacitor 2 (n-1) *Cu, 2 (n-2) *Cu, …, 2*Cu, Cu are successively converted by successive approximation.

[0164] Through the above operation, the digital code d of each bit can be obtained. i . According to the digital code d of each bit i And the actual weight of each capacitor C i , using the formula The actual weight C_msb_cal of the highest weight capacitor of the conversion capacitor is calculated.

[0165] By adopting the above-mentioned gain deviation calibration method, the deviation between the sampling capacitor and the conversion capacitor in the analog-to-digital conversion system can be calibrated, thereby further improving the accuracy of the analog-to-digital conversion system.

[0166] An embodiment of the present invention further provides a chip, which includes the above analog-to-digital conversion system.

[0167] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present invention may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0168] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0169] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0171] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An analog-to-digital conversion system, characterized in that: include: A main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module, wherein the main analog-to-digital converter and the auxiliary analog-to-digital converter both include sampling capacitors and conversion capacitor arrays; The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter preferentially pre-converts the sampled signal to obtain a pre-conversion result; The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter corresponding to the current input signal according to the pre-conversion result of the auxiliary analog-to-digital converter, and determine the number of sampling capacitors that the main analog-to-digital converter needs to connect to sample the current input signal according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to adjust the gain of the main analog-to-digital converter; The recovery module is used to restore the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

2. The analog-to-digital conversion system according to claim 1, characterized in that: The main analog-to-digital converter includes n groups of sampling capacitors and a group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

3. The analog-to-digital conversion system according to claim 2, characterized in that: The capacitance value of the conversion capacitor array of the main analog-to-digital converter is set in a successive approximation form.

4. The analog-to-digital conversion system according to claim 3, characterized in that: At least one redundant capacitor is arranged in the conversion capacitor array of the main analog-to-digital converter.

5. The analog-to-digital conversion system according to claim 3, characterized in that: The capacitance value multiple relationship of each capacitor in the conversion capacitor array of the main analog-to-digital converter is less than 2.

6. The analog-to-digital conversion system according to claim 2, characterized in that: The auxiliary analog-to-digital converter includes at least one group of sampling capacitors and one group of conversion capacitor arrays, and each group of sampling capacitors includes a positive-end sampling capacitor and a negative-end sampling capacitor.

7. The analog-to-digital conversion system according to claim 6, characterized in that: The number of sampling capacitors of the auxiliary analog-to-digital converter is less than the number of sampling capacitors of the main analog-to-digital converter; The number of bits of the conversion capacitor array of the auxiliary analog-to-digital converter is less than the number of bits of the conversion capacitor array of the main analog-to-digital converter.

8. The analog-to-digital conversion system according to claim 6, characterized in that: In the first stage working sequence of the analog-to-digital conversion system, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage.

9. The analog-to-digital conversion system according to claim 6, characterized in that: In the second phase working sequence of the analog-to-digital conversion system, upon receiving a sampling end signal, disconnecting the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor from the common mode voltage; after disconnecting the upper plate of the sampling capacitor of the main analog-to-digital converter from the common mode voltage, disconnecting the upper plate of the conversion capacitor of the main analog-to-digital converter from the common mode voltage; After the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

10. The analog-to-digital conversion system according to claim 6, characterized in that: In the third phase working sequence of the analog-to-digital conversion system, how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter is determined according to the pre-conversion result of the auxiliary analog-to-digital converter.

11. The analog-to-digital conversion system according to claim 10, characterized in that: Determining how many sampling capacitors in the main analog-to-digital converter are connected to the circuit of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter includes: A combination of sampling capacitors corresponding to the maximum gain is selected according to the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the sampling capacitors, and the sampling capacitors of the combination are connected to the circuit of the main analog-to-digital converter.

12. The analog-to-digital conversion system according to claim 6, characterized in that: In the fourth phase working sequence of the analog-to-digital conversion system, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion.

13. The analog-to-digital conversion system according to claim 6, characterized in that: In the fifth phase of the working sequence of the analog-to-digital conversion system, the final conversion result is restored to a code value of a standard range through a recovery module.

14. The analog-to-digital conversion system according to claim 6, characterized in that: In the sixth phase of the analog-to-digital conversion system, each capacitor of the main analog-to-digital converter and the auxiliary analog-to-digital converter is reset and enters the next sampling phase.

15. The analog-to-digital conversion system according to claim 2, characterized in that: The conversion capacitor of the main analog-to-digital converter is a segmented capacitor, and each segmented conversion capacitor is connected via a bridge capacitor.

16. The analog-to-digital conversion system according to claim 2, characterized in that: The main analog-to-digital converter is a two-stage analog-to-digital converter, the conversion capacitor of the first-stage analog-to-digital converter has n bits, and the conversion capacitor of the second-stage analog-to-digital converter has m bits.

17. The analog-to-digital conversion system according to claim 1, characterized in that: The system further comprises: A linear-to-logarithmic module is used to convert the voltage of the input signal into a logarithmic voltage; The auxiliary analog-to-digital converter converts the logarithmic voltage to obtain a logarithmic value conversion result.

18. The analog-to-digital conversion system according to claim 17, characterized in that: The linear-to-logarithmic module includes: a first amplifier, a current mirror, a transistor and a second amplifier; The negative input terminal of the first amplifier is connected to the input signal, the output terminal of the first amplifier is connected to the input terminal of the second amplifier and the emitter of the triode through a current mirror, and the base and collector of the triode are grounded.

19. The analog-to-digital conversion system according to claim 18, characterized in that: The current mirror comprises a first transistor and a second transistor, wherein the gate of the first transistor is connected to the gate of the second transistor and is connected to the output end of the first amplifier; The source of the first transistor and the source of the second transistor are connected to the power supply end, the drain of the first transistor is grounded through a resistor, and the drain of the second transistor is connected to the input end of the second amplifier and the emitter of the triode.

20. The analog-to-digital conversion system according to claim 17, characterized in that: The system further comprises: The exponential conversion module is used to convert the logarithmic value conversion result obtained by the auxiliary analog-to-digital converter into a linear conversion result.

21. A method for automatically selecting gain of an analog-to-digital conversion system, characterized in that: The analog-to-digital conversion system includes a main analog-to-digital converter, an auxiliary analog-to-digital converter, a gain selection module and a recovery module. The main analog-to-digital converter and the auxiliary analog-to-digital converter both include a sampling capacitor and a conversion capacitor array. The method includes: The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result; The gain selection module is used to determine the position of the current input signal in the full scale of the main analog-to-digital converter according to the pre-conversion result of the auxiliary analog-to-digital converter, and the number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal is determined according to the position of the current input signal in the full scale of the main analog-to-digital converter, so as to realize the gain selection of the main analog-to-digital converter; The recovery module is used to recover the conversion result of the main analog-to-digital converter after gain adjustment to a result corresponding to the standard range of the main analog-to-digital converter.

22. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The auxiliary analog-to-digital converter and the main analog-to-digital converter simultaneously sample the input signal, and the auxiliary analog-to-digital converter is used to pre-convert the sampled signal to obtain a pre-conversion result, including: In the sampling stage, the lower plate of the sampling capacitor of the main analog-to-digital converter is connected to the input signal, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the common mode voltage, the lower plate of the sampling capacitor of the auxiliary analog-to-digital converter is connected to the input signal, and the lower plate of the conversion capacitor of the auxiliary analog-to-digital converter is connected to the common mode voltage; At the end of sampling, the upper plate of the sampling capacitor of the auxiliary analog-to-digital converter and the upper plate of the conversion capacitor are disconnected from the common mode voltage; after the upper plate of the sampling capacitor of the main analog-to-digital converter is disconnected from the common mode voltage, the upper plate of the conversion capacitor of the main analog-to-digital converter is disconnected from the common mode voltage; after the upper plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the common mode voltage, the lower plates of the sampling capacitors of the auxiliary analog-to-digital converter and the main analog-to-digital converter are disconnected from the input signal, and the auxiliary analog-to-digital converter performs successive approximation conversion to obtain a pre-conversion result.

23. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The number of sampling capacitors that need to be connected to the main analog-to-digital converter to sample the current input signal is determined based on the pre-conversion result of the auxiliary analog-to-digital converter, including: A combination of sampling capacitors corresponding to the maximum gain is selected according to the pre-conversion result of the auxiliary analog-to-digital converter and the proportional relationship between the capacitance values ​​of the sampling capacitors, and the sampling capacitors of the combination are connected to the circuit of the main analog-to-digital converter to achieve gain selection of the main analog-to-digital converter.

24. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The recovery module is used to recover the conversion result of the main analog-to-digital converter after gain adjustment to the result corresponding to the standard range of the main analog-to-digital converter, including: After the sampling is completed, the lower plate of the conversion capacitor of the main analog-to-digital converter is connected to the reference voltage, and the final conversion result is obtained through successive approximation conversion; The final conversion result is restored to the code value of the standard range through the recovery module.

25. The automatic gain selection method of the analog-to-digital conversion system according to claim 21, characterized in that: The method further comprises: After the voltage of the input signal is converted into a logarithmic voltage by the linear-to-logarithmic module, the logarithmic voltage is converted by the auxiliary analog-to-digital converter to obtain a logarithmic value conversion result; The logarithmic conversion result obtained by the auxiliary analog-to-digital converter is converted into a linear conversion result through the exponential conversion module.

26. A gain deviation calibration method, based on the analog-to-digital conversion system of claim 1, characterized in that: The method comprises: Get the actual weight of the total sampling capacitor; Get the actual weight of the highest weight capacitor of the conversion capacitor; The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor; Replace the original gain with the actual gain.

27. The gain deviation calibration method according to claim 26, characterized in that: The obtaining of the actual weight of the total sampling capacitance comprises: In the sampling phase, the sampling capacitor to be calibrated is connected to the upper reference voltage, and the remaining capacitors are connected to the lower reference voltage; Connect the sampling capacitor to be calibrated to the common mode voltage, convert it in a successive approximation manner, and obtain a digital code starting from the lowest bit; Obtaining actual weights of the respective sampling capacitors according to the digital code starting from the least significant bit and the actual weights of the capacitors starting from the least significant bit; The actual weights of the individual sampling capacitors are added together to obtain the actual weight of the total sampling capacitor.

28. The gain deviation calibration method according to claim 26, characterized in that: The step of obtaining the actual weight of the highest weight capacitor of the conversion capacitor comprises: During the sampling phase, the highest weight capacitor in the conversion capacitor is connected to the reference voltage; After sampling, the highest weight capacitor in the conversion capacitor is connected to the common mode voltage, and the other capacitors in the conversion capacitor are successively converted to obtain the digital code of each bit; According to the digital code of each bit and the actual weight of each capacitor, the actual weight of the highest weight capacitor of the conversion capacitor is obtained.

29. The gain deviation calibration method according to claim 26, characterized in that: The actual gain is obtained according to the actual weight of the total sampling capacitor and the actual weight of the highest weight capacitor of the conversion capacitor, including: The ratio of the actual weight of the total sampling capacitor to the actual weight of the highest weight capacitor of the conversion capacitor is taken as the actual gain.

30. A chip, characterized in that: The chip comprises the analog-to-digital conversion system according to any one of claims 1-20.

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