Laminated ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component in which peeling between ceramic layers is prevented. This laminated ceramic electronic component (10) is provided with: a laminated body (12) that includes a plurality of laminated ceramic layers (14) and a plurality of laminated internal electrode layers (16), and that includes a first main surface (12a) and a second main surface (12b) that face each other in a lamination direction (x), and a first side surface (12c) and a second side surface (12d) that face each other in a width direction (y) orthogonal to the lamination direction (x); and a first end surface (12e) and a second end surface (12f) facing each other in a longitudinal direction (z) orthogonal to the stacking direction (x) and the width direction (y). And a plurality of external electrodes (30), characterized in that the plurality of internal electrode layers (16) have: first internal electrode layers (16a) which are alternately laminated with the plurality of ceramic layers (14) and which are exposed on the first end surface (12e) and the second end surface (12f); and a second internal electrode layer (16b) alternately laminated with the plurality of ceramic layers (14) and exposed on the first side surface (12c) and the second side surface (12d), and further having a dummy electrode (40) disposed apart from the first internal electrode layer (16a) and the second internal electrode layer (16b) and exposed from any one of the first end surface (12e), the second end surface (12f), the first side surface (12c), and the second side surface (12d). The plurality of external electrodes (30) are provided with: a first external electrode (30a) and a second external electrode (30b) connected to the first internal electrode layer (16a); and a third external electrode (30c) and a fourth external electrode (30d) which are connected to the second internal electrode layer (16b), and in the dummy electrode (40), the line coverage of the conductive component in a region (44) separated by 50% or more from the exposed portion (42) of the dummy electrode (40) toward the center of the laminate (12) is less than 50%.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic electronic component. Background Art

[0002] In recent years, with the improvement of the performance of mobile phones such as smartphones, there is a demand for miniaturization of laminated ceramic electronic components. For example, a laminated ceramic capacitor is a laminated ceramic electronic component that alternately laminates internal electrode layers and ceramic layers and has a desired electrostatic capacitance by the number of laminated layers and the thickness of the ceramic layers.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor having a device body (a multilayer body) in which dielectric layers (ceramic layers) and internal electrode layers are alternately stacked.

[0004] However, in the structure of the laminated ceramic capacitor described in Patent Document 1, the plane area of ​​the internal electrode layer is smaller than the plane area of ​​the ceramic layer, and there is a step formed between the peripheral portion of the internal electrode layer and the ceramic layer, except for the lead portion of the internal electrode layer to the end face of the above-mentioned element body. Due to the influence of this step, the internal electrode layer is bent, and there are problems such as short circuits between the internal electrode layers and reduced high-temperature load reliability. In particular, the thinner the thickness of the dielectric layer (ceramic layer) and the more the internal electrode layer and the dielectric layer (ceramic layer) are stacked, the more likely it is that a short circuit between the internal electrode layers will occur, and there is a tendency for reliability to decrease.

[0005] Therefore, in order to solve the above problem, it is known to arrange a dummy electrode having a thickness corresponding to the step formed between the peripheral portion of the internal electrode layer and the ceramic layer except for the portion of the internal electrode layer led out to the end surface of the laminate on the outer layer.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2006-73623 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] However, since current also flows through the dummy electrodes, there are problems such as a longer current path, an increase in ESR and ESL, etc. In addition, due to the presence of the dummy electrodes, the fixing force between the ceramic layer and the dummy electrodes is weakened, so there is a possibility of peeling between the ceramic layers.

[0011] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component that prevents separation between ceramic layers.

[0012] Technical solutions to solve problems

[0013] The laminated ceramic electronic component of the present invention comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a laminated direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the laminated direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the laminated direction and the width direction, and is characterized in that the plurality of internal electrode layers comprises: a first internal electrode layer alternately laminated with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and a second internal electrode layer alternately laminated with the plurality of ceramic layers and exposed at the first end surface and the second end surface; A plurality of ceramic layers are alternately stacked and exposed on the first side surface and the second side surface, and also have a dummy electrode, which is arranged separately from the first internal electrode layer and the second internal electrode layer and exposed from any one of the first end surface, the second end surface, the first side surface and the second side surface. A plurality of external electrodes include: a first external electrode and a second external electrode, which are connected to the first internal electrode layer; and a third external electrode and a fourth external electrode, which are connected to the second internal electrode layer. In the dummy electrode, the line coverage of the conductive component in the area separated by more than 50% from the exposed portion of the dummy electrode toward the center of the stack is less than 50%.

[0014] According to the laminated ceramic electronic component of the present invention, in the dummy electrode, the line coverage of the conductive component in the area separated by more than 50% from the exposed portion of the dummy electrode toward the center of the laminate is less than 50%, so that the ceramic layers can be joined through the gap, thereby improving the bonding strength between the ceramic layers and improving the moisture resistance reliability. In addition, the gap makes it difficult for current to flow to the front end of the dummy electrode, which can shorten the current path, thereby also causing a decrease in ESL.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide a multilayer ceramic electronic component that prevents separation between ceramic layers.

[0017] The above objects, other objects, features and advantages of the present invention will become more apparent from the following description of specific embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the present invention.

[0019] Figure 2 FIG. 1 is a plan view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the present invention.

[0020] Figure 3This is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the present invention.

[0021] Figure 4 yes Figure 1 A cross-sectional view is concerned along line IV-IV.

[0022] Figure 5 yes Figure 1 The cross-sectional view is taken along line VV.

[0023] Figure 6 yes Figure 4 A cross-sectional view is concerned along line VI-VI.

[0024] Figure 7 yes Figure 4 A cross-sectional view is concerned along line VII-VII.

[0025] Figure 8 (a) is Figure 6 The enlarged view of the portion C shown is a view showing the structure of the dummy electrode on the side surface of the laminate. Figure 8 (b) is Figure 7 The enlarged view of the D portion shown is a view showing the structure of the dummy electrode on the end surface side of the stacked body.

[0026] Fig. 9 It is a diagram for explaining the measurement area of ​​the line coverage in the dummy electrode.

[0027] Fig.10 yes Figure 4 An enlarged view of section A is shown.

[0028] Fig.11 yes Figure 5 An enlarged view of part B is shown.

[0029] Fig.12 yes Figure 6 An enlarged view of section C is shown.

[0030] Fig.13 yes Figure 7 An enlarged view of section D is shown.

[0031] Fig.14 The figures are figures showing the printing patterns of internal electrode layers and dummy electrodes in a method for manufacturing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component involved in the present invention, (a) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface, the second side surface, the first end surface, and the second end surface, (b) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and the second side surface, and (c) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and the second end surface. DETAILED DESCRIPTION

[0032] 1. Laminated ceramic electronic components

[0033] A multilayer ceramic capacitor 10 is described as an example of a multilayer ceramic electronic component according to the present invention. Figure 1 FIG. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the present invention. Figure 2 FIG. 1 is a plan view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the present invention. Figure 3 This is a left side view showing a multilayer ceramic capacitor as an example of the multilayer ceramic electronic component according to the present invention. Figure 4 yes Figure 1 A cross-sectional view is concerned along line IV-IV. Figure 5 yes Figure 1 The cross-sectional view is taken along line VV. Figure 6 yes Figure 4 A cross-sectional view is concerned along line VI-VI. Figure 7 yes Figure 4 A cross-sectional view is concerned along line VII-VII. Figure 8 (a) is Figure 6 The enlarged view of the portion C shown is a view showing the structure of the dummy electrode on the side surface of the laminate. Figure 8 (b) is Figure 7 The enlarged view of the D portion shown is a view showing the structure of the dummy electrode on the end surface side of the stacked body. Fig. 9 It is a diagram for explaining the measurement area of ​​the line coverage in the dummy electrode. Fig.10 yes Figure 4 An enlarged view of section A is shown. Fig.11 yes Figure 5 An enlarged view of part B is shown. Fig.12 yes Figure 6 An enlarged view of section C is shown. Fig.13 yes Figure 7 An enlarged view of section D is shown. Fig.14 The figures are figures showing the printing patterns of internal electrode layers and dummy electrodes in a method for manufacturing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component involved in the present invention, (a) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface, the second side surface, the first end surface, and the second end surface, (b) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and the second side surface, and (c) is a printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and the second end surface.

[0034] The stacked ceramic capacitor 10 comprises: a stacked body 12, comprising a plurality of stacked ceramic layers 14, and a plurality of internal electrode layers 16 stacked on the ceramic layers 14, and comprising a first main surface 12a and a second main surface 12b opposite to each other in a stacking direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y orthogonal to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z orthogonal to the stacking direction x and the width direction y; and a plurality of external electrodes 30 connected to the internal electrode layers 16.

[0035] The dimension of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 in the longitudinal direction z is represented by L. M Size: L M The dimension is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 is denoted by W. M Dimensions. W M The dimension is preferably 0.2 mm or more and 1.0 mm or less. The dimension of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 in the stacking direction x is denoted as T. M Size. M The size is preferably 0.2 mm or more and 1.0 mm or less.

[0036] (Laminated body)

[0037] The stacked body 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. Furthermore, the stacked body 12 has a first main surface 12a and a second main surface 12b opposite to each other in a stacking direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y orthogonal to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z orthogonal to the stacking direction x and the width direction y.

[0038] The laminate 12 has a rectangular parallelepiped shape. In addition, the laminate 12 preferably has rounded corners and ridges. In addition, the so-called corner is a portion where three adjacent faces of the laminate 12 intersect, and the so-called ridge is a portion where two adjacent faces of the laminate 12 intersect. In addition, concavities and convexities may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0039] The stack 12 comprises: an effective layer portion 15a, in which a plurality of internal electrode layers 16 are arranged opposite to each other with ceramic layers 14 interposed therebetween in a stacking direction x connecting the first main surface 12a and the second main surface 12b to each other; a first outer layer portion 15b1, formed by a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 which is closest to the first main surface 12a among the plurality of internal electrode layers 16; and a second outer layer portion 15b2, formed by a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 which is closest to the second main surface 12b among the plurality of internal electrode layers 16.

[0040] The first outer layer portion 15 b 1 is located on the first principal surface 12 a side of the laminate 12 , and is an aggregate of a plurality of ceramic layers 14 located between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0041] The second outer layer portion 15 b 2 is located on the second main surface 12 b side of the laminate 12 , and is an aggregate of a plurality of ceramic layers 14 located between the second main surface 12 b and the internal electrode layer 16 closest to the second main surface 12 b .

[0042] Furthermore, a region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the effective layer portion 15a.

[0043] In addition, the stack 12 has side portions (W gap) 22a, 22b of the stack 12 which are located between one end of the width direction y of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the first side surface 12c, and between one end of the width direction y of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the second side surface 12d, and include the third lead portion 20c and the fourth lead portion 20d of the second internal electrode layer 16b.

[0044] In addition, the stack 12 has end portions (L gap) 24a, 24b of the stack 12 located between one end of the length direction z of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the first end face 12e, and between one end of the length direction z of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the second end face 12f, and including the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a.

[0045] The ceramic layer 14 may be made of a dielectric material, for example. For example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 may be used as the dielectric material. In addition, materials containing secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components may also be used.

[0046] The number of stacked ceramic layers 14 is not particularly limited, but is preferably 4 or more and 1000 or less including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the ceramic layer 14 is preferably 0.4 μm or more and 1.0 μm or less.

[0047] The size of the stack 12 is not particularly limited. The dimension in the length direction z connecting the first end face 12e and the second end face 12f of the stack 12 is set to L dimension. The L dimension is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y connecting the first side face 12c and the second side face 12d of the stack 12 is set to W dimension. The W dimension is preferably 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x connecting the first main face 12a and the second main face 12b of the stack 12 is set to T dimension. The T dimension is preferably 0.2 mm or more and 1.0 mm or less.

[0048] (Internal electrode layer)

[0049] The internal electrode layer 16 includes a first internal electrode layer 16 a and a second internal electrode layer 16 b .

[0050] The first internal electrode layer 16a is arranged on the plurality of ceramic layers 14. In addition, the first internal electrode layer 16a is led out to the first end face 12e and the second end face 12f. The first internal electrode layer 16a includes a first opposing portion 18a located inside the stacked body 12, a first lead portion 20a connected to the first opposing portion 18a and led out to the first end face 12e, and a second lead portion 20b led out to the second end face 12f.

[0051] The shape of the first opposing portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0052] The shapes of the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed to be inclined (conical) in plan view. In addition, the shape may be a cone in plan view that is inclined toward a certain direction.

[0053] The second internal electrode layer 16b is arranged on the plurality of ceramic layers 14. In addition, the second internal electrode layer 16b is led out to the first side surface 12c and the second side surface 12d. The second internal electrode layer 16b has a second opposing portion 18b located inside the stacked body 12, a third lead portion 20c connected to the second opposing portion 18b and led out to the first side surface 12c, and a fourth lead portion 20d led out to the second side surface 12d.

[0054] The shape of the second opposing portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0055] The shapes of the third lead portion 20c and the fourth lead portion 20d of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed to be inclined (conical) in plan view. In addition, the shape may be a cone in plan view that is inclined toward a certain direction.

[0056] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0057] The number of the first internal electrode layers 16a is not particularly limited, but is preferably, for example, 1 or more and 500 or less. The number of the second internal electrode layers 16b is not particularly limited, but is preferably, for example, 1 or more and 500 or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 2 or more and 1000 or less.

[0058] The thickness of the first internal electrode layer 16 a is not particularly limited, but is preferably, for example, not less than 0.4 μm and not more than 0.8 μm.

[0059] The thickness of the second internal electrode layer 16 b is not particularly limited, but is preferably, for example, not less than 0.4 μm and not more than 0.8 μm.

[0060] In the present embodiment, the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0061] When piezoelectric ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include, for example, PZT (lead zirconate titanate)-based ceramic materials.

[0062] When semiconductor ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel ceramic materials and the like.

[0063] In addition, when magnetic ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as an inductor element. In addition, when it functions as an inductor element, the internal electrode layer becomes a coil-shaped conductor. As specific examples of magnetic ceramic materials, for example, ferrite ceramic materials can be cited.

[0064] That is, the multilayer ceramic electronic component according to the present embodiment can appropriately function not only as the multilayer ceramic capacitor 10 but also as a ceramic piezoelectric element, a thermistor element, or an inductor element by appropriately changing the material and structure of the multilayer body 12 .

[0065] (Dummy electrode)

[0066] The dummy electrode 40 is arranged separately from the first internal electrode layer 16a and the second internal electrode layer 16b, and is exposed from any one of the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d. If the dummy electrode 40 is exposed from any one of the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d, the portion where the step exists can be filled with the dummy electrode 40 by an amount corresponding to the thickness of the first internal electrode layer 16a and the second internal electrode layer 16b, so that the deformation of the internal electrode layer 16 and the ceramic layer 14 during pressing can be reduced, and compaction can be ensured.

[0067] In the present embodiment, the dummy electrode 40 includes a first dummy electrode 40 a , a second dummy electrode 40 b , a third dummy electrode 40 c , and a fourth dummy electrode 40 d .

[0068] A first dummy electrode 40a is disposed on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is disposed, separated from the first internal electrode layer 16a and exposed on the first side surface 12c. The first dummy electrode 40a faces the third lead portion 20c of the second internal electrode layer 16b via the ceramic layer 14.

[0069] The shape of the first dummy electrode 40a is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0070] A second dummy electrode 40b is disposed on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is disposed, separated from the first internal electrode layer 16a and exposed on the second side surface 12d. The second dummy electrode 40b is opposed to the fourth lead portion 20d of the second internal electrode layer 16b via the ceramic layer 14.

[0071] The shape of the second dummy electrode 40b is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a cone when viewed from above that is inclined in a certain direction.

[0072] A third dummy electrode 40c is disposed on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is disposed, separated from the second internal electrode layer 16b and exposed on the first end surface 12e. The third dummy electrode 40c faces the first lead portion 20a of the first internal electrode layer 16a via the ceramic layer 14.

[0073] The shape of the third dummy electrode 40c is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0074] A fourth dummy electrode 40d is disposed on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is disposed, separated from the second internal electrode layer 16b and exposed at the second end surface 12f. The fourth dummy electrode 40d faces the second lead portion 20b of the second internal electrode layer 16b via the ceramic layer 14.

[0075] The shape of the fourth dummy electrode 40d is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0076] The first dummy electrode 40a and the second dummy electrode 40b are preferably exposed on at least one of the first side surface 12c and the second side surface 12d on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is arranged. In addition, the first dummy electrode 40a and the second dummy electrode 40b are further preferably exposed on both the first side surface 12c and the second side surface 12d on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is arranged. By configuring in this way, the deformation generated when the stacked body 12 is pressed can be reduced.

[0077] The third dummy electrode 40c and the fourth dummy electrode 40d are preferably exposed on at least one of the first end face 12e and the second end face 12f on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is arranged. In addition, the third dummy electrode 40c and the fourth dummy electrode 40d are further preferably exposed on both the first end face 12e and the second end face 12f on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is arranged. By configuring in this way, the deformation generated when the laminate 12 is pressed can be reduced.

[0078] The dummy electrode 40 includes a conductive material as a conductive component. The conductive material of the dummy electrode 40 can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy including at least one of these metals such as an Ag-Pd alloy.

[0079] The dummy electrode 40 is provided with a line coverage area of ​​50% or less in an end area 44 of the dummy electrode 40 separated by more than 50% from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12. Figure 8 As shown in (a), the first dummy electrode 40a is provided with an end region 44a of the first dummy electrode 40a having a line coverage of less than 50% in a region separated by more than 50% from the exposed portion 42a of the first dummy electrode 40a toward the center of the stack 12. Similarly, the second dummy electrode 40b is provided with an end region 44b of the second dummy electrode 40b having a line coverage of less than 50% in a region separated by more than 50% from the exposed portion 42b of the second dummy electrode 40b toward the center of the stack 12. In addition, as Figure 8 As shown in (b), the third dummy electrode 40c is provided with an end region 44c of the second dummy electrode 40b having a line coverage of 50% or less in a region separated by more than 50% from the exposed portion 42c of the third dummy electrode 40c toward the center of the stack 12. Similarly, the fourth dummy electrode 40d is provided with an end region 44d of the fourth dummy electrode 40d having a line coverage of 50% or less in a region separated by more than 50% from the exposed portion 42d of the fourth dummy electrode 40d toward the center of the stack 12.

[0080] Here, the line coverage refers to the ratio of the total length of the conductive component actually present in the dummy electrode to the total length of the dummy electrode 40 .

[0081] Next, the method for measuring the line coverage is described. First, in the case of the first dummy electrode 40a and the second dummy electrode 40b, grinding is performed until 1 / 2 of the length direction z of the stack 12 to expose the WT section. In addition, in the case of the third dummy electrode 40c and the fourth dummy electrode 40d, grinding is performed until 1 / 2 of the width direction y of the stack 12 to expose the LT section. Next, the WT section or the LT section is photographed using a digital microscope (VHX manufactured by Keyence Corporation). Next, image recognition is performed on each section image using image processing software (HALCON manufactured by MVTec Corporation). In the case of the WT section, the measurement area F is preferably set to a quadrilateral area with a width direction y of 5μm and a stacking direction x of 30μm. In addition, in the case of the LT section, the measurement area F is preferably set to a quadrilateral area with a length direction z of 5μm and a stacking direction x of 30μm. The coverage is calculated by the ratio of the total length of the conductive components of the actual dummy electrodes to the total length of the dummy electrodes 40 in the region. Therefore, the region with a line coverage of 50% or less is a region where the ratio of the total length of the conductive components of the actual dummy electrodes to the total length of the dummy electrodes 40 is 50% or less. For example, Fig. 9 The measurement areas F1 to F2 of the line coverage of the first dummy electrode 40a in the WT cross section are shown. N In the measurement area F1 to F N In the embodiment, the line coverage is measured by calculating the total length of the first dummy electrodes 40 a and the total length of the conductive component in which the first dummy electrodes 40 a exist.

[0082] By providing a region with a line coverage of 50% or less in the end region 44 of the dummy electrode, the ceramic layers 14 can be bonded to each other via the gap 46, thereby having the effect of improving the bonding strength between the ceramic layers 14 and improving the moisture resistance reliability. In addition, the gap 46 makes it difficult for the current to flow to the front end of the end region 44 of the dummy electrode 40, and the current path can be shortened, thereby having the effect of reducing the ESL. Furthermore, in the case of moisture intrusion from the outside, by selectively concentrating the moisture in the end region 44 of the dummy electrode 40 with a line coverage of 50% or less, it has the effect of ensuring the moisture resistance reliability of the effective layer portion 15a.

[0083] In addition, the ratio of the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 is preferably 50% or more and 80% or less. By making the ratio of the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 to be 50% or more, the ceramic layer 14 can be joined via the void 46, thereby having the effect of causing the improvement of the bonding strength between the ceramic layers 14 and the improvement of the moisture resistance reliability. Furthermore, in the case of moisture intrusion from the outside, by selectively concentrating the moisture in the end region 44 of the dummy electrode 40 with a line coverage of 50% or less, the moisture resistance reliability of the effective layer portion 15a is ensured. In addition, by making the ratio of the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 to be 80% or less, the current path no longer flows to the front end of the end region 44 of the dummy electrode 40 through the void 46, and the current path can be shortened, thereby having the effect of causing the reduction of ESL. On the other hand, if the ratio of the area of ​​the gap 46 to the area of ​​the end region 44 of the dummy electrode 40 is greater than 80%, the step generated between the internal electrode layer 16 and the dummy electrode 40 becomes larger due to the difference in thickness between the internal electrode layer 16 and the dummy electrode 40. As a result, when pressing, a portion of the stacking direction x of the stacked body 12 is locally thinner due to the pressing of the step, and the risk of reduced moisture resistance reliability increases.

[0084] Here, the thickness of the first internal electrode layer 16a in the stacking direction x is set to t1, and the thickness of the second internal electrode layer 16b in the stacking direction x is set to t2. In addition, the thickness of the first dummy electrode 40a in the stacking direction x is set to t3, the thickness of the second dummy electrode 40b in the stacking direction x is set to t4, the thickness of the third dummy electrode 40c in the stacking direction x is set to t5, and the thickness of the fourth dummy electrode 40d in the stacking direction x is set to t6.

[0085] The thickness t3, t4, t5, and t6 of the dummy electrode 40 are preferably formed thinner than the thickness t1 and t2 of the internal electrode layer 16. More specifically, the thickness t3, t4, t5, and t6 of the dummy electrode 40 are preferably 75% or more and 95% or less relative to the thickness t1 and t2 of the internal electrode layer 16. By making the thickness t3, t4, t5, and t6 of the dummy electrode 40 75% or more and 95% or less relative to the thickness t1 and t2 of the internal electrode layer 16, the step can be fully filled, and the deformation of the internal electrode layer 16 and the ceramic layer 14 during pressing can be reduced.

[0086] In addition, the length w1 of the first dummy electrode 40a exposed on the first side surface 12c in the width direction y of the laminate 12 is preferably 50% or more and 60% or less of the length w3 of the third lead portion 20c of the second internal electrode layer 16b in the width direction y of the laminate 12. By setting the length w1 of the first dummy electrode 40a exposed on the first side surface 12c in the width direction y of the laminate 12 to be 50% or more and 60% or less of the length w3 of the third lead portion 20c of the second internal electrode layer 16b in the width direction y of the laminate 12, it is possible to reduce the deformation generated when the laminate 12 is pressed while maintaining the current path at an appropriate distance. Similarly, the length w2 of the second dummy electrode 40b exposed on the second side surface 12d in the width direction y of the laminate 12 is preferably 50% or more and 60% or less of the length w4 of the fourth lead portion 20d of the second internal electrode layer 16b in the width direction y of the laminate 12. By setting the length w2 of the stack 12 in the width direction y of the second dummy electrode 40b exposed on the second side surface 12d to be greater than 50% and less than 60% of the length w4 of the stack 12 in the width direction y of the fourth lead portion 20d of the second internal electrode layer 16b, it is possible to reduce the deformation generated when the stack 12 is pressed while maintaining the current path at an appropriate distance.

[0087] Furthermore, the central portion M1 of the first dummy electrode 40a exposed on the first side surface 12c in the longitudinal direction z of the laminate 12 is preferably located within 3% of the central portion M of the second internal electrode layer 16b in the longitudinal direction z of the laminate 12. By arranging in this way, the dummy electrode 40 and the second internal electrode layer 16b are uniformly pressed, so that it is difficult to generate structural defects such as peeling between the ceramic layers 14. Similarly, the central portion M2 of the second dummy electrode 40b exposed on the second side surface 12d in the longitudinal direction z of the laminate 12 is preferably located within 3% of the central portion M of the second internal electrode layer 16b in the longitudinal direction z of the laminate 12. By arranging in this way, the dummy electrode 40 and the second internal electrode layer 16b are uniformly pressed, so that it is difficult to generate structural defects such as peeling between the ceramic layers 14.

[0088] In addition, the length l1 of the third dummy electrode 40c exposed at the first end surface 12e in the length direction z of the laminate 12 is preferably 50% or more and 60% or less of the length l3 of the laminate 12 in the length direction z of the first lead portion 20a of the first internal electrode layer 16a. By setting the length l1 of the third dummy electrode 40c exposed at the first end surface 12e in the length direction z of the laminate 12 to 50% or more and 60% or less of the length l3 of the laminate 12 in the length direction z of the first lead portion 20a of the first internal electrode layer 16a, it is possible to reduce the deformation generated when the laminate 12 is pressed while maintaining the current path at an appropriate distance. Similarly, the length l2 of the fourth dummy electrode 40d exposed at the second end surface 12f in the length direction z of the laminate 12 is preferably 50% or more and 60% or less of the length l4 of the laminate 12 in the length direction z of the second lead portion 20b of the first internal electrode layer 16a. By setting the length l2 of the stack 12 of the fourth dummy electrode 40d exposed at the second end face 12f in the longitudinal direction z to be greater than 50% and less than 60% of the length l4 of the stack 12 of the second lead portion 20b of the first internal electrode layer 16a in the longitudinal direction z, it is possible to reduce the deformation generated when the stack 12 is pressed while maintaining the current path at an appropriate distance.

[0089] Furthermore, the central portion N1 of the third dummy electrode 40c exposed at the first end face 12e in the width direction y of the laminate 12 is preferably located within 3% of the central portion N of the first internal electrode layer 16a in the width direction y of the laminate 12. By arranging in this way, the dummy electrode 40 and the first internal electrode layer 16a are uniformly pressed, so that there is an effect that structural defects such as peeling between the ceramic layers 14 are not easily generated. Similarly, the central portion N2 of the fourth dummy electrode 40d exposed at the second end face 12f in the width direction y of the laminate 12 is preferably located within 3% of the central portion N of the first internal electrode layer 16a in the width direction y of the laminate 12. By arranging in this way, the dummy electrode 40 and the first internal electrode layer 16a are uniformly pressed, so there is an effect that structural defects such as peeling between the ceramic layers 14 are not easily generated.

[0090] (External Electrode)

[0091] The external electrode 30 includes a first external electrode 30 a , a second external electrode 30 b , a third external electrode 30 c , and a fourth external electrode 30 d .

[0092] The first external electrode 30a is disposed on the first end surface 12e and connected to the first internal electrode layer 16a. The first external electrode 30a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0093] The second external electrode 30b is disposed on the second end surface 12f and connected to the first internal electrode layer 16a. The second external electrode 30b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0094] The third external electrode 30c is disposed on the first side surface 12c and is connected to the second internal electrode layer 16b. In addition, the third external electrode 30c may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0095] The fourth external electrode 30d is disposed on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 30d may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0096] It is preferable that each of the first external electrode 30 a , the second external electrode 30 b , the third external electrode 30 c , and the fourth external electrode 30 d includes a base electrode layer 32 and a plating layer 34 .

[0097] In other words, the first external electrode 30a preferably includes the first base electrode layer 32a and the first plating layer 34a. The second external electrode 30b preferably includes the second base electrode layer 32b and the second plating layer 34b. The third external electrode 30c preferably includes the third base electrode layer 32c and the third plating layer 34c. The fourth external electrode 30d preferably includes the fourth base electrode layer 32d and the fourth plating layer 34d.

[0098] The foundation electrode layer 32 includes a first foundation electrode layer 32a, a second foundation electrode layer 32b, a third foundation electrode layer 32c, and a fourth foundation electrode layer 32d. The foundation electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0099] First, the case where the base electrode layer 32 is formed by a sintered layer is described. The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. In addition, as the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Furthermore, the sintered layer can also be a multilayer.

[0100] The sintered layer is obtained by applying a conductive paste containing a glass component and a metal component to the stacked body 12 and sintering it. The sintered layer may be obtained by simultaneously sintering the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the stacked small pieces, or may be obtained by sintering the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 to obtain the stacked body 12, and then applying the conductive paste and sintering it. In addition, when the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the stacked small pieces are sintered simultaneously, it is preferable to form the sintered layer by sintering a material to which a ceramic component is added instead of a glass component.

[0101] The thickness of the first sintered layer and the second sintered layer located at the central part of the stacking direction x connecting the first main surface 12a and the second main surface 12b, and the thickness of the first sintered layer and the second sintered layer in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f (end surface center thickness) is preferably greater than 5 μm and less than 30 μm, for example.

[0102] In addition, when a sintered layer is also provided on a portion of the first principal surface 12a or a portion of the second principal surface 12b, the thickness of the first sintered layer and the second sintered layer located on the first principal surface 12a or the second principal surface 12b in the central portion of the longitudinal direction z connecting the first end surface 12e and the second end surface 12f, and in the stacking direction x connecting the first principal surface 12a and the second principal surface 12b, is preferably, for example, greater than 5 μm and less than 10 μm.

[0103] Next, the case where the base electrode layer 32 is formed by the conductive resin layer is described. The conductive resin layer is arranged on the sintered layer to cover the sintered layer, or it can be arranged directly on the laminate 12 without providing the sintered layer. In addition, the conductive resin layer can completely cover the sintered layer, or it can cover a part of the sintered layer. Furthermore, the conductive resin layer can also be a multilayer.

[0104] The conductive resin layer includes a thermosetting resin and a metal. Since the conductive resin layer includes a thermosetting resin, it is more flexible than, for example, a plated film or a sintered layer including a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the multilayer ceramic capacitor 10.

[0105] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi or alloys containing them can be used. In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using metal powder coated with Ag on the surface of the metal powder, Cu, Ni, Sn, Bi or alloy powders thereof are preferably used as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals and is therefore suitable for electrode materials, and Ag is a precious metal and therefore does not oxidize and has high weather resistance. In addition, it is because the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag.

[0106] Furthermore, as the metal contained in the conductive resin layer, metals subjected to oxidation resistance treatment may be used for Cu and Ni. In addition, as the metal contained in the conductive resin layer, metal powders obtained by coating the surface of Sn, Ni, or Cu may be used. When using metal powders obtained by coating the surface of Sn, Ni, or Cu, it is preferred that Ag, Cu, Ni, Sn, Bi, or alloy powders thereof be used as the metal powder.

[0107] The metal contained in the conductive resin layer is mainly responsible for the conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0108] The metal contained in the conductive resin layer may be a spherical metal, a flat metal, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0109] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0110] In addition, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol, amine, anhydride, imidazole, active ester, and amide-imide can be used as the curing agent for the epoxy resin.

[0111] The thickness of the thickest portion of the conductive resin layer is preferably, for example, 5 μm or more and 30 μm or less.

[0112] Next, the case where the base electrode layer 32 is formed of a thin film layer will be described. When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition. The thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0113] (Plating layer)

[0114] The plating layer 34 includes a first plating layer 34a configured to cover the first base electrode layer 32a, a second plating layer 34b configured to cover the second base electrode layer 32b, a third plating layer 34c configured to cover the third base electrode layer 32c, and a fourth plating layer 34d configured to cover the fourth base electrode layer 32d.

[0115] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0116] In addition, the plating layer 34 may be formed of multiple layers. The plating layer 34 is preferably a two-layer structure in the order of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer 32 from being corroded by the solder when the multilayer ceramic capacitor 10 is mounted. In addition, the Sn plating layer can improve the wettability of the solder when the multilayer ceramic capacitor 10 is mounted, and can be easily mounted.

[0117] Furthermore, the thickness of each of the plating layers 34 is preferably 4 μm or more and 10 μm or less.

[0118] Any one or each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may have a plated layer 34 formed directly on the surface of the laminate 12. That is, the laminated ceramic capacitor 10 may have a structure including a plated layer 34 that is directly electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plated layer 34 may be formed directly after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0119] When the plating layer 34 is formed directly on the laminate 12 without providing a base electrode layer 32, the height can be reduced, i.e., thinned, by an amount corresponding to the reduction in the thickness of the base electrode layer 32 or converted into the thickness of the laminate 12, i.e., the thickness of the effective layer portion 15a, thereby increasing the design freedom of the thin chip.

[0120] When the plated layer 34 is formed directly on the laminate 12 , the plated layer 34 preferably includes a lower plated electrode formed on the surface of the laminate 12 and an upper plated electrode formed on the surface of the lower plated electrode.

[0121] Preferably, the lower plated electrode and the upper plated electrode each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0122] The lower plated electrode is preferably formed using Ni having solder barrier properties. In addition, the upper plated electrode is preferably formed using Sn or Au having good solder wettability.

[0123] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, the lower plated electrode is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plated electrode may be formed as required, and the first external electrode and the second external electrode may each be composed only of the lower plated electrode.

[0124] When the plated layer 34 is formed directly on the laminate 12 , the plated layer 34 may have an upper plated electrode as the outermost layer, or another plated electrode may be further formed on the surface of the upper plated electrode.

[0125] When the plating layer 34 is formed directly on the laminate 12 , the thickness of each plating layer 34 is preferably 4 μm or more and 10 μm or less.

[0126] When the plating layer 34 is formed directly on the laminate 12, the plating layer 34 preferably does not contain glass. In addition, the metal ratio per unit volume of the plating layer 34 is preferably 99 volume % or more.

[0127] according to Figure 1 In the illustrated laminated ceramic capacitor 10, in the dummy electrode 40, the line coverage of the conductive component of the region 44 separated by more than 50% from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12 is less than 50%. By setting such a structure, the ceramic layers 14 can be joined via the gaps 46, so the bonding strength between the ceramic layers 14 can be improved, and the moisture resistance reliability can also be improved. In addition, the gaps 46 prevent the current from flowing to the front end of the dummy electrode 40, and the current path can be shortened, thereby also causing a decrease in ESL. Furthermore, in the case of moisture intrusion from the outside, by selectively concentrating the moisture in the end region 44 of the dummy electrode 40 with a line coverage of less than 50%, the moisture resistance reliability of the effective layer portion 15a is ensured.

[0128] also, Figure 1 The dummy electrodes 40 ( 40 a , 40 b ) of the multilayer ceramic capacitor 10 shown are preferably exposed on at least one of the first side surface 12 c and the second side surface 12 d on the ceramic layer 14 where the first internal electrode layer 16 a is arranged. This can reduce deformation generated when the multilayer body 12 is pressed.

[0129] also, Figure 1The dummy electrodes 40 ( 40 c , 40 d ) of the multilayer ceramic capacitor 10 shown are preferably exposed on at least one of the first end face 12 e and the second end face 12 f on the ceramic layer 14 where the second internal electrode layer 16 b is arranged. This can reduce the deformation generated when the multilayer body 12 is pressed.

[0130] also, Figure 1 The thicknesses t3, t4, t5, and t6 of the dummy electrode 40 in the stacking direction x of the multilayer ceramic capacitor 10 shown are preferably smaller than the thicknesses t1 and t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x. Figure 1 The thickness t3, t4, t5, t6 of the dummy electrode 40 in the stacking direction x of the multilayer ceramic capacitor 10 shown is preferably 75% or more and 95% or less of the thickness t1, t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x. This can sufficiently fill the step (the difference between the thickness t3, t4, t5, t6 of the dummy electrode 40 in the stacking direction x and the thickness t1, t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x), and can reduce the deformation of the internal electrode layer 16 and the ceramic layer 14 during pressing.

[0131] In addition, Figure 1 The lengths w1 and w2 of the dummy electrodes 40a and 40b exposed on the first side surface 12c or the second side surface 12d of the laminated ceramic capacitor 10 shown in the width direction y of the laminated body 12 are preferably 50% or more and 60% or less of the lengths w3 and w4 of the third lead portion 20c of the second internal electrode layer 16b and the fourth lead portion 20d of the second internal electrode layer 16b in the width direction y of the laminated body 12. Thus, the deformation generated when the laminated body 12 is pressed can be reduced while maintaining the current path at an appropriate distance.

[0132] In addition, Figure 1 The central portions M1 and M2 in the length direction z of the laminated body 12 of the dummy electrodes 40a and 40b exposed on the first side surface 12c or the second side surface 12d of the laminated ceramic capacitor 10 shown are preferably located within 3% of the central portion M in the length direction z of the laminated body 12 of the second internal electrode layer 16b exposed on the first side surface 12c or the second side surface 12d. As a result, the dummy electrodes 40a and 40b and the second internal electrode layer 16b are uniformly pressed, so that structural defects such as peeling between the ceramic layers 14 are less likely to occur.

[0133] In addition, Figure 1In the dummy electrode 40 of the laminated ceramic capacitor 10 shown, the area of ​​the gap 46 is preferably 50% or more and 80% or less relative to the area of ​​the region 44 separated by more than 50% from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12. As a result, the ceramic layers 14 can be joined via the gap 46, thereby having the effect of improving the bonding strength between the ceramic layers 14 and improving the moisture resistance reliability. Furthermore, in the case of moisture intrusion from the outside, by selectively concentrating the moisture in the end region 44 of the dummy electrode 40 with a line coverage of less than 50%, the moisture resistance reliability of the effective layer portion 15a is ensured. The gap 46 prevents the current path from flowing to the front end of the end region 44 of the dummy electrode 40, and the current path can be shortened, thereby having the effect of causing a decrease in ESL.

[0134] 2. Method for manufacturing a laminated ceramic electronic component

[0135] Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 as an example of the multilayer ceramic electronic component according to the present invention will be described.

[0136] First, a conductive paste for a dielectric sheet, an internal electrode, and a dummy electrode is prepared. The conductive paste for a dielectric sheet, an internal electrode, and a dummy electrode contains a binder and a solvent. The binder and the solvent can be known binders and solvents.

[0137] Next, a conductive paste for the internal electrodes and the dummy electrodes is printed on the dielectric sheet in a given pattern, for example, by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of internal electrode layers and dummy electrodes is prepared. More specifically, a screen plate for printing the first internal electrode layer 16a, the first dummy electrode 40a, and the second dummy electrode 40b, and a screen plate for printing the second internal electrode layer 16b, the third dummy electrode 40c, and the fourth dummy electrode 40d are prepared, respectively, and a printer capable of printing the two screen plates separately is used, such as Fig.14 By printing as in (a) of the present invention, the internal electrode layer 16 and the dummy electrode 40 of the present invention can be printed. Fig.14 In (a), the printed patterns of the internal electrode layer and the dummy electrode in this embodiment are shown. That is, the pattern 80 of the first internal electrode layer 16a, the first dummy electrode 40a, and the second dummy electrode 40b, and the pattern 82 of the second internal electrode layer 16b, the third dummy electrode 40c, and the fourth dummy electrode 40d are printed, and when the laminate is cut in the subsequent process, the internal electrode layer 16a is cut along the inner electrode layer 16b. Fig.14By cutting along the cutting lines 90 indicated by the dotted lines in (a), the laminated body 12 including the first internal electrode layer 16a, the second internal electrode layer 16b, the first dummy electrode 40a, the second dummy electrode 40b, the third dummy electrode 40c, and the fourth dummy electrode 40d can be produced.

[0138] In addition, in the present embodiment, the first dummy electrode 40a, the second dummy electrode 40b, the third dummy electrode 40c, and the fourth dummy electrode 40d are provided, but the present invention is not limited thereto. That is, for example, in the case where the first dummy electrode 40a and the second dummy electrode 40b are provided but the third dummy electrode 40c and the fourth dummy electrode 40d are not provided, Fig.14 By printing the first internal electrode layer 16a, the second internal electrode layer 16b, the first dummy electrode 40a, and the second dummy electrode 40b as in (b), it is possible to form a portion of the effective layer portion 15a that has the first dummy electrode 40a and the second dummy electrode 40b but does not have the third dummy electrode 40c and the fourth dummy electrode 40d. In addition, for example, in the case where the first dummy electrode 40a and the second dummy electrode 40b are not present but the third dummy electrode 40c and the fourth dummy electrode 40d are present, by printing the first dummy electrode 40a and the second dummy electrode 40b as in (b), it is possible to form a portion of the effective layer portion 15a that has the first dummy electrode 40a and the second dummy electrode 40b but does not have the third dummy electrode 40c and the fourth dummy electrode 40d. Fig.14 By printing the first internal electrode layer 16a, the second internal electrode layer 16b, the third dummy electrode 40c and the fourth dummy electrode 40d as in (c), it is possible to form a portion of the effective layer portion 15a that does not have the first dummy electrode 40a and the second dummy electrode 40b but has the third dummy electrode 40c and the fourth dummy electrode 40d.

[0139] Here, the portion to be the effective layer portion 15a is formed by laminating sheets on which the internal electrode layer 16 and the dummy electrode 40 are printed so as to obtain a desired structure. In the present embodiment, the patterns of the internal electrode and the dummy electrode are printed by gravure printing.

[0140] Next, a portion that will become the first outer layer portion 15b1 on the first main surface 12a side is formed by laminating a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed. Then, a portion that will become the effective layer portion 15a prepared as described above is laminated, and a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are laminated on the portion that will become the effective layer portion 15a, thereby forming a portion that will become the second outer layer portion 15b2 on the second main surface 12b side. In this way, a laminated sheet can be produced.

[0141] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like to produce a laminated block.

[0142] Next, the stacked block is cut into a given size to obtain stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0143] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the ceramic and the internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0144] The first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminate 12. In addition, the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d are formed on the first side face 12c and the second side face 12d of the fired laminate 12.

[0145] When a sintered layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied and then sintered to form the base electrode layer 32. The sintering temperature at this time is preferably 700° C. to 900° C. In the present embodiment, the base electrode layer 32 is formed of a sintered layer.

[0146] Here, various methods can be used as a method of forming a sintered layer as the base electrode layer 32. For example, the third base electrode layer 32c and the fourth base electrode layer 32d can be applied by extruding a conductive paste from a slit. In the case of this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0147] In addition, it is also possible to form it using a roller transfer method. In the case of the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0148] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminated body 12. When the first base electrode layer 32a and the second base electrode layer 32b are formed as the fired layers as the base electrode layers 32, a conductive paste containing a glass component and a metal component is applied and then fired to form the base electrode layers 32. The temperature of the firing treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0149] Here, various methods can be used as a method for forming the first foundation electrode layer 32a and the second foundation electrode layer 32b. For example, a method such as dipping can be used to form the first foundation electrode layer 32a and the second foundation electrode layer 32b not only on the first end surface 12e and the second end surface 12f, but also to extend to a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0150] In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed not only on the first end face 12e and the second end face 12f by the DIP method, but also extended to a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0151] In addition, in this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are fired after the third base electrode layer 32c and the fourth base electrode layer 32d are fired, but the first base electrode layer 32a and the second base electrode layer 32b and the third base electrode layer 32c and the fourth base electrode layer 32d may be fired at the same time.

[0152] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the sintered layer, or the conductive resin layer may be formed directly on the laminate without forming a sintered layer.

[0153] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to a sintered layer or a laminate, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to below 100 ppm.

[0154] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 using a baked layer, for example, a method of applying the conductive paste by squeezing it out from a slit or a roll transfer method can be used.

[0155] When the base electrode layer 32 is formed by a thin film layer, masking or the like is performed and the base electrode layer 32 can be formed by a thin film forming method such as sputtering or evaporation at a desired location. The base electrode layer 32 formed by a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0156] Finally, a plating layer 34 is formed. In addition, the plating layer 34 can be formed on the surface of the base electrode layer 32, or can be directly formed on the laminate 12. In the present embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. In more detail, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires pretreatment using a catalyst or the like in order to increase the plating deposition rate, and has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0157] As above, it is possible to produce Figure 1 A multilayer ceramic capacitor 10 described in .

[0158] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0159] That is, various changes can be made to the above-described embodiment and each modified example with respect to mechanism, shape, material, number, position, arrangement, etc. within the scope not departing from the technical idea and purpose of the present invention, and they are included in the present invention.

[0160] In addition, in the present embodiment, a three-terminal stacked ceramic capacitor is described, but it can also be used for a two-terminal stacked ceramic electronic component, for example. That is, the stacked ceramic electronic component has a stacked body and a plurality of external electrodes, the stacked body includes a ceramic layer and a plurality of internal electrode layers, and includes a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction and the width direction, wherein the plurality of internal electrode layers include: a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and a second internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface. The laminate is alternately stacked and exposed on the first side surface and the second side surface, and further comprises a dummy electrode, which is arranged separately from the first internal electrode layer and the second internal electrode layer and exposed from any one of the first end surface and the second end surface, and the plurality of external electrodes include: a first external electrode, which is arranged on the first end surface and connected to the first internal electrode layer; and a second external electrode, which is arranged on the second end surface and connected to the second internal electrode layer, and in the dummy electrode, the line coverage of the conductive component of the region separated by 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is less than 50%. By configuring in this way, it is possible to prevent peeling between ceramic layers.

[0161] <1>

[0162] A laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction and the width direction, wherein:

[0163] The plurality of internal electrode layers have:

[0164] a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and

[0165] a second internal electrode layer which is alternately stacked with the plurality of ceramic layers and is exposed on the first side surface and the second side surface;

[0166] further comprising a dummy electrode, which is arranged separately from the first internal electrode layer and the second internal electrode layer and is exposed from any one of the first end surface, the second end surface, the first side surface, and the second side surface,

[0167] The plurality of external electrodes include:

[0168] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0169] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0170] In the dummy electrode, a line coverage of a conductive component in a region separated by 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is less than 50%.

[0171] <2>

[0172] The multilayer ceramic electronic component according to <1>,

[0173] The dummy electrode is exposed on at least one of the first side surface and the second side surface on the ceramic layer on which the first internal electrode layer is arranged.

[0174] <3>

[0175] The multilayer ceramic electronic component according to <1> or <2>,

[0176] The dummy electrode is exposed on at least one of the first end surface and the second end surface on the ceramic layer on which the second internal electrode layer is arranged.

[0177] <4>

[0178] The multilayer ceramic electronic component according to any one of <1> to <3>,

[0179] The thickness of the dummy electrode in the stacking direction is smaller than the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

[0180] <5>

[0181] The multilayer ceramic electronic component according to any one of <1> to <4>,

[0182] The thickness of the dummy electrode in the stacking direction is not less than 75% and not more than 95% of the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

[0183] <6>

[0184] The multilayer ceramic electronic component according to <3>, wherein

[0185] The second internal electrode layer comprises: a second opposing portion opposing the first internal electrode layer; a third lead portion extending from the second opposing portion and led to the first side surface; and a fourth lead portion extending from the second opposing portion and led to the second side surface.

[0186] The width direction length of the stack of the dummy electrode exposed on the first side or the second side is greater than 50% and less than 60% of the width direction length of the stack of the third lead portion of the second internal electrode layer and the fourth lead portion of the second internal electrode layer.

[0187] <7>

[0188] The multilayer ceramic electronic component according to any one of <1> to <6>,

[0189] A center portion in the longitudinal direction of the laminate of the dummy electrode exposed on the first side surface or the second side surface is located within 3% of a center portion in the longitudinal direction of the laminate of the second internal electrode layer exposed on the first side surface or the second side surface.

[0190] <8>

[0191] The multilayer ceramic electronic component according to any one of <1> to <7>,

[0192] In the dummy electrode, a ratio of an area of ​​the void to an area of ​​a region separated by 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less.

[0193] Industrial Applicability

[0194] The present invention relates to a multilayer ceramic electronic component and can be used as a multilayer ceramic electronic component that prevents peeling between ceramic layers.

[0195] Description of Reference Numerals

[0196] 10. Multilayer ceramic capacitors;

[0197] 12 laminate;

[0198] 12a 1st main side;

[0199] 12b 2nd main side;

[0200] 12c 1st side;

[0201] 12d 2nd side;

[0202] 12e 1st end face;

[0203] 12f 2nd end surface;

[0204] 14 Ceramic layer;

[0205] 15a effective layer;

[0206] 15b1 1st outer part;

[0207] 15b2 2nd outer part;

[0208] 16 internal electrode layer;

[0209] 16a first internal electrode layer;

[0210] 16b second internal electrode layer;

[0211] 18a: first opposing portion;

[0212] 18b second opposing portion;

[0213] 20a: first lead-out portion;

[0214] 20b: second lead-out portion;

[0215] 20c 3rd lead-out section;

[0216] 20d 4th lead-out section;

[0217] 22a, 22b side of the stack (W gap);

[0218] 24a, 24b ends of the stack (L gap);

[0219] 30 external electrodes;

[0220] 30a first external electrode;

[0221] 30b second external electrode;

[0222] 30c 3rd external electrode;

[0223] 30d 4th external electrode;

[0224] 32 base electrode layer;

[0225] 32a: a first base electrode layer;

[0226] 32b: a second base electrode layer;

[0227] 32c: the third base electrode layer;

[0228] 32d 4th base electrode layer;

[0229] 34 coating;

[0230] 34a: first coating layer;

[0231] 34b: second coating layer;

[0232] 34c: 3rd coating layer;

[0233] 34d 4th coating layer;

[0234] 40 dummy electrodes;

[0235] 40a: a first dummy electrode;

[0236] 40b: a second dummy electrode;

[0237] 40c: a third dummy electrode;

[0238] 40d 4th dummy electrode;

[0239] 42: exposed portion of the dummy electrode;

[0240] 42a: an exposed portion of the first dummy electrode;

[0241] 42b: an exposed portion of the second dummy electrode;

[0242] 42c: an exposed portion of the third dummy electrode;

[0243] 42d: an exposed portion of a fourth dummy electrode;

[0244] 44: an end region of the dummy electrode;

[0245] 44a an end region of the first dummy electrode;

[0246] 44b an end region of the second dummy electrode;

[0247] 44c: an end region of the third dummy electrode;

[0248] 44d an end region of the fourth dummy electrode;

[0249] 46 gap;

[0250] x stacking direction;

[0251] y width direction;

[0252] z length direction;

[0253] L M The length dimension of the multilayer ceramic capacitor;

[0254] W M The width dimension of the multilayer ceramic capacitor;

[0255] T M The dimensions of a stacked ceramic capacitor in the stacking direction;

[0256] L is the length dimension of the laminate;

[0257] W is the width dimension of the laminate;

[0258] T is the dimension of the stack in the stacking direction;

[0259] F1~F N Determination area;

[0260] M: a central portion in the longitudinal direction of the second internal electrode layer;

[0261] M1: the center portion in the length direction of the first dummy electrode;

[0262] M2: the center portion in the length direction of the second dummy electrode;

[0263] N: a central portion in the width direction of the first internal electrode layer;

[0264] N1: the central portion in the width direction of the third dummy electrode;

[0265] N2: the central portion in the width direction of the fourth dummy electrode;

[0266] t1: thickness of the first internal electrode layer in the stacking direction;

[0267] t2: thickness of the second internal electrode layer in the stacking direction;

[0268] t3: thickness of the first dummy electrode in the stacking direction;

[0269] t4: thickness of the second dummy electrode in the stacking direction;

[0270] t5: thickness of the third dummy electrode in the stacking direction;

[0271] t6: thickness of the fourth dummy electrode in the stacking direction;

[0272] w1: the length of the first dummy electrode in the width direction;

[0273] w2: the length of the second dummy electrode in the width direction;

[0274] w3: the length of the third lead portion in the width direction;

[0275] w4: the length of the fourth lead portion in the width direction;

[0276] l1 is the length of the third dummy electrode in the longitudinal direction;

[0277] l2 The length of the fourth dummy electrode in the longitudinal direction;

[0278] l3: the length of the first lead-out portion in the longitudinal direction;

[0279] l4: Length of the second lead portion in the longitudinal direction.

Claims

1. A laminated ceramic electronic component comprising a laminate and a plurality of external electrodes, the laminate comprising a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the lamination direction and the width direction, wherein: The plurality of internal electrode layers have: a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and a second internal electrode layer which is alternately stacked with the plurality of ceramic layers and is exposed on the first side surface and the second side surface; further comprising a dummy electrode, which is arranged separately from the first internal electrode layer and the second internal electrode layer and is exposed from any one of the first end surface, the second end surface, the first side surface, and the second side surface, The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. In the dummy electrode, a line coverage of a conductive component in a region separated by 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is less than 50%.

2. The multilayer ceramic electronic component according to claim 1, wherein The dummy electrode is exposed on at least one of the first side surface and the second side surface on the ceramic layer on which the first internal electrode layer is arranged.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The dummy electrode is exposed on at least one of the first end surface and the second end surface on the ceramic layer on which the second internal electrode layer is arranged.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein The thickness of the dummy electrode in the stacking direction is smaller than the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

5. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein The thickness of the dummy electrode in the stacking direction is not less than 75% and not more than 95% of the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

6. The multilayer ceramic electronic component according to claim 3, wherein The second internal electrode layer comprises: a second opposing portion opposing the first internal electrode layer; a third lead portion extending from the second opposing portion and led to the first side surface; and a fourth lead portion extending from the second opposing portion and led to the second side surface. The width direction length of the stack of the dummy electrode exposed on the first side or the second side is greater than 50% and less than 60% of the width direction length of the stack of the third lead portion of the second internal electrode layer and the fourth lead portion of the second internal electrode layer.

7. The multilayer ceramic electronic component according to any one of claims 1 to 6, wherein A central portion of the stack in the longitudinal direction of the dummy electrode exposed on the first side surface or the second side surface is located within 3% of a central portion of the stack in the longitudinal direction of the second internal electrode layer exposed on the first side surface or the second side surface.

8. The multilayer ceramic electronic component according to any one of claims 1 to 7, wherein In the dummy electrode, a ratio of an area of ​​the void to an area of ​​a region separated by 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less.

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