Mask and semiconductor structure

Abstract

The invention discloses a mask and a semiconductor structure. The mask comprises a device region and an electrostatic protection region surrounding the device region, a protection pattern for forming an induced anti-static protection ring is arranged in the static protection area, the protection pattern comprises a plurality of shading patterns which are distributed at intervals, and the protection pattern meets one or more of the following conditions: corners of adjacent shading patterns are opposite to each other; or the corner of the shading pattern is opposite to the boundary of the main pattern in the device area. By arranging the shading pattern on the mask plate, charge energy accumulated in the mask plate is released through the corner of the shading pattern, so that discharge of the induced anti-static protection ring occurs on the shading pattern, and the effect of releasing the charge energy accumulated in the mask plate can be achieved; the probability that the charge energy accumulated in the mask destroys the main pattern of the device region is reduced, and the product yield of the semiconductor structure formed by adopting the mask is further improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a mask and a semiconductor structure. Background Art

[0002] Reticle, also known as photomask, photomask, photolithography mask, etc., is a graphic transfer tool or master in the microelectronics manufacturing process. It is a carrier of intellectual property information such as graphic design and process technology.

[0003] Masks are used for mass production in the downstream electronic component manufacturing industry. They are the key to connecting chip design and production, and are one of the determining factors for the precision and quality of downstream products. They are characterized by customization and refinement.

[0004] Currently, the performance of masks still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a mask and a semiconductor structure, which are beneficial to improving the performance of the mask, thereby further improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a mask plate, including a device area, and an electrostatic protection area surrounding the device area; the electrostatic protection area has a protection pattern for forming an induced anti-static protection ring, and the protection pattern includes a plurality of spaced-apart shading patterns, and the protection pattern satisfies one or more of the following situations: the corners of adjacent shading patterns are opposite to each other; or, the corners of the shading pattern are opposite to the boundary of the main pattern in the device area.

[0007] Optionally, the protection pattern further includes a light-transmitting pattern, the light-transmitting pattern is located on a side of the light-shielding pattern, and the light-transmitting pattern is in contact with the light-shielding pattern.

[0008] Optionally, the material of the light-transmitting pattern includes one or both of transparent glass and transparent resin; the material of the light-shielding pattern includes one or more of chromium, silicon, molybdenum silicide and iron oxide.

[0009] Optionally, the shading patterns have the same shape.

[0010] Optionally, the shading pattern has a plurality of corners, and the number of the corners is greater than or equal to 3.

[0011] Optionally, the shape of the shading pattern includes one or both of a triangle and a parallelogram.

[0012] Optionally, the distance between two closest sides of adjacent shading patterns in the vertical direction is 1 nanometer to 5000 nanometers.

[0013] Optionally, when the corners of adjacent shading patterns are opposite to each other, the side length of the shading pattern is 1 micron to 100 microns; when the corner of the shading pattern is opposite to the boundary of the main pattern in the device area, the side length of the shading pattern is 1 micron to 100 microns.

[0014] Optionally, when the corner of the shading pattern is directly opposite to the boundary of the main pattern in the device area, the vertical distance between the shading pattern and the boundary of the main pattern in the device area is 1 micron to 100 microns.

[0015] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed using the mask provided by the aforementioned embodiment, wherein the semiconductor structure includes a device area, and an electrostatic protection area surrounding the device area: the electrostatic protection area has an induced anti-static protection ring surrounding the device area, and the induced anti-static protection ring includes a plurality of spaced-apart graphic layers, and the induced anti-static protection ring satisfies one or more of the following situations: the corners of adjacent graphic layers are opposite to each other; or the corners of the graphic layer are opposite to the boundary of the main graphic in the device area.

[0016] Optionally, the induced anti-static protection ring includes an opening surrounding the device area, and the graphic layer is arranged in the opening.

[0017] Optionally, the graphic layers have the same shape.

[0018] Optionally, the graphic layer has a plurality of corners, and the number of the corners is greater than or equal to 3.

[0019] Optionally, the shape of the graphic layer includes one or both of a triangle and a parallelogram.

[0020] Optionally, the distance between two closest edges of adjacent graphic layers in the vertical direction is 1 nanometer to 5000 nanometers.

[0021] Optionally, when the corners of adjacent layers are opposite to each other, the side length of the graphic layer is 1 micron to 100 microns; when the corner of the graphic layer is opposite to the boundary of the main graphic in the device area, the side length of the graphic layer is 1 micron to 100 microns.

[0022] Optionally, when a corner of the graphic layer is directly opposite to a boundary of the main graphic in the device area, a vertical distance between the graphic layer and the boundary of the main graphic in the device area is 1 micron to 100 microns.

[0023] Optionally, the material of the graphic layer includes photoresist.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] An embodiment of the present invention provides a mask, which includes a device area and an electrostatic protection area surrounding the device area. The electrostatic protection area has a protection pattern for forming an induced anti-static protection ring, and the protection pattern includes a plurality of spaced shading patterns, and the protection pattern satisfies one or more of the following situations: the corners of adjacent shading patterns are opposite to each other; or the corners of the shading pattern are opposite to the boundary of the main pattern in the device area. In this embodiment, by setting the corners of adjacent shading patterns to be opposite to each other, or setting the corners of the shading pattern to be opposite to the boundary of the main pattern in the device area, the charge energy accumulated in the mask can be released through the corners of the shading pattern, so that the discharge of the induced anti-static protection ring occurs on its shading pattern, which can play a role in releasing the charge energy accumulated in the mask, reducing the probability that the charge energy accumulated in the mask will damage the main pattern of the device area, thereby improving the product yield of the semiconductor structure formed using the mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 to Figure 2 is a schematic structural diagram corresponding to an embodiment of a mask of the present invention;

[0027] Figure 3 to Figure 4 It is a schematic diagram of the corresponding structure in an embodiment of a semiconductor junction of the present invention. DETAILED DESCRIPTION

[0028] At present, during the production, transportation and storage of the mask, the environmental voltage changes too quickly. For example, when the mask moves in an electric field, it is easy to generate electricity through friction, which makes the main pattern of the device area of ​​the mask charged. When the charge accumulates to saturation, the mask will produce discharge. The discharge behavior of the mask will damage the main pattern of the device area, causing the main pattern of the device area to change, thereby reducing the product yield of the semiconductor structure formed using the mask.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a mask plate, including a device area, and an electrostatic protection area surrounding the device area; the electrostatic protection area has a protection pattern for forming an induced anti-static protection ring, and the protection pattern includes a plurality of spaced-apart shading patterns, and the protection pattern satisfies one or more of the following situations: the corners of adjacent shading patterns are opposite to each other; or, the corners of the shading pattern are opposite to the boundary of the main pattern in the device area.

[0030] This embodiment sets the corners of adjacent shading patterns to be opposite to each other, or sets the corners of the shading patterns to be opposite to the boundaries of the main patterns in the device area, so that the charge energy accumulated in the mask can be released through the corners of the shading patterns, so that the discharge of the induced anti-static protection ring occurs on its shading pattern, which can release the charge energy accumulated in the mask, reduce the probability of the charge energy accumulated in the mask to damage the main pattern of the device area, and thus improve the product yield of the semiconductor structure formed using the mask.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 to Figure 2 is a schematic diagram of the structure corresponding to an embodiment of a mask of the present invention, wherein: Figure 1 This is a top view of the mask. Figure 2 yes Figure 1 A partial enlarged view of the protected pattern in the middle.

[0033] The mask plate 100D includes a device area 100A and an electrostatic protection area 100B surrounding the device area 100A; the electrostatic protection area 100B has a protection pattern 100C for forming an induced anti-static protection ring, and the protection pattern 100C includes a plurality of spaced-apart shading patterns 102, and the protection pattern 100C satisfies one or more of the following situations: the corners of adjacent shading patterns 102 are opposite to each other; or, the corners of the shading pattern 102 are opposite to the boundary of the main pattern in the device area 100A.

[0034] It should be noted that, by setting the corners of the adjacent shading patterns 102 to be opposite to each other, or setting the corners of the shading patterns 102 to be opposite to the boundaries of the main patterns in the device area 100A, the charge energy accumulated in the mask 100D can be released through the corners of the shading patterns 102, so that the discharge of the induced anti-static protection ring occurs on its shading pattern 102, which can release the charge energy accumulated in the mask 100D, reduce the probability of the charge energy accumulated in the mask 100D damaging the main pattern of the device area 100A, and thus improve the product yield of the semiconductor structure formed using the mask 100D.

[0035] A mask is a structure that is used to make various functional patterns on a film, plastic or glass substrate and accurately position them for selective exposure of a photoresist coating.

[0036] The mask plate 100D is widely used. It is needed in fields involving photolithography processes, such as IC (Integrated Circuit), FPD (Flat Panel Display), PCB (Printed Circuit Boards), MEMS (Micro Electro Mechanical Systems), etc.

[0037] In this embodiment, the mask 100D includes a device region 100A and an electrostatic protection region 100B surrounding the device region 100A.

[0038] Specifically, the device region 100A is used as a region for setting a main pattern, and the main pattern is used to form a functional device structure in a semiconductor structure, such as an interconnection structure, a gate structure, a metal line and other functional device structures.

[0039] The electrostatic protection area 100B is used as an area for setting a protection pattern 100C, and the protection pattern 100C is used to form an induced anti-static protection ring, that is, the protection pattern 100C can induce the release of the charge energy accumulated in the mask plate 100D, thereby reducing the probability that the charge energy accumulated in the mask plate 100D will damage the main pattern of the device area 100A, thereby improving the product yield of the semiconductor structure formed using the mask plate 100D.

[0040] In this embodiment, the electrostatic protection area 100B has a protection pattern 100C for forming an induced anti-static protection ring, and the protection pattern 100C includes a plurality of spaced-apart shading patterns 102, and the protection pattern 100C satisfies one or more of the following situations: the corners of adjacent shading patterns 102 are opposite to each other; or, the corners of the shading pattern 102 are opposite to the boundary of the main pattern in the device area 100A.

[0041] As an example, the drawings show that the corners of adjacent light-shielding patterns 102 are opposite to each other, and the corner of the light-shielding pattern 102 is opposite to the boundary of the main pattern in the device region 100A.

[0042] It should be noted that, in this embodiment, by setting the corners of the adjacent shading patterns 102 to be opposite to each other, and setting the corners of the shading patterns 102 to be opposite to the boundaries of the main patterns in the device area 100A, the charge energy accumulated in the mask plate 100D can be released through the corners of the shading patterns 102, so that the discharge of the induced anti-static protection ring occurs on its shading pattern 102, which can release the charge energy accumulated in the mask plate 100D, reduce the probability that the charge energy accumulated in the mask plate 100D will damage the device area 100A pattern, and thus improve the product yield of the semiconductor structure formed using the mask plate 100D.

[0043] The light shielding pattern 102 is used to form a pattern layer in the semiconductor structure in the subsequent process of forming the semiconductor structure using the mask plate 100D.

[0044] In this embodiment, the shapes of the light shielding patterns 102 are the same.

[0045] Specifically, the shapes of the shading patterns 102 are the same. In the subsequent process of forming a semiconductor structure using the mask plate 100D, the exposure difficulty of forming a pattern layer in the semiconductor structure is reduced, the accuracy of pattern transfer is improved, and the product yield of the semiconductor structure is improved.

[0046] In this embodiment, the light shielding pattern 102 has a plurality of corners, and the number of the corners is greater than or equal to three.

[0047] It should be noted that the purpose of setting the corners is to promote the occurrence of discharge at the corners. Multiple corners are set so that when static electricity accumulates a lot, the static electricity in the mask 100D can be completely released through discharge at multiple corners.

[0048] In this embodiment, the shape of the light shielding pattern 102 includes one or both of a triangle and a parallelogram.

[0049] It should be noted that both the triangle and the parallelogram have corners. Accordingly, in the process of setting the protection pattern 100C in the electrostatic protection area 100B, the corners of the adjacent shading pattern 102 can be set to be opposite to each other, or the corners of the shading pattern 102 can be set to be opposite to the boundary of the main pattern in the device area 100A, so that the charge energy accumulated in the mask 100D can be released through the corners of the shading pattern 102.

[0050] As an example, the shape of the shading pattern 102 shown in the drawings is a type of parallelogram, that is, a rectangle.

[0051] Specifically, by selecting a rectangle as the shading pattern 102, compared with selecting a triangle or other parallelogram, the process difficulty of pattern transfer is the lowest and the accuracy of pattern transfer is the highest in the process of forming a semiconductor structure by using the mask 100D for exposure and development. While reducing the process difficulty of the semiconductor structure, it can also improve the product yield of the semiconductor structure.

[0052] It should be noted that the distance between the two closest sides of the adjacent shading patterns 102 in the vertical direction should not be too large or too small. If the distance between the two closest sides of the adjacent shading patterns 102 in the vertical direction is too large, when the size of the electrostatic protection zone 100B of the mask 100D is constant, it is easy to cause the number of shading patterns 102 set in the electrostatic protection zone 100B to become smaller, and accordingly, the number of corners of adjacent shading patterns 102 that face each other becomes smaller, or the number of corners of the shading patterns 102 that face the boundary of the main pattern in the device area 100A becomes smaller, so that the effect of releasing the charge energy accumulated in the mask 100D through the corners of the shading pattern 102 becomes worse, and the probability of the charge energy accumulated in the mask 100D damaging the pattern in the device area 100A through the electrostatic protection zone 100B is increased, thereby reducing the product yield of the semiconductor structure formed by using the mask 100D. If the distance between the two closest sides of adjacent light shielding patterns 102 in the vertical direction is too small, in the subsequent process of using the mask 100D to expose and develop to form a semiconductor structure, the process difficulty of forming a pattern layer in the semiconductor structure is increased, making the pattern transfer accuracy worse, thereby affecting the product yield of the semiconductor structure. For this reason, in this embodiment, the distance D1 between the two closest sides of the adjacent light shielding patterns 102 in the vertical direction is 1 nanometer to 5000 nanometers.

[0053] It should also be noted that when the corners of adjacent shading patterns 102 face each other, the side length of the shading pattern 102 should not be too small or too large. If the side length of the shading pattern 102 is too small, it is easy to cause the charge energy accumulated in the mask 100D to be released through the corners of the shading pattern 102 to be released poorly; if the side length of the shading pattern 102 is too large, it is easy to cause the available area of ​​the pattern in the device area 100A to be reduced, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, when the corners of adjacent shading patterns 102 face each other, the side length D2 of the shading pattern 102 is 1 micron to 100 microns.

[0054] As an example, when the corner of the shading pattern 102 is directly opposite to the boundary of the main pattern in the device area 100A, the side length of the shading pattern 102 should not be too small or too large. If the side length of the shading pattern 102 is too large, when the size of the electrostatic protection area 100B of the mask 100D is constant, the probability of the shading pattern 102 contacting the boundary of the main pattern in the device area 100A is increased, so that the corner of the shading pattern 102 cannot be directly opposite to the boundary of the main pattern in the device area 100A, which means that the charge energy accumulated in the mask 100D cannot be released through the corner of the shading pattern 102, which increases the probability that the charge energy accumulated in the mask 100D causes damage to the device area 100A pattern, thereby reducing the product yield of the semiconductor structure formed using the mask 100D. If the side length of the light shielding pattern 102 is too small, it is easy to cause the charge energy accumulated in the mask 100D to be released through the corner of the light shielding pattern 102. Therefore, in this embodiment, when the corner of the light shielding pattern 102 is directly opposite to the boundary of the main pattern in the device area 100A, the side length D3 of the light shielding pattern 102 is 1 micron to 100 microns.

[0055] It should be noted that when the corner of the shading pattern 102 is directly opposite to the boundary of the main pattern in the device area 100A, the vertical distance between the shading pattern 102 and the boundary of the main pattern in the device area 100A should not be too small or too large. If the vertical distance between the shading pattern 102 and the boundary of the main pattern in the device area 100A is too large, it is easy to cause the effect of the charge energy accumulated in the mask 100D being released through the corner of the shading pattern 102 to be poor; if the vertical distance between the shading pattern 102 and the boundary of the main pattern in the device area 100A is too small, that is, the distance between the corner of the shading pattern 102 and the boundary of the main pattern in the device area 100A is too close, accordingly, during the process of the charge energy accumulated in the mask 100D being released through the corner of the shading pattern 102, the main pattern in the device area 100A will still be damaged, thereby reducing the product yield of the semiconductor structure formed using the mask 100D. To this end, in this embodiment, when the corner of the shading pattern 102 is opposite to the boundary of the main pattern in the device area 100A, the vertical distance D4 between the shading pattern 102 and the boundary of the main pattern in the device area 100A is 1 micron to 100 microns.

[0056] In this embodiment, the material of the light shielding pattern 102 includes one or more of chromium, silicon, molybdenum silicide and iron oxide.

[0057] Specifically, chromium, silicon, molybdenum silicide and iron oxide are all commonly used materials for the mask 100D light-shielding pattern 102, and have low process costs, good coating uniformity, high etching accuracy and other characteristics.

[0058] In this embodiment, the protection pattern 100C further includes a light-transmitting pattern 106 . The light-transmitting pattern 106 is located on the side of the light-shielding pattern 102 , and the transparent pattern is in contact with the light-shielding pattern 102 .

[0059] Specifically, in a subsequent process of forming a semiconductor structure using the mask plate 100D, as an example, the mask plate 100D is used to form a mask layer, and the light-transmitting pattern 106 is used as a mask opening for forming the mask layer.

[0060] The light-transmitting pattern 106 is located at the side of the light-shielding pattern 102 , and the transparent pattern is in contact with the light-shielding pattern 102 .

[0061] It should be noted that the material of the shading pattern 102 serves as a conductor and the material of the light-transmitting pattern 106 serves as an insulator. When the two conductors carry different charges and there is an insulator between the two conductors, as the electrostatic charge of the mask 100D accumulates to a certain value, static electricity is likely to occur, causing the charge energy accumulated in the mask 100D to be released through the corners of the shading pattern 102.

[0062] In this embodiment, the material of the light-transmitting pattern 106 includes one or both of transparent glass and transparent resin.

[0063] It should be noted that transparent glass and transparent resin are both commonly used materials for mask 100D, and have the characteristics of low process cost. At the same time, transparent glass and transparent resin have high optical transmittance and low thermal expansion coefficient, which can improve the accuracy of mask 100D during graphic transmission.

[0064] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by using the mask provided by the above embodiment, wherein: Figure 3 to Figure 4 is a schematic diagram of the structure corresponding to the semiconductor junction in the first embodiment of the present invention, Figure 3 is a top view of the semiconductor structure. Figure 4 yes Figure 3 A partial enlarged view of the induced anti-static protection ring in the middle part.

[0065] The semiconductor structure includes a device area 200A and an electrostatic protection area 200B surrounding the device area 200A; the electrostatic protection area 200B has an induced anti-static protection ring 200C surrounding the device area 200A, and the induced anti-static protection ring 200C includes a plurality of spaced graphic layers 202, and the induced anti-static protection ring 200C satisfies one or more of the following situations: the corners of adjacent graphic layers 202 are opposite to each other; or the corners of the graphic layer 202 are opposite to the boundary of the main graphic in the device area 200A.

[0066] It should be noted that the graphic layer 202 is formed by using the shading pattern in the mask. By setting the corners of the adjacent shading patterns in the mask to be opposite to each other, or setting the corners of the shading patterns to be opposite to the boundaries of the main patterns in the device area 200A, the charge energy accumulated in the mask can be released through the corners of the shading patterns, so that the discharge of the induced anti-static protection ring 200C occurs on its shading pattern, which can release the charge energy accumulated in the mask, reducing the probability that the charge energy accumulated in the mask will damage the main pattern of the device area 200A. Accordingly, in the process of forming a semiconductor structure using the mask, the accuracy of the pattern transfer is increased, and the product yield of the semiconductor structure formed using the mask is effectively improved.

[0067] Specifically, the device region 200A is used as a region for setting functional devices, and the functional devices are used to form functional device structures in a semiconductor structure, such as interconnect structures, gate structures, metal lines and other functional device structures.

[0068] The electrostatic protection zone 200B is used as an area for setting an induced anti-static protection ring 200C, that is, the induced anti-static protection ring 200C can induce the release of charge energy accumulated in the mask, thereby reducing the probability that the charge energy accumulated in the mask will damage the main pattern of the device area 200A, thereby improving the product yield of the semiconductor structure formed using the mask.

[0069] In this embodiment, the induced anti-static protection ring 200C includes a plurality of spaced-apart graphic layers 202, and the induced anti-static protection ring 200C satisfies one or more of the following situations: the corners of adjacent graphic layers 202 are opposite to each other; or, the corners of the graphic layer 202 are opposite to the boundary of the main graphic in the device area 200A.

[0070] As an example, the drawings show that the corners of adjacent light shielding layers are opposite to each other, and the corners of the light shielding layers are opposite to the boundary of the main pattern in the device area 200A.

[0071] In this embodiment, the shapes of the pattern layers 202 are the same.

[0072] Specifically, the graphic layer 202 is formed using the shading pattern in the mask. Since the shape of the shading pattern is the same, in the subsequent process of using the mask to form the semiconductor structure, the exposure difficulty of forming the graphic layer 202 in the semiconductor structure is reduced, the accuracy of the graphic transfer is improved, and the product yield of the semiconductor structure is improved.

[0073] In this embodiment, the graphic layer 202 has a plurality of corners, and the number of the corners is greater than or equal to three.

[0074] It should be noted that the purpose of setting the corners is to promote the occurrence of discharge at the corners. Multiple corners are set so that when static electricity accumulates a lot, the static electricity in the mask 100D can be completely released through discharge at multiple corners.

[0075] In this embodiment, the shape of the graphic layer 202 includes one or both of a triangle and a parallelogram.

[0076] It should be noted that both the triangle and the parallelogram are graphics with corners. Accordingly, in the process of setting the graphic layer 202 in the electrostatic protection area 200B, the corners of the adjacent graphic layers 202 can be set to be opposite to each other, or the corners of the graphic layer 202 and the boundary of the main graphic in the device area 200A can be set to be opposite to each other, so that the charge energy accumulated in the semiconductor structure can be released through the corners of the graphic layer 202.

[0077] As an example, the shape of the graphic layer 202 shown in the drawings is a type of parallelogram, ie, a rectangle.

[0078] Specifically, by selecting a rectangle as the shape of the graphic layer 202, compared to selecting a triangle or other parallelogram, the process difficulty of graphic transfer is the lowest and the accuracy of graphic transfer is the highest during the process of using a mask to expose and develop to form a semiconductor structure (such as the graphic layer 202). While reducing the difficulty of the process of the semiconductor structure, it can also improve the product yield of the semiconductor structure.

[0079] It should be noted that the distance between the two closest sides of the adjacent graphic layers 202 in the vertical direction should not be too large or too small. If the distance between the two closest sides of the adjacent graphic layers 202 in the vertical direction is too large, when the size of the electrostatic protection area 200B of the mask is constant, it is easy to cause the number of graphic layers 202 set in the electrostatic protection area 200B to become smaller, and accordingly, it also causes the number of corners of adjacent graphic layers 202 that are directly opposite to each other to become smaller, or the number of corners of the graphic layers 202 that are directly opposite to the boundary of the main graphic in the device area 200A to become smaller, thereby making the effect of the charge energy accumulated in the semiconductor structure being released through the corners of the graphic layer 202 worse, increasing the probability that the charge energy accumulated in the semiconductor structure will damage the graphic in the device area 200A through the electrostatic protection area 200B, and thus reducing the product yield of the semiconductor structure. If the distance between the two closest edges of adjacent pattern layers 202 in the vertical direction is too small, the probability of the pattern layer 202 contacting the boundary of the main pattern of the device area 200A increases, thereby affecting the product yield of the semiconductor structure. To this end, in this embodiment, the distance D1 between the two closest edges of the adjacent pattern layers 202 in the vertical direction is 1 nanometer to 5000 nanometers.

[0080] It should also be noted that when the corners of adjacent layers are facing each other, the side length of the graphic layer 202 should not be too small or too large. If the side length of the graphic layer 202 is too small, it is easy to cause the charge energy accumulated in the mask 100D to be released through the corners of the shading pattern 102 to be poor; if the side length of the graphic layer 202 is too large, it is easy to cause the available area of ​​the pattern in the device area 100A to be reduced, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, when the corners of adjacent shading patterns are facing each other, the side length D2 of the shading pattern is 1 micron to 100 microns.

[0081] As an example, when the corner of the graphic layer 202 is directly opposite to the boundary of the main pattern in the device area 200A, the side length of the graphic layer 202 should not be too small or too large. If the side length of the graphic layer 202 is too large, when the size of the electrostatic protection area 200B is constant, the probability of the graphic layer 202 contacting the boundary of the main pattern in the device area 200A is increased, so that the corner of the graphic layer 202 cannot be directly opposite to the boundary of the main pattern in the device area 200A, which means that the charge energy accumulated in the semiconductor structure cannot be released through the corner of the graphic layer 202, increasing the probability that the charge energy accumulated in the semiconductor structure damages the device area 200A pattern, thereby reducing the product yield of the semiconductor structure formed by the mask. If the side length of the graphic layer 202 is too small, it is easy to cause the effect of the charge energy accumulated in the mask 100D being released through the corner of the light shielding pattern 102 to be poor. To this end, in this embodiment, when the corner of the pattern layer 202 is directly opposite to the boundary of the main pattern in the device area 200A, the side length D3 of the pattern layer 202 is 1 micrometer to 100 micrometers.

[0082] It should be noted that when the corner of the graphic layer 202 is directly opposite to the boundary of the main graphic in the device area 200A, the vertical distance between the graphic layer 202 and the boundary of the main graphic in the device area 200A should not be too small or too large. If the vertical distance between the graphic layer 202 and the boundary of the main graphic in the device area 200A is too large, it is easy to cause the effect of the charge energy accumulated in the mask 100D being released through the corner of the light shielding graphic 102 to be poor; if the vertical distance between the graphic layer 202 and the boundary of the main graphic in the device area 200A is too small, that is, the distance between the corner of the graphic layer 202 and the boundary of the main graphic in the device area 200A is too close, accordingly, during the process of the charge energy accumulated in the semiconductor structure being released through the corner of the graphic layer 202, the main graphic in the device area 200A will still be damaged, thereby reducing the product yield of the semiconductor structure. To this end, in this embodiment, when the corner of the pattern layer 202 is directly opposite to the boundary of the main pattern in the device area 200A, the vertical distance D4 between the pattern layer 202 and the boundary of the main pattern in the device area 200A is 1 micron to 100 microns.

[0083] In this embodiment, the material of the pattern layer 202 includes photoresist.

[0084] The pattern layer 202 is formed by mask exposure and development, and photoresist is a common object to be exposed and developed by the mask.

[0085] In this embodiment, the induced anti-static protection ring 200C includes an opening 206 surrounding an electrostatic protection area 200B of the device area 200A, and the pattern layer 202 is disposed in the opening 206 .

[0086] In the process of forming a semiconductor structure using a mask, as an example, the mask is used to form a mask layer, and the light-transmitting pattern in the mask is used as a mask opening for forming the mask layer.

[0087] As an example, the opening 206 is a mask opening.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A mask, characterized in that: including a device area and an electrostatic protection area surrounding the device area; The electrostatic protection zone has a protection pattern for forming an induced anti-static protection ring, and the protection pattern includes a plurality of spaced-apart shading patterns, and the protection pattern satisfies one or more of the following situations: the corners of adjacent shading patterns are opposite to each other; or the corners of the shading pattern are opposite to the boundary of the main pattern in the device area.

2. The mask according to claim 1, characterized in that: The protection pattern further includes a light-transmitting pattern, the light-transmitting pattern is located at the side of the light-shielding pattern, and the light-transmitting pattern is in contact with the light-shielding pattern.

3. The mask according to claim 2, characterized in that: The material of the light-transmitting pattern includes one or both of transparent glass and transparent resin; The material of the light-shielding pattern includes one or more of chromium, silicon, molybdenum silicide and iron oxide.

4. The mask according to claim 1, characterized in that: The shapes of the shading patterns are the same.

5. The mask according to claim 1, characterized in that: The shading pattern has a plurality of corners, and the number of the corners is greater than or equal to 3.

6. The mask according to claim 1, characterized in that: The shape of the shading pattern includes one or both of a triangle and a parallelogram.

7. The mask according to claim 1, characterized in that: The distance between the two closest sides of the adjacent shading patterns in the vertical direction is 1 nanometer to 5000 nanometers.

8. The mask according to claim 1, characterized in that: When the corners of adjacent shading patterns are opposite to each other, the side length of the shading patterns is 1 micrometer to 100 micrometers; When the corner of the light-shielding pattern is directly opposite to the boundary of the main pattern in the device area, the side length of the light-shielding pattern is 1 micron to 100 microns.

9. The mask according to claim 1, characterized in that: When the corner of the light-shielding pattern is directly opposite to the boundary of the main pattern in the device area, the vertical distance between the light-shielding pattern and the boundary of the main pattern in the device area is 1 micrometer to 100 micrometers.

10. A semiconductor structure formed using the mask according to any one of claims 1 to 9, characterized in that: The semiconductor structure includes a device region and an electrostatic protection region surrounding the device region: The electrostatic protection zone has an induced anti-static protection ring surrounding the device zone, and the induced anti-static protection ring includes a plurality of spaced-apart graphic layers, and the induced anti-static protection ring satisfies one or more of the following situations: the corners of adjacent graphic layers are directly opposite to each other; or the corners of the graphic layer are directly opposite to the boundary of the main graphic in the device zone.

11. The semiconductor structure according to claim 10, characterized in that The induced anti-static protection ring comprises an opening surrounding the device area, and the pattern layer is arranged in the opening.

12. The semiconductor structure according to claim 10, wherein: The graphic layers have the same shape.

13. The semiconductor structure according to claim 10, wherein: The graphic layer has a plurality of corners, and the number of the corners is greater than or equal to 3.

14. The semiconductor structure according to claim 10, wherein: The shape of the graphic layer includes one or both of a triangle and a parallelogram.

15. The semiconductor structure according to claim 10, wherein: The distance between two closest sides of adjacent graphic layers in the vertical direction is 1 nanometer to 5000 nanometers.

16. The semiconductor structure according to claim 10, wherein: When the corners of adjacent layers are facing each other, the side length of the graphic layer is 1 micron to 100 microns; When the corner of the graphic layer is directly opposite to the boundary of the main graphic in the device area, the side length of the graphic layer is 1 micron to 100 microns.

17. The semiconductor structure according to claim 10, wherein: When the corner of the pattern layer is directly opposite to the boundary of the main pattern in the device area, the vertical distance between the pattern layer and the boundary of the main pattern in the device area is 1 micron to 100 microns.

18. The semiconductor structure according to claim 10, wherein: The material of the pattern layer includes photoresist.

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