Method for reducing tungsten gate defects

Abstract

The invention provides a method for reducing tungsten gate defects, which comprises the following steps of: 1, providing a substrate, forming a plurality of dummy gate structures on the substrate, and ensuring that the height of the dummy gate structure with large line width is greater than that of the dummy gate structure with small line width; 2, forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is formed by a material formed by an HARP process and a material formed by a plasma enhanced deposition process, and the materials are stacked from bottom to top; step 3, grinding the interlayer dielectric layer until the top of the dummy gate structure is exposed; 4, removing the gate layer in the dummy gate structure, and forming a tungsten metal layer on the substrate; and step 5, grinding the tungsten metal layer to form a tungsten gate. Tungsten residues caused by dish-shaped defects on the surface of the interlayer dielectric layer are avoided, and meanwhile, the reduction of the height of the tungsten grid electrode caused by over-grinding is inhibited.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for reducing tungsten gate defects. Background Art

[0002] As the device feature size decreases, in order to achieve better aspect ratio filling, the HARP process is used to form an interlayer dielectric layer on the substrate. Since the material is not plasma bombarded during the HARP process, the density of the interlayer dielectric layer formed is poor. The subsequent grinding of the interlayer dielectric layer and the removal of the dummy gate are likely to damage the interlayer dielectric layer, thereby forming a dishing defect. When tungsten metal is filled in the groove left after the dummy gate is removed, tungsten residue will appear at the location of the dishing defect (such as Figure 1 (as shown in (a)).

[0003] Another form of tungsten gate defect is that when grinding tungsten metal in the area where large-size gate devices (such as LC devices) are located, the grinding rate of large-size gates is faster than that of small-size gates, which makes it easy to over-grind (such as Figure 1 (b) shows that the height of the tungsten gate decreases. To eliminate the tungsten residue, the grinding time needs to be increased, which is prone to over-grinding; if the grinding time is reduced, the tungsten residue cannot be effectively removed. The tungsten residue and the reduction of the tungsten gate height caused by over-grinding will both lead to a decrease in device performance. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for reducing tungsten gate defects, so as to solve the problem of device performance degradation caused by tungsten gate defects in the prior art.

[0005] To achieve the above objectives and other related objectives, the present application provides a method for reducing tungsten gate defects, comprising:

[0006] Step 1, providing a substrate, and forming a plurality of dummy gate structures on the substrate, wherein the height of the dummy gate structure with a large line width is greater than the height of the dummy gate structure with a small line width;

[0007] Step 2, forming an interlayer dielectric layer composed of a material formed by a HARP process and a material formed by a plasma enhanced deposition process stacked from bottom to top on the substrate;

[0008] Step 3, grinding the interlayer dielectric layer until the top of the dummy gate structure is exposed;

[0009] Step 4, after removing the gate layer in the dummy gate structure, a tungsten metal layer is formed on the substrate;

[0010] Step 5: grinding the tungsten metal layer to form a tungsten gate.

[0011] Preferably, the thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a large line width is located is greater than the thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a small line width is located.

[0012] Preferably, the thickness of the material layer formed by the HARP process is greater than the thickness of the material layer formed by the plasma enhanced deposition process.

[0013] Preferably, the grinding in step three and step five is chemical mechanical grinding.

[0014] Preferably, in step four, a dry etching process is used to remove the gate layer in the dummy gate structure.

[0015] Preferably, the gate layer in the dummy gate structure includes an interface layer and a gate dielectric layer stacked from bottom to top.

[0016] Preferably, the material of the interface layer includes titanium nitride.

[0017] Preferably, the material of the gate dielectric layer is a high dielectric constant material.

[0018] Preferably, the gate dielectric layer is a stacked structure formed by stacking silicon oxide or silicon oxynitride and a high dielectric constant material from bottom to top.

[0019] Preferably, the material of the gate layer is amorphous silicon or polycrystalline silicon.

[0020] As described above, the method for reducing tungsten gate defects provided by the present application has the following beneficial effects: the interlayer dielectric layer is composed of a material formed by a HARP process and a material formed by a plasma enhanced deposition process stacked from bottom to top, thereby avoiding tungsten residues caused by dish-shaped defects on the surface of the interlayer dielectric layer; at the same time, the pseudo gate height of the large-scale line width gate device is increased and the thickness of the material layer formed by the plasma enhanced deposition process in the interlayer dielectric layer located in the substrate area where the large-scale line width gate device is located is larger, thereby suppressing the decrease in the tungsten gate height caused by over-grinding. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 Electron photo showing a defect in a tungsten gate.

[0023] Figure 2 A flow chart showing a method for reducing tungsten gate defects provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] See also Figure 2 , which shows a flow chart of a method for reducing tungsten gate defects provided in an embodiment of the present application.

[0030] like Figure 2 As shown, the method for reducing tungsten gate defects includes the following steps:

[0031] Step 1, providing a substrate, and forming a plurality of dummy gate structures on the substrate, wherein the height of the dummy gate structure with a large line width is greater than the height of the dummy gate structure with a small line width;

[0032] Step 2, forming an interlayer dielectric layer composed of a material formed by a HARP process and a material formed by a plasma enhanced deposition process stacked from bottom to top on the substrate;

[0033] Step 3, grinding the interlayer dielectric layer until the top of the dummy gate structure is exposed;

[0034] Step 4, after removing the gate layer in the dummy gate structure, a tungsten metal layer is formed on the substrate;

[0035] Step 5: grinding the tungsten metal layer to form a tungsten gate.

[0036] In step 1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.

[0037] As an example, a plurality of isolation structures are formed in the substrate, and the dummy gate structures are distributed in different substrate regions separated by the isolation structures.

[0038] The isolation structure may be composed of any insulating material such as silicon dioxide (SiO2), or a "high-k" dielectric having a high dielectric constant, which may be greater than 3.9, for example. In some cases, the isolation structure may be composed of an oxide material. Examples of materials suitable for forming the isolation structure may include silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials now known or later developed with similar properties.

[0039] Exemplarily, the isolation structure is formed by a shallow trench isolation (STI) process, where the shallow trench isolation process includes but is not limited to shallow trench etching, oxide filling, and oxide planarization.

[0040] Shallow trench etching includes but is not limited to isolation oxide layer, nitride precipitation, shallow trench isolation using mask, and STI shallow trench etching. STI oxide filling includes but is not limited to trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling or PVD (physical vapor deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by a variety of methods. The planarization of the silicon wafer can be achieved by filling the gap with SOG (spin-on-glass). SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, SOG is baked to evaporate the solvent and leave silicon dioxide in the gap. The entire surface can also be reversed to reduce the thickness of the entire silicon wafer. The planarization process can also be effectively performed by CMP process (also known as chemical mechanical polishing process), including but not limited to polishing the trench oxide (chemical mechanical polishing can be used) and nitride removal.

[0041] As an example, the dummy gate structure includes an interface layer, a gate dielectric layer and a gate layer stacked from bottom to top.

[0042] Exemplarily, the material of the interface layer includes titanium nitride (TiN); the material of the gate dielectric layer is a high dielectric constant (high-k) material, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), hafnium zirconate (HfZrOx), etc. The gate dielectric layer can also be a stacked structure composed of silicon oxide (or silicon oxynitride) and high dielectric constant (high-K) materials stacked from bottom to top; the material of the gate layer is amorphous silicon or polycrystalline silicon.

[0043] In a specific embodiment, the steps of forming a pseudo gate structure may include: first using a suitable deposition process to sequentially form an interface layer and a gate dielectric layer on a substrate; then depositing a gate layer on the gate dielectric layer; spin coating photoresist on the gate layer, and then patterning the photoresist using a mask to form a patterned photoresist layer; then using the patterned photoresist layer to sequentially etch the gate layer, the gate dielectric layer and the interface layer, and removing the patterned photoresist layer after etching.

[0044] Among the plurality of dummy gate structures formed, the height of the dummy gate structure having a large line width is greater than the height of the dummy gate structure having a small line width.

[0045] In step 2, a HARP process is first performed and then a plasma enhanced deposition process is performed, wherein the thickness of the material layer formed by the HARP process is greater than the thickness of the material layer formed by the plasma enhanced deposition process.

[0046] Preferably, the thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a large line width is located is greater than the thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a small line width is located.

[0047] In step three, as an example, the polishing performed is chemical mechanical polishing.

[0048] In step 4, as an example, a dry etching process is used to remove the gate layer in the dummy gate structure.

[0049] Exemplarily, a tungsten metal layer is formed on the substrate by physical vapor deposition or atomic layer deposition, and the tungsten metal layer fills the groove left after the gate layer in the dummy gate structure is removed.

[0050] Since the upper portion of the interlayer dielectric layer is a material layer formed by a plasma enhanced deposition process, the grinding performed in step three and the dry etching performed in step four will not cause damage to the interlayer dielectric layer (eg, formation of dish-shaped defects).

[0051] In step five, as an example, the polishing performed is chemical mechanical polishing.

[0052] Since there are no dish-shaped defects on the surface of the interlayer dielectric layer, the grinding of tungsten metal will not form tungsten residue; since the height of the pseudo gate structure with a large line width is higher and the thickness of the material layer formed by the plasma enhanced deposition process on the substrate area where it is located is thicker, sufficient space can be reserved for over-grinding, thereby avoiding the decrease in the height of the tungsten gate after grinding.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] In summary, the method for reducing tungsten gate defects provided by the present application is that the interlayer dielectric layer is composed of materials formed by the HARP process and materials formed by the plasma enhanced deposition process stacked from bottom to top, so as to avoid tungsten residues caused by dish-shaped defects on the surface of the interlayer dielectric layer; at the same time, the pseudo gate height of the large-scale line width gate device is increased, and the thickness of the material layer formed by the plasma enhanced deposition process in the interlayer dielectric layer located in the substrate area where the large-scale line width gate device is located is larger, so as to suppress the decrease of the tungsten gate height caused by over-grinding. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for reducing tungsten gate defects, characterized in that: The method comprises: Step 1, providing a substrate, and forming a plurality of dummy gate structures on the substrate, wherein the height of the dummy gate structure with a large line width is greater than the height of the dummy gate structure with a small line width; Step 2, forming an interlayer dielectric layer composed of a material formed by a HARP process and a material formed by a plasma enhanced deposition process stacked from bottom to top on the substrate; Step three, grinding the interlayer dielectric layer until the top of the dummy gate structure is exposed; Step 4, after removing the gate layer in the dummy gate structure, forming a tungsten metal layer on the substrate; Step five: grinding the tungsten metal layer to form a tungsten gate.

2. The method according to claim 1, characterized in that The thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a large line width is located is greater than the thickness of the material layer formed by the plasma enhanced deposition process on the substrate region where the dummy gate structure with a small line width is located.

3. The method according to claim 1, characterized in that The thickness of the material layer formed by the HARP process is greater than the thickness of the material layer formed by the plasma enhanced deposition process.

4. The method according to claim 1, characterized in that: The grinding in step three and step five is chemical mechanical grinding.

5. The method according to claim 1, characterized in that In the step 4, a dry etching process is used to remove the gate layer in the dummy gate structure.

6. The method according to claim 1, characterized in that The gate layer in the pseudo gate structure includes an interface layer and a gate dielectric layer stacked from bottom to top.

7. The method according to claim 6, characterized in that The material of the interface layer includes titanium nitride.

8. The method according to claim 6, characterized in that The material of the gate dielectric layer is a high dielectric constant material.

9. The method according to claim 8, characterized in that The gate dielectric layer is a stacked structure formed by stacking silicon oxide or silicon oxynitride and the high dielectric constant material from bottom to top.

10. The method according to claim 6, characterized in that The material of the gate layer is amorphous silicon or polycrystalline silicon.

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