Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that a conductive bonding pad is etched through and damaged. The semiconductor structure comprises a substrate with a first groove, a capacitor, the conductive bonding pad and a first conductive plug; the capacitor is arranged in the first groove, and the capacitor comprises a first electrode layer, a dielectric layer and a second electrode layer which are stacked in sequence; the conductive bonding pad is arranged on the substrate and is electrically connected with the first electrode layer; the conductive pad comprises a compensation layer and a conductive layer which are stacked; the first conductive plug is arranged on the substrate; the end, close to the substrate, of the first conductive plug extends into the compensation layer and is spaced from the surface, close to the compensation layer, of the substrate. According to the invention, the thickness of the conductive pad is increased, the conductive pad is prevented from being etched through, and the contact area of the conductive pad and the first conductive plug is increased.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous improvement of chip integration, deep trench capacitors (DTCs) are being used more and more widely. For example, deep trench capacitors can be used in storage units and in silicon interposers to reduce noise on power signals and data signals.

[0003] In the related art, it is usually necessary to form a conductive pad connected to an electrode plate of a deep trench capacitor, and then realize the electrical connection between the conductive pad and the peripheral circuit through a conductive plug. However, when preparing the conductive plug connected to the deep trench capacitor, the conductive pad is easily damaged. Summary of the invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce damage to a conductive pad and reduce the contact resistance between the conductive pad and a first conductive plug.

[0005] A first aspect of an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0006] A substrate having a first groove therein;

[0007] A capacitor, the capacitor is arranged in the first groove, and the capacitor includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence;

[0008] A conductive pad, which is disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer which are stacked;

[0009] A first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

[0010] In some embodiments, the conductive layer is disposed on the compensation layer, and a thickness of the compensation layer is greater than a thickness of the conductive layer.

[0011] In some embodiments, a diameter of the first conductive plug gradually decreases from the compensation layer toward the substrate.

[0012] In some embodiments, the semiconductor structure further includes a first dielectric layer, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer covers the inner wall of the first trench, and the second sub-dielectric layer is disposed on the substrate and connected to the first sub-dielectric layer;

[0013] The first electrode layer at least covers the first sub-dielectric layer.

[0014] In some embodiments, the second electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked in layers, and the first sub-electrode layer covers the dielectric layer;

[0015] The second sub-electrode layer is disposed in the area surrounded by the first sub-electrode layer, and a second conductive plug is disposed in the second sub-electrode layer.

[0016] A second aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0017] providing a substrate, and forming a first trench in the substrate;

[0018] Forming a capacitor and a conductive pad, wherein the capacitor is arranged in the first groove, and the capacitor comprises a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is arranged on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer stacked;

[0019] A first conductive plug is formed, wherein the first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

[0020] In some embodiments, the steps of forming the capacitor and the conductive pad include:

[0021] forming a dielectric material layer and a compensation material layer stacked on the substrate, wherein the dielectric material layer is disposed on the substrate;

[0022] A first electrode material layer, a dielectric layer and a second electrode layer are formed in the first groove, which are stacked in sequence. The first electrode material layer extends outside the first groove and covers the top surface of the compensation material layer. The dielectric layer and the second electrode layer are arranged in sequence on the first electrode material layer. There is a step surface between the first electrode material layer and the second electrode layer, wherein the first electrode material layer and the compensation material layer covered by the second electrode layer constitute the first electrode layer, the first electrode material layer not covered by the second electrode layer constitutes a conductive layer, and the compensation material layer not covered by the second electrode layer constitutes a compensation layer.

[0023] In some embodiments, after the step of forming a stacked second sub-dielectric layer and a compensation layer on the substrate and before the step of forming the first electrode material layer in the first trench, the method further includes:

[0024] The substrate exposed in the first trench is oxidized to form a first sub-dielectric layer, and the first sub-dielectric layer is connected to the second sub-dielectric layer to form a first dielectric layer; wherein the thickness of the first sub-dielectric layer located on the side wall of the first trench is less than the thickness of the first sub-dielectric layer located on the bottom wall of the first trench.

[0025] In some embodiments, the step of forming the first electrode material layer, the dielectric layer, and the second electrode layer stacked in sequence in the first trench comprises:

[0026] forming a first electrode material layer on the inner wall of the first groove, wherein the first electrode material layer extends outside the first groove and covers the compensation material layer;

[0027] forming a dielectric material layer and a second electrode material layer stacked in sequence on the first electrode material layer;

[0028] At least part of the second electrode material layer, the dielectric material layer, the first electrode material layer and the compensation material layer located on one side of the first groove are removed, and a step surface is formed between the second electrode material layer and the first electrode material layer retained on one side of the first groove; wherein the exposed first electrode material layer constitutes the conductive layer, the remaining first electrode material layer constitutes the first electrode layer, the retained dielectric material layer constitutes the dielectric layer, the retained second electrode material layer constitutes the second electrode layer, and the exposed compensation material layer constitutes the compensation layer.

[0029] In some embodiments, the step of forming the first conductive plug and simultaneously forming the second conductive plug, wherein the second conductive plug is connected to the second sub-electrode layer, comprises:

[0030] forming a second dielectric layer, wherein the second dielectric layer covers the substrate and covers each film layer located on the substrate;

[0031] Patterning the second dielectric layer to form a first contact hole and a second contact hole spaced apart in the second dielectric layer, wherein the first contact hole at least exposes a surface of the compensation layer facing away from the substrate, and the bottom of the second contact hole is located in the second sub-electrode layer;

[0032] A first conductive plug is formed in the first contact hole, and a second conductive plug is formed in the second contact hole.

[0033] In the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, the conductive pad is improved, and the conductive pad includes a compensation layer and a conductive layer that are stacked, that is, the compensation layer is added on the basis of the conductive layer, so that the thickness of the conductive pad can be increased. When a contact hole for accommodating the first conductive plug is subsequently formed, the conductive pad can be used as an etching stop layer and can prevent the conductive pad from being etched through, thereby preventing the first conductive plug from being electrically connected to other semiconductor devices located in the substrate, thereby improving the yield of the semiconductor structure.

[0034] In addition, the bottom of the first conductive plug is located inside the conductive pad, and the bottom surface and part of the side surface of the first conductive plug are wrapped by the conductive pad, which can increase the contact area between the first conductive plug and the conductive pad, reduce the contact resistance between the first conductive plug and the conductive pad, and improve the performance of the semiconductor structure.

[0035] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A schematic diagram of a semiconductor structure provided in the related art;

[0038] Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0039] Figure 3 A diagram of the relative positions of the conductive pad and the first conductive plug provided in an embodiment of the present disclosure;

[0040] Figure 4 A relative position diagram of a conductive pad and a first conductive plug provided for related art;

[0041] Figure 5 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of forming a dielectric material layer and a compensation material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0043] Figure 7 A schematic diagram of forming a first trench in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of forming a second sub-dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Fig. 9 Schematic diagram of forming a first electrode material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0046] Fig.10 A schematic diagram of forming a dielectric material layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Fig.11 Schematic diagram of forming a second electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Fig.12 Schematic diagram of forming a second electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0049] Fig.13 A schematic diagram of removing part of a film layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Fig.14 A schematic diagram of forming a capacitor and a conductive pad in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Fig.15 A schematic diagram of forming a second dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Fig.16 A schematic diagram of forming a first conductive plug and a second conductive plug in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0053] Fig.17 A schematic diagram of forming a first dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0054] Fig.18 Schematic diagram of forming a first electrode material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0055] Fig.19 Schematic diagram of forming a compensation material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 .

[0056] Reference numerals:

[0057] 1: substrate; 2: conductive pad; 3: insulating layer; 4: conductive plug;

[0058] 100: substrate; 110: first trench; 120: second trench;

[0059] 200: capacitor; 210: first electrode layer; 211: first electrode material layer; 230: dielectric layer; 231: dielectric material layer; 220: second electrode layer; 221: first sub-electrode layer; 222: second sub-electrode layer; 223: second electrode material layer; 2231: first layer; 2232: second layer;

[0060] 300: conductive pad; 310: compensation layer; 311: compensation material layer; 320: conductive layer;

[0061] 400: first conductive plug; 410: first surface; 420: second surface;

[0062] 500: first dielectric layer; 510: first sub-dielectric layer; 520: second sub-dielectric layer; 530: dielectric material layer;

[0063] 600: a second conductive plug;

[0064] 700: second dielectric layer; 710: first contact hole; 720: second contact hole. DETAILED DESCRIPTION

[0065] As described in the background technology, the problem that the conductive pad is easily damaged during the preparation of the conductive plug in the related technology, the inventors have found that the reason for this problem is that, please refer to the attached Figure 1 In the direction perpendicular to the substrate 1, the thickness of the conductive pad 2 is small. When etching the insulating layer 3 to form the contact hole, the conductive pad 2 cannot be used as an etching barrier due to its small thickness, so that the contact hole will penetrate the conductive pad 2 and even partially etch the substrate 1. Afterwards, the formed conductive plug 4 may penetrate the conductive pad 2 and extend to the substrate 1. In this way, on the one hand, the conductive pad 2 will be damaged, and on the other hand, the conductive plug 4 may be short-circuited with other semiconductor devices in the substrate 1, reducing the yield of the semiconductor structure.

[0066] In view of the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, wherein the conductive pad is improved, and the conductive pad includes a compensation layer and a conductive layer that are stacked, that is, the compensation layer is added on the basis of the conductive layer, so that the thickness of the conductive pad can be increased. When a contact hole for accommodating the first conductive plug is subsequently formed, the conductive pad can be used as an etching stop layer and can prevent the conductive pad from being etched through, thereby preventing the first conductive plug from being electrically connected to other semiconductor devices located in the substrate, thereby improving the yield of the semiconductor structure.

[0067] In addition, the bottom of the first conductive plug is located inside the conductive pad, and the bottom surface and part of the side surface of the first conductive plug are wrapped by the conductive pad, which can increase the contact area between the first conductive plug and the conductive pad, reduce the contact resistance between the first conductive plug and the conductive pad, and improve the performance of the semiconductor structure.

[0068] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0069] Please refer to the attached Figure 2 The embodiments of the present disclosure provide a semiconductor structure, which can be used as a semiconductor device in a dynamic random access memory (DRAM) or as a device in a silicon interposer.

[0070] The semiconductor structure includes a substrate 100, and the substrate 100 is used to provide support for the film layer arranged thereon. When the semiconductor structure is used as a device in a dynamic random access memory (DRAM), the material of the substrate 100 may include the substrate 100 being a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. When the semiconductor structure is used as a device in a silicon adapter, the material of the substrate 100 may include silicon oxide or silicon nitride.

[0071] The substrate 100 has a first groove 110 (see FIG. Figure 7), the depth direction of the first groove 110 is parallel to the direction perpendicular to the substrate 100. It should be noted that, along the direction from the top surface to the bottom surface of the substrate 100, the width of the first groove 110 can be equal everywhere, or can be gradually reduced. This embodiment is not specifically limited here.

[0072] The semiconductor structure also includes a capacitor 200, which is arranged in the first trench 110, so that the capacitor 200 constitutes a deep trench capacitor (DTC). When the capacitor 200 is used as part of a storage unit in a dynamic random access memory (DRAM), compared with the technical solution in the related art in which the capacitor 200 is arranged above the substrate 100, the volume of the dynamic random access memory can be reduced, which facilitates the development of the dynamic random access memory in the direction of integration. When the capacitor 200 is used as a device in a silicon adapter, the power supply signal and / or the data signal can be reduced in noise to ensure the normal operation of chips such as processors and memories. In addition, the space of the silicon adapter can be saved, so that more or larger silicon through holes can be set on the adapter to enhance the signal transmission function of the adapter.

[0073] It should be noted that the capacitor 200 may be partially located in the first trench 110 and partially located on the substrate 100 to facilitate the connection between the electrode layer of the capacitor 200 and the conductive pad.

[0074] The capacitor 200 includes a first electrode layer 210, a dielectric layer 230, and a second electrode layer 220, wherein the first electrode layer 210, the dielectric layer 230, and the second electrode layer 220 are stacked in sequence, and the first electrode layer 210 is arranged close to the inner wall of the first trench 110. The dielectric layer 230 is conformally covered on the first electrode layer 210, and the second electrode layer 220 is conformally covered on the dielectric layer 230. It should be noted that the first electrode layer 210 can be arranged only on the inner wall of the first trench 110, or can extend outside the first trench 110 and cover the substrate 100.

[0075] In this embodiment, the first electrode layer 210 and the second electrode layer 220 are made of the same material and can both include titanium nitride. The first electrode layer 210 and the second electrode layer 220 are made of different materials. For example, the material of the first electrode layer 210 includes titanium nitride, and the second electrode layer 220 includes a mixture of titanium nitride and polysilicon. The material of the dielectric layer 230 is a material with a high dielectric constant K, which can increase the capacitance value of the capacitor 200, thereby increasing the storage capacity of the capacitor or improving the noise removal ability of the capacitor. Among them, the material with a high dielectric constant K can include any one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and strontium titanium oxide (SrTiO3).

[0076] The semiconductor structure further includes a conductive pad 300, which is disposed on the substrate 100 and connected to the first electrode layer 210. The conductive pad 300 includes a compensation layer 310 and a conductive layer 320 which are stacked. In one example, the compensation layer 310 is disposed on the substrate 100, and the conductive layer 320 is disposed on the compensation layer 310. In another example, the conductive layer 320 is disposed on the substrate 100, and the compensation layer 310 is disposed on the conductive layer 320. The material of the compensation layer 310 may be the same as or different from the material of the conductive layer 320. For example, the material of the compensation layer 310 and the material of the conductive layer 320 both include titanium nitride.

[0077] As an example, the thickness of the compensation layer 310 is greater than the thickness of the conductive layer 320, for example, the thickness of the compensation layer 310 is 2-3 times the thickness of the conductive layer 320. In one example, the thickness of the compensation layer 310 is between 40nm and 50nm, and the thickness of the conductive layer 320 is between 20nm and 30nm. In this way, the thickness of the conductive pad 300 can be increased as much as possible, the process window of the contact hole can be expanded, and the bottom of the contact hole can be ensured to stop at the conductive pad 300. For example, the bottom of the contact hole can be ensured to stop at the compensation layer 310 to avoid cutting through the conductive pad 300, thereby improving the yield of the device.

[0078] The first conductive plug 400 is disposed on the substrate 100 and extends in a direction perpendicular to the substrate 100. Among them, one end of the first conductive plug 400 close to the substrate 100 extends into the compensation layer 310, and there is a gap between the first conductive plug 400 and the surface of the substrate 100 close to the compensation layer 310, that is, the first conductive plug 400 does not penetrate the conductive pad 300. It should be noted that when the compensation layer 310 is disposed on the conductive layer 320, the surface of the first conductive plug 400 facing the substrate 100 is flush with the surface of the compensation layer 310 facing the substrate 100, that is, the bottom of the contact hole is located exactly at the interface between the compensation layer 310 and the conductive layer 320.

[0079] In this embodiment, the conductive pad 300 is improved so that the conductive pad 300 includes a compensation layer 310 and a conductive layer 320 which are stacked, that is, the compensation layer 310 is added on the basis of the conductive layer 320, so that the thickness of the conductive pad 300 can be increased. When a contact hole for accommodating the first conductive plug 400 is subsequently formed, the conductive pad 300 can be used as an etching stop layer so that the bottom of the contact hole is located in the conductive pad 300 to prevent the conductive pad 300 from being etched through, thereby improving the process window of the first conductive plug 400, and further preventing the first conductive plug 400 from being electrically connected to other semiconductor devices located in the substrate 100, thereby improving the yield of the semiconductor structure.

[0080] Please refer to the attached Figure 3 , taking the case where the conductive layer 320 is disposed on the compensation layer 310 and the first conductive plug 400 extends into the compensation layer 310 as an example, the contact area between the conductive pad 300 and the first conductive plug 400 is described in detail.

[0081] Taking the cross section parallel to the substrate 100 as the cross section, the cross section of the first conductive plug 400 is circular, the cross section of the first conductive plug 400 and the conductive layer 320 facing away from the substrate 100 is the first surface 410, the diameter of the first surface 410 is d1, the surface of the first conductive plug 400 extending into the compensation layer 310 is the second surface 420, and the diameter of the second surface 420 is d2. The contact area S between the first conductive plug 400 and the conductive pad 300 is equal to πd1 2 +π(d1+d2)h1, wherein h1 is the vertical distance between the first surface 410 and the second surface 420, that is, the thickness of the conductive layer 320 and the partial thickness of the compensation layer 310.

[0082] Please refer to the attached Figure 4 , the first conductive plug 400 in the related art usually penetrates the conductive pad, so the contact area between the first conductive plug 400 and the conductive pad is the side surface of the area where the first conductive plug 400 and the conductive pad are opposite. In view of the small thickness of the conductive pad, the diameter difference between the upper surface and the lower surface of the area where the first conductive plug 400 and the conductive pad are opposite is very small, which is recorded as d3. In the related art, the contact area between the first conductive plug 400 and the conductive pad is equal to π×d3×h2, where j2 is the thickness of the conductive layer 320.

[0083] By comparing the above two formulas, in the semiconductor structure provided by the embodiment of the present disclosure, the contact area between the first conductive plug 400 and the conductive pad 300 is significantly increased, thereby reducing the contact resistance between the first conductive plug 400 and the conductive pad 300, and greatly improving the reliability of the device.

[0084] As a possible implementation, the diameter of the first conductive plug 400 gradually decreases from the direction of the compensation layer 310 toward the substrate 100, that is, along the direction from the top surface of the substrate 100 toward the bottom surface of the substrate 100. That is to say, when forming the contact hole, the process window becomes smaller and smaller, thus reducing the risk of over-etching, avoiding the bottom of the contact hole being located in the conductive pad 300, preventing the conductive pad 300 from being etched through, improving the process window of the first conductive plug 400, and further avoiding the first conductive plug 400 from being electrically connected to other semiconductor devices located in the substrate 100, thereby improving the yield of the semiconductor structure.

[0085] In a possible implementation, the semiconductor structure includes a first dielectric layer 500. The first dielectric layer 500 includes a first sub-dielectric layer 510 and a second sub-dielectric layer 520. The first sub-dielectric layer 510 conformally covers the inner wall of the first trench 110 to achieve an insulation setting between the first electrode layer 210 of the capacitor 200 and other semiconductor devices in the substrate 100. The thickness of the first sub-dielectric layer 510 and the second sub-dielectric layer 520 may be equal everywhere or may be unequal.

[0086] The second dielectric layer 520 is disposed on the substrate 100 and connected to the first dielectric layer 510. In other words, the first dielectric layer 500 covers the inner wall of the first trench 110 and extends outside the first trench 110 to cover the substrate 100.

[0087] The first electrode layer 210 at least covers the first sub-dielectric layer 510. In one example, the first electrode layer 210 covers the first sub-dielectric layer 510, so that the capacitor 200 is disposed in the first trench 110. In another example, the first electrode layer 210 covers the first sub-dielectric layer 510 and also covers a portion of the second sub-dielectric layer 520, so that the storage capacity of the capacitor 200 can be increased, and the connection between the first electrode layer 210 and the conductive pad 300 can be facilitated, so as to facilitate the transmission of semiconductor structure signals.

[0088] In this embodiment, the material of the first dielectric layer 500 includes silicon oxide, but is not limited thereto.

[0089] In a possible implementation, the second electrode layer 220 includes a first sub-electrode layer 221 and a second sub-electrode layer 222 which are stacked, the first sub-electrode layer 221 covers the dielectric layer 230, and the second sub-electrode layer 222 is arranged in the area surrounded by the first sub-electrode layer 221. The material of the first sub-electrode layer 221 includes titanium nitride, and the material of the second sub-electrode layer 222 includes polysilicon.

[0090] The second sub-electrode layer 222 is provided with a second conductive plug 600. In this embodiment, the conductive pad 300 is made of titanium nitride and the second sub-electrode layer 222 is made of polysilicon. Since the two materials are different, when etching to form a contact hole, the etching selectivity can be selectively adjusted to better control the depths of the first conductive plug 400 and the second conductive plug 600, thereby improving the performance of the semiconductor structure.

[0091] It should be noted that the semiconductor structure provided in the embodiment of the present disclosure further includes a second dielectric layer 700, which covers the substrate 100 and the devices located on the substrate 100. In this way, the insulation setting of the first conductive plug 400 and the second conductive plug 600 can be achieved. The material of the second dielectric layer 700 includes silicon nitride, but is not limited thereto.

[0092] Please refer to the attached Figure 5 The present disclosure also provides a method for preparing a semiconductor structure, comprising the following steps:

[0093] Step S100: providing a substrate, and forming a first trench in the substrate.

[0094] Exemplarily, a first trench 110 is formed in the substrate 100 by a patterning process, and the depth direction of the first trench 110 is perpendicular to the substrate 100. The patterning process may be a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process.

[0095] It should be noted that, when the semiconductor structure of this embodiment is a partial structure of a dynamic random access memory (DRAM), the first trench 110 may be formed in the active region.

[0096] Step S200: forming a capacitor and a conductive pad, wherein the capacitor is arranged in the first groove, and the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is arranged on the substrate and electrically connected to the first electrode layer; wherein the conductive pad includes a compensation layer and a conductive layer stacked.

[0097] It should be noted that the compensation layer 310 of the conductive pad 300 in this embodiment may be located below the conductive layer 320 or above the conductive layer 320. The compensation layer 310 and the conductive layer 320 are located at different positions, and the corresponding steps are also different.

[0098] In a possible implementation, the conductive layer 320 is disposed on the compensation layer 310, and the preparation steps are as follows: a dielectric material layer 530 and a compensation material layer 311 are stacked on the substrate 100, and the dielectric material layer 530 is disposed on the substrate 100. The compensation material layer 311 is disposed on the surface of the dielectric material layer 530 away from the substrate 100. It should be noted that the dielectric material layer 530 and the compensation material layer 311 can be formed by directly depositing them on the substrate 100 after forming the first trench 110. Alternatively, they can be formed simultaneously during the process of forming the first trench 110.

[0099] For example, please refer to the attached Figure 6 , a dielectric material layer 530 and a compensation material layer 311 are sequentially stacked on the substrate 100 by using a physical vapor deposition process (PVD). In this embodiment, the compensation material layer 311 is prepared by a physical vapor deposition process, so that a thicker compensation material layer 311 can be formed, thereby increasing the thickness of the conductive pad 300 formed subsequently as much as possible.

[0100] Afterwards, please refer to the attached Figure 7 , patterning the compensation material layer 311, the dielectric material layer 530 and the substrate 100 to form a first trench 110 in the substrate 100. The remaining dielectric material layer 530 constitutes the second sub-dielectric layer 520.

[0101] Afterwards, please refer to the attached Figure 8 , the substrate 100 exposed in the first trench 110 is oxidized to form a first sub-dielectric layer 510, and the first sub-dielectric layer 510 is connected to the second sub-dielectric layer 520 to form a first dielectric layer 500. In this embodiment, the substrate 100 is directly oxidized, so that the first sub-dielectric layer 510 of a certain thickness can be formed only on the inner wall of the first trench 110, and it is not necessary to form a film layer of a certain thickness on the compensation layer 310, and the step of removing the film layer on the compensation layer 310 can be reduced, which has the advantages of simplifying the steps and saving production costs.

[0102] In this embodiment, the thickness of the first sub-dielectric layer 510 located on the side wall of the first trench 110 is less than the thickness of the first sub-dielectric layer 510 located on the bottom wall of the first trench 110. When a voltage is applied to the capacitor, the electric potential tends to accumulate at the bottom of the first trench 110. Therefore, in this embodiment, the thickness of the first sub-dielectric layer 510 located on the bottom wall of the first trench 110 is larger.

[0103] Afterwards, please refer to the attached Fig. 9 To Attachment Fig.14A first electrode material layer 211, a dielectric layer 230 and a second electrode layer 220 are formed in the first groove 110, and are stacked in sequence. The first electrode material layer 211 extends outside the first groove 110 and covers the top surface of the compensation material layer 311. The dielectric layer 230 and the second electrode layer 220 are sequentially arranged in the first electrode material layer 211. There is a step surface between the first electrode material layer 211 and the second electrode layer 220, wherein the first electrode material layer 211 and the compensation material layer 311 covered by the second electrode layer 220 constitute the first electrode layer 210, and the compensation material layer 311 not covered by the second electrode layer 220 constitutes the compensation layer 310.

[0104] For example, please refer to the attached Fig. 9 , the first electrode material layer 211 is formed on the inner wall of the first trench 110 by an atomic layer deposition process, and the first electrode material layer 211 extends outside the first trench 110 and covers the compensation material layer 311. In this embodiment, the first electrode material layer 211 is formed by an atomic layer deposition process, which can improve the uniformity of the first electrode material layer 211 and further improve the step coverage of the first electrode material layer 211.

[0105] Afterwards, please refer to the attached Fig.10 To Attachment Fig.12 , the dielectric material layer 231 and the second electrode material layer 223 are sequentially stacked on the first electrode material layer 211 by continuing the atomic layer deposition process, and the second electrode material layer 223 fills the area surrounded by the dielectric material layer 231. The dielectric material layer 231 is conformally covered on the first electrode material layer 211.

[0106] The second electrode material layer 223 may include a double-layer structure. Exemplarily, the second electrode material layer 223 includes a first layer 2231 and a second layer 2232, wherein the first layer 2231 conformally covers the dielectric material layer 231, and the first layer 2231 surrounds the second trench 120 in the first trench. Afterwards, a second layer 2232 is formed in the second trench 120 using a physical vapor deposition process, and the second layer 2232 fills the second trench 120, extends outside the second trench 120, and covers the first layer 2231. In this embodiment, the material of the first layer 2231 includes titanium nitride, and the material of the second layer 2232 includes polysilicon.

[0107] Afterwards, please refer to the attached Fig.13 and attached Fig.14, at least part of the second electrode material layer 223, the dielectric material layer 231, the first electrode material layer 211 and the compensation material layer 311 located on one side of the first groove 110 are removed, and a step surface is formed between the second electrode material layer 223 and the first electrode material layer 211 retained on one side of the first groove 110; wherein the exposed first electrode material layer 211 constitutes the conductive layer 320, the remaining first electrode material layer 211 constitutes the first electrode layer 210, the retained dielectric material layer 231 constitutes the dielectric layer 230, the retained second electrode material layer 223 constitutes the second electrode layer 220, and the exposed compensation material layer 311 constitutes the compensation layer 310.

[0108] For example, please refer to the attached Fig.13 , a first etching process is used to remove a portion of the second electrode material layer 223, the dielectric material layer 231, the first electrode material layer 211, the compensation material layer 311, and the second sub-dielectric layer 520. Fig.14 , a second etching process is used to remove part of the second electrode material layer 223 and the dielectric material layer 231, so that the remaining second electrode material layer 223 constitutes the second electrode layer 220, and the remaining dielectric material layer 231 constitutes the dielectric layer 230. At this time, there is a step surface between the second electrode layer 220 and the remaining first electrode material layer 211, that is, part of the first electrode material layer 211 is located directly below the second electrode layer 220, and the remaining part of the first electrode material layer 211 is not blocked by the second electrode layer 220.

[0109] Therefore, the first electrode material layer 211 and the compensation material layer 311 covered by the second electrode layer 220 constitute the first electrode layer 210, the first electrode material layer 211 not covered by the second electrode layer 220 constitutes the conductive layer 320, and the compensation material layer 311 not covered by the second electrode layer 220 constitutes the compensation layer 310. The stacked compensation layer 310 and the conductive layer 320 constitute the conductive pad 300.

[0110] Step S300: forming a first conductive plug, wherein the first conductive plug is disposed on a substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

[0111] Please refer to the attached Fig.15 , forming a second dielectric layer 700, the second dielectric layer 700 covers the substrate 100 and covers each film layer on the substrate 100, and the top surface of the second dielectric layer 700 is higher than the top surface of the second electrode layer 220. The material of the second dielectric layer 700 includes silicon nitride, but is not limited thereto.

[0112] Please refer to the attached Fig.16, patterning the second dielectric layer 700 to form a first contact hole 710 and a second contact hole 720 spaced apart in the second dielectric layer 700, wherein the first contact hole 710 at least exposes the surface of the compensation layer 310 facing away from the substrate 100, that is, the bottom of the first contact hole 710 is the top surface of the compensation layer 310, and the bottom of the second contact hole 720 is located in the compensation layer 310. The bottom of the second contact hole 720 is located in the second sub-electrode layer 222.

[0113] After that, continue to refer to the attached Figure 2 , a conductive material is deposited in the first contact hole 710 and the second contact hole 720 respectively by a deposition process to form a first conductive plug 400 in the first contact hole 710 and a second conductive plug 600 in the second contact hole 720. In this step, the second conductive plug 600 connected to the second sub-electrode layer 222 can be formed simultaneously while the first conductive plug 400 is formed, so that the preparation process of the first conductive plug 400 and the second conductive plug 600 can be simplified. The first conductive plug 400 and the second conductive plug 600 are made of the same material, both of which include metal tungsten.

[0114] When forming the first contact hole 710 and the second contact hole 720, in view of the large thickness of the conductive pad 300, the process window of the first contact hole 710 can be expanded to ensure that the bottom of the first contact hole 710 stops well in the conductive pad 300. For example, it is ensured that the bottom of the first contact hole 710 stops well in the compensation layer 310 to avoid cutting through the conductive pad 300, thereby improving the yield of the device. In a possible implementation, the compensation layer 310 is disposed on the conductive layer 320, and the preparation steps thereof are as follows:

[0115] Please refer to the attached Fig.17 A dielectric material layer is formed on the inner wall of the first trench 110 by an atomic deposition process, and the dielectric material layer extends outside the first trench 110 and covers the substrate 100. The dielectric material layer on the inner wall of the first trench 110 constitutes a first sub-dielectric layer 510, and the dielectric material layer on the substrate 100 constitutes a second sub-dielectric layer 520.

[0116] Afterwards, please refer to the attached Fig.18 , a first electrode material layer 211 is formed on the dielectric material layer.

[0117] Afterwards, please refer to the attached Fig.19 , forming a compensation material layer 311 , where the compensation material layer 311 is located on the surface of the first electrode material layer 211 on the substrate 100 .

[0118] You can refer to the attached Fig.10 To Attachment Fig.16The preparation is performed such that, in the formed conductive pad 300 , the conductive layer 320 is located between the compensation layer 310 and the substrate 100 .

[0119] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0120] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0121] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a first groove therein; A capacitor, the capacitor is arranged in the first groove, and the capacitor includes a first electrode layer, a dielectric layer and a second electrode layer stacked in sequence; A conductive pad, which is disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer which are stacked; A first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

2. The semiconductor structure according to claim 1, characterized in that: The conductive layer is disposed on the compensation layer, and a thickness of the compensation layer is greater than a thickness of the conductive layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The diameter of the first conductive plug gradually decreases in a direction from the compensation layer to the substrate.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further includes a first dielectric layer, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer covers the inner wall of the first trench, and the second sub-dielectric layer is disposed on the substrate and connected to the first sub-dielectric layer; The first electrode layer at least covers the first sub-dielectric layer.

5. The semiconductor structure according to claim 1 or 2, characterized in that: The second electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked in layers, and the first sub-electrode layer covers the dielectric layer; The second sub-electrode layer is disposed in the area surrounded by the first sub-electrode layer, and a second conductive plug is disposed in the second sub-electrode layer.

6. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, and forming a first trench in the substrate; Forming a capacitor and a conductive pad, wherein the capacitor is arranged in the first groove, and the capacitor comprises a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is arranged on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer stacked; A first conductive plug is formed, wherein the first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The steps of forming the capacitor and the conductive pad include: forming a dielectric material layer and a compensation material layer stacked on the substrate, wherein the dielectric material layer is disposed on the substrate; A first electrode material layer, a dielectric layer and a second electrode layer are formed in the first groove, which are stacked in sequence. The first electrode material layer extends outside the first groove and covers the top surface of the compensation material layer. The dielectric layer and the second electrode layer are arranged in sequence on the first electrode material layer. There is a step surface between the first electrode material layer and the second electrode layer, wherein the first electrode material layer and the compensation material layer covered by the second electrode layer constitute the first electrode layer, the first electrode material layer not covered by the second electrode layer constitutes a conductive layer, and the compensation material layer not covered by the second electrode layer constitutes a compensation layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: After the step of forming a stacked second sub-dielectric layer and a compensation layer on the substrate and before the step of forming the first electrode material layer in the first trench, the method further includes: The substrate exposed in the first trench is oxidized to form a first sub-dielectric layer, and the first sub-dielectric layer is connected to the second sub-dielectric layer to form a first dielectric layer; wherein the thickness of the first sub-dielectric layer located on the side wall of the first trench is less than the thickness of the first sub-dielectric layer located on the bottom wall of the first trench.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step of forming the first electrode material layer, the dielectric layer and the second electrode layer stacked in sequence in the first trench comprises: forming a first electrode material layer on the inner wall of the first groove, wherein the first electrode material layer extends outside the first groove and covers the compensation material layer; forming a dielectric material layer and a second electrode material layer stacked in sequence on the first electrode material layer; At least part of the second electrode material layer, the dielectric material layer, the first electrode material layer and the compensation material layer located on one side of the first groove are removed, and a step surface is formed between the second electrode material layer and the first electrode material layer retained on one side of the first groove; wherein the exposed first electrode material layer constitutes the conductive layer, the remaining first electrode material layer constitutes the first electrode layer, the retained dielectric material layer constitutes the dielectric layer, the retained second electrode material layer constitutes the second electrode layer, and the exposed compensation material layer constitutes the compensation layer.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step of forming a second conductive plug is performed simultaneously with the step of forming the first conductive plug, wherein the second conductive plug is connected to the second sub-electrode layer, and includes: forming a second dielectric layer, wherein the second dielectric layer covers the substrate and covers each film layer located on the substrate; Patterning the second dielectric layer to form a first contact hole and a second contact hole spaced apart in the second dielectric layer, wherein the first contact hole at least exposes a surface of the compensation layer facing away from the substrate, and the bottom of the second contact hole is located in the second sub-electrode layer; A first conductive plug is formed in the first contact hole, and a second conductive plug is formed in the second contact hole.

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