High-voltage power supply circuit of test equipment

Abstract

The invention provides a high-voltage power supply circuit of test equipment, the high-voltage power supply circuit is independent of the test equipment, and the high-voltage power supply circuit can have N high-voltage output channels, so that the high-voltage power supply circuit can be assembled according to the high-voltage power supply circuit, a functional board card can be customized and designed according to user requirements, and the cost problem caused by integration of a redundant function of the functional board card is avoided; customized board cards are reduced, and the production cost of products is reduced; meanwhile, the voltage and the current of each high-voltage unit can be collected, the channel selection and the working mode of each high-voltage unit can be independently controlled, and the high-voltage output performance of the high-voltage units is improved; in addition, the N high-voltage units multiplex the controller, the DAC module, the ADC module, the OPA module, the multiplex selection circuit and the like, so that the cost is reduced; the number of the high-voltage units is multiple, parallel testing of multiple to-be-tested devices can be supported, and the testing efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of testing technology, and more specifically, particularly relates to a high-voltage power supply circuit of testing equipment. Background Art

[0002] In the field of highly integrated and sophisticated electronic product testing, the ability to perform high voltage (HV) and simultaneous measurements (i.e., testing multiple units or parameters at the same time) is a key indicator for evaluating the performance of test equipment. In the current market, advanced testers such as Magnum 2 and T5830 meet this demand with their excellent performance.

[0003] Taking T5830 as an example, its built-in HV LVL DR module is a highlight of this model in the field of high-voltage testing. The module consists of 48 independent units, each of which has the ability to output high voltage up to 30V and can operate stably at a maximum current of 90mA. This design not only ensures the accuracy of the test, but also achieves an amazing scalability of a total of 288 high-voltage output channels through the flexibility of each unit being configured to 6 branches. In addition, T5830 also allows users to merge every 2 units into one MC (Management Cel) and flexibly configure it to VSIM (Virtual Simulation Mode) mode or MVM (Multi-Variable Measurement) mode according to test requirements, further improving the flexibility and efficiency of the test. Magnum 2, which has a similar structure to T5830, also has these advanced features.

[0004] Although high-end testers such as Magnum 2 and T5830 perform well in high voltage and DATC measurements, their cost issues cannot be ignored. Taking Magnum 2 as an example, its high price (about RMB 7 million to 8 million) often discourages many potential users. What is even more regrettable is that due to the modular design of the tester, users often cannot purchase the required HV modules separately, but must bear the full cost of the entire machine, which undoubtedly increases the test cost and limits the effective use of test resources. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a high-voltage power supply circuit of a test device, which is independent of the test device and can be assembled according to requirements, thereby reducing the test cost.

[0006] The present application discloses a high-voltage power supply circuit of a test device, wherein the high-voltage power supply circuit is independent of the test device; the high-voltage power supply circuit comprises: a controller, a DAC module, an OPA module, an ADC module and M high-voltage output circuits; the high-voltage output circuit comprises: a multiplexing selection circuit, N high-voltage channel selection circuits and N high-voltage units, and the multiplexing selection circuit comprises: an ADC channel selection circuit, a VSIM channel selection circuit and an MVM channel selection circuit; M is a positive integer, and N is an integer greater than 1; wherein:

[0007] The N high-voltage channel selection circuits correspond to the N high-voltage units in a one-to-one manner;

[0008] The first end of the controller is connected to one end of the high-voltage channel selection circuit through the DAC module, the OPA module, and the high-voltage unit in sequence;

[0009] The other end of the high-voltage channel selection circuit serves as an output end of the high-voltage power supply circuit and is connected to the device under test;

[0010] The second end of the controller is connected to the output end of the ADC module;

[0011] The four input terminals of the ADC module correspond one to one with the four output terminals of the ADC channel selection circuit; each input terminal of the ADC module is correspondingly connected with each output terminal of the ADC channel selection module;

[0012] The two first input terminals of the ADC channel selection module correspond one to one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is correspondingly connected with each output terminal of the VSIM channel selection circuit;

[0013] The two second input terminals of the ADC channel selection module correspond one to one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is correspondingly connected with each output terminal of the MVM channel selection circuit;

[0014] The two input terminals of the VSIM channel selection circuit are connected to the positive and negative electrodes of the current sampling terminal in the high voltage unit correspondingly;

[0015] An input end of the MVM channel selection circuit is connected to a voltage sampling end of the high voltage unit;

[0016] The ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high-voltage unit and the high-voltage channel selection circuit are all controlled by the controller.

[0017] Optionally, the OPA module includes: an in-phase adder and a follower;

[0018] The input end of the in-phase adder is connected to the output end of the DAC module;

[0019] The output end of the in-phase adder is connected to the input end of the follower;

[0020] The output end of the follower serves as the output end of the OPA module;

[0021] The positive pole of the power supply end of the in-phase adder and the positive pole of the power supply end of the follower are both connected to a 30V power supply;

[0022] The negative electrode of the power supply end of the in-phase adder and the negative electrode of the power supply end of the follower are both connected to a -5V power supply.

[0023] Optionally, the in-phase adder includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier and a first capacitor;

[0024] One end of the third resistor serves as an input end of the in-phase adder;

[0025] The non-inverting input terminal of the first operational amplifier is respectively connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor;

[0026] The negative phase input terminal of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor respectively;

[0027] The output end of the first operational amplifier is connected to the other end of the second resistor, and the connection point serves as the output end of the in-phase adder;

[0028] The positive and negative electrodes of the power supply terminal of the first operational amplifier serve as the positive and negative electrodes of the power supply terminal of the in-phase adder respectively;

[0029] The other end of the fourth resistor is connected to a reference power supply; the other end of the first capacitor and the other end of the first resistor are grounded.

[0030] Optionally, the follower includes: two follower units; a connection point after the input ends of the two follower units are connected serves as the input end of the follower; and the output ends of the two follower units serve as the output ends of the follower respectively;

[0031] The follower unit includes: a second operational amplifier, a fifth resistor and a sixth resistor;

[0032] The non-inverting input terminal of the second operational amplifier serves as the input terminal of the follower unit;

[0033] The negative input terminal of the second operational amplifier is respectively connected to the output terminal of the second operational amplifier, one end of the fifth resistor and one end of the sixth resistor;

[0034] The other end of the sixth resistor is grounded;

[0035] The other end of the fifth resistor serves as the output end of the follower unit;

[0036] The positive and negative electrodes of the power supply terminals of the second operational amplifier serve as the positive and negative electrodes of the power supply terminals of the follower unit.

[0037] Optionally, N is 16; the OPA module has 2 output terminals;

[0038] wherein the input ends of eight of the high voltage units are connected to an output end of the OPA module;

[0039] The input ends of the other eight high-voltage units are connected to another output end of the OPA module.

[0040] Optionally, the high voltage unit includes: an HV operational amplifier circuit, a current sampling circuit and a switch unit; the HV operational amplifier circuit includes: a high voltage operational amplifier, a seventh resistor, an eighth resistor and a ninth resistor; the current sampling circuit includes: a tenth resistor and a first switch; the switch unit includes: a second switch and a third switch;

[0041] The non-inverting input terminal of the high-voltage operational amplifier serves as the input terminal of the high-voltage unit;

[0042] The negative input terminal of the high-voltage operational amplifier is connected to one end of the seventh resistor;

[0043] The output end of the high-voltage operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and the connection point serves as the positive electrode of the current sampling end of the high-voltage unit;

[0044] The other end of the ninth resistor is respectively connected to one end of the third switch, one end of the eighth resistor and one end of the first switch, and the connection point serves as the negative electrode of the current sampling terminal of the high voltage unit;

[0045] The other end of the seventh resistor is connected to the other end of the eighth resistor and one end of the second switch respectively, and the connection point serves as a voltage sampling end of the high-voltage unit;

[0046] The other end of the first switch is connected to the other end of the tenth resistor;

[0047] The other end of the second switch serves as the first output end of the high voltage unit;

[0048] The other end of the third switch serves as the second output end of the high voltage unit.

[0049] Optionally, the high-voltage channel selection circuit includes: a first channel switch and a second channel switch;

[0050] One end of the first channel switch is connected to the first output end of the high voltage unit;

[0051] One end of the second channel switch is connected to the second output end of the high voltage unit;

[0052] The other end of the first channel switch is connected to the other end of the second channel switch, and the connection point serves as the output end of the high-voltage channel selection circuit.

[0053] Optionally, the ADC channel selection circuit includes: four MUX switches, four MUX operational amplifiers, and four MUX resistors;

[0054] One end of the first MUX switch serves as a first input end of the ADC channel selection circuit; the other end of the first MUX switch is respectively connected to one end of the first MUX resistor and the positive input end of the first MUX operational amplifier; the other end of the first MUX resistor is grounded; the positive electrode of the power supply end of the first MUX operational amplifier is connected to the positive power supply; the negative electrode of the power supply end of the first MUX operational amplifier is connected to the negative power supply; the output end of the first MUX operational amplifier serves as the first output end of the ADC channel selection circuit;

[0055] One end of the second MUX switch serves as another first input end of the ADC channel selection circuit; the other end of the second MUX switch is respectively connected to one end of the second MUX resistor and the positive input end of the second MUX operational amplifier; the other end of the second MUX resistor is grounded; the output end of the second MUX operational amplifier serves as the second output end of the ADC channel selection circuit;

[0056] One end of the third MUX switch serves as a second input end of the ADC channel selection circuit; the other end of the third MUX switch is respectively connected to one end of the third MUX resistor and the positive input end of the third MUX operational amplifier; the other end of the third MUX resistor is grounded; the positive electrode of the power supply end of the third MUX operational amplifier is connected to the positive power supply; the negative electrode of the power supply end of the third MUX operational amplifier is connected to the negative power supply; the output end of the third MUX operational amplifier serves as the third output end of the ADC channel selection circuit;

[0057] One end of the fourth MUX switch serves as another second input end of the ADC channel selection circuit; the other end of the fourth MUX switch is respectively connected to one end of the fourth MUX resistor and the positive input end of the fourth MUX operational amplifier; the other end of the fourth MUX resistor is grounded; and the output end of the fourth MUX operational amplifier serves as the fourth output end of the ADC channel selection circuit.

[0058] Optionally, the VSIM channel selection circuit includes: two first multiplexing circuits; the first multiplexing circuit includes: a first multiplexing chip, a fifth MUX operational amplifier, a sixth MUX operational amplifier, a gain chip and four multiplexing resistors;

[0059] The VDD pin of the first multiplexing chip is connected to a positive power supply; the VSS pin thereof is connected to a negative power supply; and the EPAD pin and the GND pin thereof are both grounded;

[0060] The non-inverting input terminal of the fifth MUX operational amplifier is connected to the DA pin of the first multiplexing chip;

[0061] The negative input terminal of the fifth MUX operational amplifier is connected to the output terminal of the fifth MUX operational amplifier, one end of the first multiplexing resistor, and one end of the second multiplexing resistor;

[0062] The non-inverting input terminal of the sixth MUX operational amplifier is connected to the DB pin of the first multiplexing chip;

[0063] The other end of the first multiplexed resistor is connected to the -INA pin of the gain chip;

[0064] The negative input terminal of the sixth MUX operational amplifier is connected to the output terminal of the sixth MUX operational amplifier, one end of the third multiplexing resistor, and one end of the fourth multiplexing resistor;

[0065] The other end of the third multiplexed resistor is connected to the +INA pin of the gain chip;

[0066] The other end of the second multiplexed resistor, the other end of the fourth multiplexed resistor and the REF pin of the gain chip are all grounded;

[0067] The positive electrode of the power supply end of the fifth MUX operational amplifier, the positive electrode of the power supply end of the sixth MUX operational amplifier, and the positive electrode of the power supply end of the gain chip are connected to a positive power supply;

[0068] The negative electrode of the power supply terminal of the fifth MUX operational amplifier, the negative electrode of the power supply terminal of the sixth MUX operational amplifier, and the negative electrode of the power supply terminal of the gain chip are connected to a negative power supply;

[0069] The OUT pin of the gain chip is connected to the anode of the first diode, and the connection point serves as the output end of the first multiplexing circuit;

[0070] The input end of the first multiplexing chip serves as the input end of the first multiplexing circuit;

[0071] A cathode of the first diode receives a first clamping voltage.

[0072] Optionally, the MVM channel selection circuit includes: two second multiplexing circuits, and the second multiplexing circuit includes: a second multiplexing chip and a seventh MUX operational amplifier;

[0073] The input end of the second multiplexing chip serves as the input end of the second multiplexing circuit;

[0074] The D pin of the second multiplexing chip is connected to one end of the fifth multiplexing resistor;

[0075] The other end of the fifth multiplexing resistor is respectively connected to the non-inverting input end of the seventh MUX operational amplifier and one end of the sixth multiplexing resistor, and the other end of the sixth multiplexing resistor is grounded;

[0076] The negative phase input terminal of the seventh MUX operational amplifier is respectively connected to one end of the seventh multiplexing resistor and one end of the eighth multiplexing resistor;

[0077] The other end of the seventh multiplexed resistor receives a bias voltage;

[0078] The output end of the seventh MUX operational amplifier is respectively connected to the other end of the eighth multiplexing resistor and the anode of the second diode, and the connection point serves as the output end of the second multiplexing circuit;

[0079] A cathode of the second diode receives a second clamping voltage.

[0080] It can be seen from the above technical scheme that the present invention provides a high-voltage power supply circuit of a test device, which is independent of the test device, and the high-voltage power supply circuit can have N high-voltage output channels, and can be assembled according to the high-voltage power supply circuit, and the functional board can be customized and designed according to user needs, so as to avoid the cost problem caused by the integration of redundant functions of the functional board, reduce the customized board and reduce the product production cost; at the same time, the voltage and current of each high-voltage unit can be collected, and the channel selection and working mode of each high-voltage unit can be independently controlled to improve the high-voltage output performance of the high-voltage unit; in addition, N high-voltage units reuse controllers, DAC modules, ADC modules, OPA modules and reuse selection circuits, etc., to reduce costs; the number of high-voltage units is multiple, which can support parallel testing of multiple devices under test and improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0082] Figure 1is a schematic diagram of a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0083] Figure 2 is a schematic diagram of a DAC module involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0084] Figure 3 is a schematic diagram of an OPA module involved in a high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0085] Figure 4 It is a schematic diagram of a common-phase adder involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0086] Figure 5 is a schematic diagram of a follower involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0087] Figure 6 It is a schematic diagram of a high-voltage output channel in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0088] Figure 7 It is a schematic diagram of an integrated module of a high-voltage unit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0089] Figure 8 is another schematic diagram of an integrated module of a high-voltage unit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0090] Fig. 9 It is a schematic diagram of a high-voltage unit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0091] Fig.10 It is a schematic diagram of a high-voltage channel selection circuit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0092] Fig.11 It is a schematic diagram of a sampling module involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0093] Fig.12 It is a schematic diagram of a VSIM channel selection circuit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0094] Fig.13 It is a schematic diagram of an MVM channel selection circuit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0095] Fig.14It is a schematic diagram of an ADC channel selection circuit involved in a high-voltage power supply circuit of a test device provided by an embodiment of the present invention;

[0096] Fig.15 It is a schematic diagram of an ADC module involved in a high-voltage power supply circuit of a test device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0097] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0098] In the present application, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one ..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the terms "first", "second", "third", "fourth", etc. (if present) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here, for example.

[0099] An embodiment of the present application provides a high-voltage power supply circuit for a test device, which is used to solve the problem that the modular design of existing test machines in the prior art is that users are often unable to purchase the required HV modules separately, but must bear the full cost of the entire machine, which undoubtedly increases the testing cost and limits the effective utilization of testing resources.

[0100] The high-voltage power supply circuit is independent of the test equipment. That is to say, the user can purchase the high-voltage power supply circuit separately, and then assemble it according to the high-voltage power supply circuit to obtain the test equipment required by the user. The assembly method can improve the user's personalized configuration and avoid the cost problem caused by the integration of redundant functions.

[0101] See also Figure 1 The high-voltage power supply circuit includes: a controller, a DAC module, an OPA module, an ADC module and M high-voltage output circuits.

[0102] DAC module, or Digital-to-Analog Converter, is an electronic component that converts digital signals into analog signals. Its main components include digital signal processing module, digital analog-to-digital conversion module, digital signal output module, and analog signal processing module. The DAC module receives digital signals, processes and converts them internally, and finally outputs analog signals. This conversion is widely used in many fields such as audio, video, and communication. For example, in an audio system, the DAC module can convert digital audio signals into analog audio signals so that they can be played through speakers.

[0103] The performance indicators of DAC modules include resolution, update rate, etc. Resolution determines the accuracy of the analog signal that the DAC can generate, while the update rate determines the speed at which the DAC can process digital signals. DAC modules with high resolution and fast update rate can provide higher quality analog signal output.

[0104] OPA module, usually refers to operational amplifier (OperationalAmplifier), is a circuit unit with a very high amplification factor. The operational amplifier contains a multi-stage amplification circuit, which can amplify and process weak signals. Operational amplifiers have a variety of applications, such as signal amplification, filtering, comparison, etc. In electronic systems, operational amplifiers are often used as core components of signal conditioning circuits to improve the signal processing capability and accuracy of the system.

[0105] The main parameters of an operational amplifier include input offset voltage, open-loop voltage gain, closed-loop bandwidth, etc. These parameters determine the performance of the operational amplifier. For example, the smaller the input offset voltage, the higher the precision of the operational amplifier; the larger the open-loop voltage gain, the stronger the amplification ability of the operational amplifier.

[0106] ADC module, or Analog-to-Digital Converter, is an electronic component that converts analog signals into digital signals. The main components of the ADC module include analog signal sampling module, analog signal processing module, analog-to-digital conversion module, and digital signal processing module. The ADC module collects analog signals, processes and converts them internally, and finally outputs digital signals. This conversion is widely used in many fields such as digital signal processing and control systems.

[0107] The performance indicators of the ADC module include resolution, sampling rate, etc. Resolution determines the accuracy of the analog signal that the ADC can identify, while the sampling rate determines the speed at which the ADC can collect analog signals. ADC modules with high resolution and high sampling rate can provide more accurate digital signal output.

[0108] The number of high-voltage output circuits can be multiple or one, for example, the number of high-voltage output circuits is 8, that is, M = 8. It can be determined according to the actual situation and is within the protection scope of this application.

[0109] The high-voltage output circuit includes: a multiplexing selection circuit, N high-voltage channel selection circuits and N high-voltage units HVunit. The multiplexing selection circuit includes: an ADC channel selection circuit, a VSIM channel selection circuit and an MVM channel selection circuit.

[0110] It should be noted that if Figure 1 As shown, FPGA is control; DAC is DAC module; OPA is OPA module; HV unit is high voltage unit; HV channel selection is high voltage channel selection circuit; HV-ADC channel selection is ADC channel selection circuit; HV-VSIM channel selection is VSIM channel selection circuit; HV-MVM channel selection is MVM channel selection circuit; V1, V2, and V3 are voltages of each node respectively.

[0111] M is a positive integer, and N is an integer greater than 1.

[0112] The N high-voltage channel selection circuits correspond to the N high-voltage units HV unit one by one. That is, a high-voltage unit HV unit is used as a high-voltage output channel, and the high-voltage channel selection circuit can select the state of each high-voltage output channel, that is, select the working mode of the high-voltage unit HV unit.

[0113] The multiplexing selection circuit can collect electrical signals from each high-voltage output channel, such as current and voltage, and feed these electrical signals back to the controller through the ADC module, so that the controller controls the working state of the multiplexing selection circuit according to the signal corresponding to the high-voltage output channel, thereby realizing the working mode control of the high-voltage unit HV unit.

[0114] The first end of the controller is connected to one end of the high-voltage channel selection circuit through the DAC module, the OPA module, and the high-voltage unit HV unit in sequence.

[0115] Specifically, the first end of the controller is connected to the input end of the DAC module, the output end of the DAC module is connected to the input end of the OPA module; the output end of the OPA is connected to the input end of the high voltage unit HV unit, and the output end of the high voltage input unit is connected to the input end of the channel to the selection circuit.

[0116] It should be noted that the number of N can be multiple or 1, for example, N=16; it will not be described in detail here, and it depends on the actual situation, and it is all within the protection scope of this application.

[0117] The number of high-voltage output channels of the high-voltage power supply circuit is N*M; that is, when M=1 and N is 16, the number of high-voltage output channels of the high-voltage power supply circuit is 16; when M=8 and N is 16, the number of high-voltage output channels of the high-voltage power supply circuit is 128; other values ​​are not repeated here one by one.

[0118] The other end of the high voltage channel selection circuit serves as an output end of the high voltage power supply circuit and is connected to the device under test.

[0119] The other end of each high-voltage channel selection circuit can be an output end of a high-voltage power supply circuit, that is, the high-voltage power supply circuit can be connected to N*M devices to be tested. Furthermore, the present application can be configured with more high-voltage output circuits and high-voltage units HVunit to achieve simultaneous testing of multiple devices to be tested, thereby improving test efficiency.

[0120] The second terminal of the controller is connected to the output terminal of the ADC module.

[0121] That is, the controller receives the signal fed back by the ADC module.

[0122] The four input terminals of the ADC module correspond one to one with the four output terminals of the ADC channel selection module; each input terminal of the ADC module is connected to each output terminal of the ADC channel selection module accordingly.

[0123] Specifically, the first input end of the ADC is connected to the first output end of the ADC channel selection module; the second input end of the ADC is connected to the second output end of the ADC channel selection module; the third input end of the ADC is connected to the third output end of the ADC channel selection module; and the fourth input end of the ADC is connected to the fourth output end of the ADC channel selection module.

[0124] The two first input terminals of the ADC channel selection module correspond one to one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is connected to each output terminal of the VSIM channel selection circuit. Specifically, one first input terminal of the ADC channel selection module is connected to one output terminal of the VSIM channel selection circuit; the other first input terminal of the ADC channel selection module is connected to the other output terminal of the VSIM channel selection circuit.

[0125] The two second input terminals of the ADC channel selection module correspond one to one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is connected to each output terminal of the MVM channel selection circuit. Specifically, one second input terminal of the ADC channel selection module is connected to one output terminal of the MVM channel selection circuit; the other second input terminal of the ADC channel selection module is connected to the other output terminal of the MVM channel selection circuit.

[0126] The two input ends of the VSIM channel selection circuit are connected to the positive and negative poles of the current sampling end in the high-voltage unit HVunit accordingly; specifically, one input end of the VSIM channel selection circuit is connected to the positive pole of the current sampling end in the high-voltage unit HV unit; the other input end of the VSIM channel selection circuit is connected to the negative pole of the current sampling end in the high-voltage unit HV unit; the current signal of the high-voltage unit HV unit of the VSIM channel selection circuit.

[0127] The input end of the MVM channel selection circuit is connected to the voltage sampling end of the high voltage unit HV unit.

[0128] That is, the MVM channel selection circuit receives the voltage signal of the high voltage unit HV unit.

[0129] The ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high voltage unit HV unit and the high voltage channel selection circuit are all controlled by the controller.

[0130] Specifically, the controller controls the paths in the ADC channel selection circuit, the VSIM channel selection circuit, and the MVM channel selection circuit to achieve current sampling and voltage sampling for the corresponding high-voltage unit HV unit; at the same time, by controlling the working state of the high-voltage channel selection circuit, the working state of the high-voltage output path in which it is located is achieved.

[0131] It should be noted that the high-voltage power supply circuit is one of the high-voltage functional modules of the general functions of the ATE tester. Different companies have different strategies and different ways of integrating and distributing functional modules. You can use one board with multiple functional modules, or you can use one board with one function and insert multiple boards with different functions to meet the various functional requirements of the tester. Different strategies determine the configuration functions of the tester, and thus determine the cost price of the tester.

[0132] The existing products on the market have already solidified their configuration methods, but customers’ needs are diverse. Some customers’ needs have overflowed functions, and the cost exceeds their budget.

[0133] This application describes a design scheme in which a single module of a high-voltage power supply circuit can have 16 high-voltage output channels, so that functional boards can be designed according to customer needs, and customized boards can be used to reduce product production costs.

[0134] In this embodiment, wherein: N high-voltage channel selection circuits correspond to N high-voltage units one by one; the first end of the controller is connected to one end of the high-voltage channel selection circuit through the DAC module, the OPA module, and the high-voltage unit in sequence; the other end of the high-voltage channel selection circuit is connected to the device under test as an output end of the high-voltage power supply circuit; the second end of the controller is connected to the output end of the ADC module; the four input ends of the ADC module correspond to the four output ends of the ADC channel selection module one by one; each input end of the ADC module is connected to each output end of the ADC channel selection module; the two first input ends of the ADC channel selection module correspond to the two output ends of the VSIM channel selection circuit; each first input end of the ADC channel selection module is connected to each output end of the VSIM channel selection circuit; the two second input ends of the ADC channel selection module correspond to the two output ends of the MVM channel selection circuit; each second input end of the ADC channel selection module is connected to each output end of the MVM channel selection circuit; VSIM channel selection The two input ends of the selection circuit are connected to the positive and negative poles of the current sampling end in the high-voltage unit correspondingly; the input end of the MVM channel selection circuit is connected to the voltage sampling end of the high-voltage unit; the ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high-voltage unit and the high-voltage channel selection circuit are all controlled by the controller; that is to say, the high-voltage power supply circuit is independent of the test equipment, and the high-voltage power supply circuit can have N high-voltage output channels, and then it can be assembled according to the high-voltage power supply circuit, and the functional board can be customized and designed according to user needs to avoid the cost problem caused by the integration of redundant functions of the functional board, reduce the customized board and reduce the product production cost; at the same time, the voltage and current of each high-voltage unit can be collected, and the channel selection and working mode of each high-voltage unit can be independently controlled to improve the high-voltage output performance of the high-voltage unit; in addition, N high-voltage units reuse controllers, DAC modules, ADC modules, OPA modules and reuse selection circuits, etc., to reduce costs; the number of high-voltage units is multiple, which can support parallel testing of multiple devices under test and improve test efficiency.

[0135] Optional, such as Figure 2 As shown, the DAC module can be implemented by using a DAC chip plus peripheral devices; specifically, Figure 2 As shown, the DAC module can use the 16-bit high-precision DAC chip AD5761R to achieve digital-to-analog conversion.

[0136] The VDD pin and VSS pin of the DAC chip are connected to ±15V power supplies respectively, its DVCC pin is connected to VCC_3.3V power supply, and the VREFIN pin is the input pin of the 2.5V reference voltage, which serves as the reference voltage for digital-to-analog conversion.

[0137] That is to say, the DAC chip integrates a sophisticated power management design, where the VDD pin is connected to the +15V power supply as the positive power supply VDD input; and the VSS pin is connected to the -15V power supply as the negative power supply VSS input. This bipolar power supply configuration ensures that the DAC chip can operate stably and efficiently. In addition, the DVCC pin is specially designed to receive the VCC_3.3V power supply, which is designed for the digital logic part to ensure the stability and reliability of the SPI communication interface.

[0138] To provide an accurate reference for digital-to-analog conversions, the VREFIN pin is configured to receive a 2.5V reference voltage input. This stable reference voltage is critical to ensuring the accuracy of the DAC output signal, and it serves as the reference point for all analog output conversions.

[0139] Its LED4 is the DAC fault warning light. When the temperature of the DAC chip exceeds 150℃, the output is short-circuited, and when the DAC chip is undervoltage, this pin is pulled low and the light comes on to warn.

[0140] In other words, the system is also equipped with a fault monitoring and alarm mechanism, which is implemented through the LED4 fault alarm light. When the DAC chip encounters an abnormal situation, such as the temperature exceeds the safety threshold of 150℃, the output end is short-circuited, or the chip is undervoltage, the LED4 pin will be pulled low, thereby lighting the alarm light and notifying maintenance personnel to handle it in time.

[0141] The DAC chip communicates with the FPGA (controller) through the SPI serial bus. The FPGA uses SPI serial communication to control the AD5761R output VOUT voltage V1 through the corresponding pins. The output VOUT voltage V1 can reach a range of -10V to 10V. This range does not meet the high-voltage output range of -5V to 30V, so an OPA module (bias amplifier circuit) is required to achieve voltage adjustment.

[0142] That is to say, in terms of communication, the DAC chip is seamlessly connected to the FPGA controller through the SPI (Serial Peripheral Interface) bus. As the master control unit, the FPGA accurately controls the analog voltage V1 (i.e. VOUT) required for the AD5761R chip to output through the SPI communication protocol. It is worth noting that although the DAC chip supports an output range of -10V to 10V, this is not enough to meet the high voltage requirements of -5V to 30V in some application scenarios.

[0143] To this end, the system introduced an OPA module (bias amplifier circuit) as a key processing link after the DAC module output. It achieved bias adjustment and amplification of the DAC output signal, successfully expanding the voltage range to -5V to 30V, thus meeting a wider range of high-voltage application needs. This design not only improves the flexibility and adaptability of the system, but also ensures the accuracy and stability of the output signal.

[0144] Optional, such as Figure 3 As shown, the OPA module includes: an in-phase adder and a follower.

[0145] The input end of the in-phase adder is connected to the output end of the DAC module; the output end of the in-phase adder is connected to the input end of the follower; the output end of the follower serves as the output end of the OPA module; the positive pole of the power supply end of the in-phase adder and the positive pole of the power supply end of the follower are both connected to a 30V power supply; the negative pole of the power supply end of the in-phase adder and the negative pole of the power supply end of the follower are both connected to a -5V power supply.

[0146] As a key link in the signal processing chain, the in-phase adder has its input directly connected to the output of the DAC module, ensuring that the analog voltage signal generated by the DAC module (such as a DAC chip) can be transmitted to the in-phase adder for processing without loss. The in-phase adder here plays the role of adding the DAC module output signal with other possible signal sources (which can be a reference power supply) to achieve in-phase superposition of the signal. The other signal source can be a reference power supply, and the voltage of the reference power supply can be 5V. Of course, other possibilities are not excluded, and they will not be repeated here.

[0147] The follower, as a buffer amplifier with high input impedance and low output impedance, can effectively isolate the influence of the subsequent circuit on the previous circuit, while maintaining the integrity of the signal and driving the subsequent circuit. In this way, the signal processed by the in-phase adder can be stably transmitted to the follower.

[0148] That is to say, the in-phase adder realizes the bias amplification and adjustment of the output voltage of the DAC module, and the voltage follower realizes the isolation and driving of the DAC output voltage.

[0149] As the core of voltage regulation, the OPA module is responsible for further amplifying the signal output by the follower and adjusting it to the required voltage range, i.e. -5V to 30V, to meet the needs of high-voltage applications.

[0150] In terms of power supply, both the in-phase adder and the follower use a bipolar power supply to ensure the stability and performance of the circuit. Specifically, the positive pole of the power supply end of the in-phase adder and the positive pole of the power supply end of the follower are connected to a 30V power supply to provide a positive bias voltage for the circuit; and their negative poles are connected to a -5V power supply at the same time to provide a negative bias voltage for the circuit. This symmetrical power supply configuration helps reduce the impact of power supply noise on circuit performance and improves the stability and reliability of the overall circuit.

[0151] Optional, such as Figure 4 The in-phase adder shown includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier and a first capacitor.

[0152] One end of the third resistor is connected to the output end of the DAC module as the input end of the in-phase adder. The precise analog signal generated by the DAC module can flow into the in-phase adder without hindrance for subsequent signal processing.

[0153] The non-inverting input terminal of the first operational amplifier is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor respectively. The connection method not only realizes the convergence of signals, but also filters the signals to a certain extent through the addition of capacitors, thereby reducing the interference of high-frequency noise.

[0154] The negative phase input terminal of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor, respectively. That is, the negative phase input terminal of the first operational amplifier forms a feedback network with one end of the first resistor and the other end of the second resistor. This feedback mechanism is crucial to maintaining the operation of the operational amplifier in the linear amplification region, ensuring that the in-phase adder can accurately perform voltage amplification and signal addition operations.

[0155] The output end of the first operational amplifier is connected to the other end of the second resistor, and the connection point serves as the output end of the in-phase adder and is connected to the input end of the second operational amplifier.

[0156] The positive and negative poles of the power supply terminal of the first operational amplifier serve as the positive and negative poles of the power supply terminal of the in-phase adder respectively; that is, the positive pole of the power supply terminal of the first operational amplifier is connected to the 30V power supply, and the negative pole of the power supply terminal is connected to the -5V power supply.

[0157] The other end of the fourth resistor is connected to the reference power supply; the other end of the first capacitor and the other end of the first resistor are grounded.

[0158] In terms of power supply, the first operational amplifier adopts a bipolar power supply mode, and the positive and negative poles of its power supply end are directly used as the positive and negative poles of the power supply end of the in-phase adder. Specifically, the positive pole of the power supply end is connected to a stable 30V power supply to provide a positive bias for the circuit; and the negative pole of the power supply end is connected to a -5V power supply to provide a negative bias for the circuit. This symmetrical power supply configuration not only ensures that the operational amplifier can work stably, but also reduces the impact of power supply fluctuations on circuit performance.

[0159] In addition, the other end of the fourth resistor is carefully connected to the reference power supply to provide a certain bias current or voltage for the circuit. The other end of the first capacitor and the other end of the first resistor are both grounded, which not only provides a stable reference potential for the circuit, but also helps to reduce interference and noise in the circuit.

[0160] The voltage range is amplified to -5V~30V through the in-phase adder circuit.

[0161] The formula for the in-phase adder is as follows:

[0162]

[0163]

[0164] Among them, V1: -10V to 10V (output voltage of DAC module); V2 = 5V (reference voltage).

[0165] Therefore, according to the above formula, V OUT The range is -10V to 30V, but because the negative power supply VSS of the first operational amplifier is -5V, the negative voltage range is clamped by the power supply, and the output voltage range is -5V to 30V.

[0166] Optionally, the follower includes: two follower units; a connection point after the input ends of the two follower units are connected as the input end of the follower; and the output ends of the two follower units are respectively used as the output ends of the follower.

[0167] The follower unit includes: a second operational amplifier.

[0168] The positive input terminal of the second operational amplifier is used as the input terminal of the follower unit and connected to the output terminal of the in-phase adder. The negative input terminal of the second operational amplifier is respectively connected to the output terminal of the second operational amplifier, and the connection point is used as the output terminal of the follower unit; the positive and negative poles of the power supply terminal of the second operational amplifier are used as the positive and negative poles of the power supply terminal of the follower unit.

[0169] Specifically, the follower unit may further be provided with a fifth resistor and a sixth resistor.

[0170] The positive input terminal of the second operational amplifier is used as the input terminal of the follower unit and is connected to the output terminal of the in-phase adder. The negative input terminal of the second operational amplifier is respectively connected to the output terminal of the second operational amplifier, one end of the fifth resistor and one end of the sixth resistor, and the other end of the sixth resistor is grounded. The other end of the fifth resistor is used as the output terminal of the follower unit, and the positive and negative poles of the power supply terminal of the second operational amplifier are used as the positive and negative poles of the power supply terminal of the follower unit.

[0171] like Figure 5 As shown, in the first follower unit: the positive input terminal of the second operational amplifier U28A is used as the input terminal of the first follower unit and is connected to the output terminal of the in-phase adder. The negative input terminal of the second operational amplifier U28A is respectively connected to the output terminal of the second operational amplifier U28A, one end of the fifth resistor R302 and one end of the sixth resistor R303, and the other end of the sixth resistor R303 is grounded. The other end of the fifth resistor R302 serves as the output terminal of the first follower unit. The positive and negative poles of the power supply terminal of the second operational amplifier U28A serve as the positive and negative poles of the power supply terminal of the first follower unit. The positive pole of the power supply terminal of the second operational amplifier U28A is connected to the VDD_30V power supply; the negative pole of the power supply terminal of the second operational amplifier U28A is connected to the VSS_-5V power supply.

[0172] In the second follower unit: the positive input terminal of the second operational amplifier U28B is used as the input terminal of the second follower unit and is connected to the output terminal of the in-phase adder. The negative input terminal of the second operational amplifier U28B is respectively connected to the output terminal of the second operational amplifier U28B, one end of the fifth resistor R304 and one end of the sixth resistor R305, and the other end of the sixth resistor R305 is grounded. The other end of the fifth resistor R305 serves as the output terminal of the second follower unit. The positive and negative poles of the power supply terminal of the second operational amplifier U28B serve as the positive and negative poles of the power supply terminal of the second follower unit.

[0173] The second operational amplifier can be implemented using an OPA2196 chip.

[0174] The bias amplification voltage is isolated from the subsequent circuit through the first follower unit and the second follower unit to ensure the purity and stability of the signal.

[0175] The first follower unit and the second follower unit accurately isolate and convert the voltage HV_OUT output by the in-phase adder into two independent output voltages: HV_OPA1 and HV_OPA2. This conversion process not only maintains the integrity of the signal, but also significantly improves the efficiency and speed of signal processing through dual-channel parallel processing.

[0176] Optional, such as Figure 6 As shown, N is 16; the OPA module has 2 output terminals.

[0177] The input ends of 8 high-voltage units HV unit are connected to one output end of the OPA module; the input ends of the other 8 high-voltage units HV unit are connected to another output end of the OPA module.

[0178] Figure 6 In the figure, VISM / MVM mode is: two modes used by the customer end, that is, 16 high-voltage units, which can be used by users to test the VSIM and MVM functions; VSIM means Voltage source current measure, which is the current measurement mode, specifically the test machine measures the current by giving voltage; MVM means measure voltage mode, which is the voltage measurement mode, specifically the test machine measures the voltage by giving voltage, or it can be an external voltage measurement; Probercard side (example) means: the external connection side of the test machine. The externally connected component is the prober card.

[0179] Specifically, the high-voltage units HVunit0-unit7 are connected to the first output terminal (HV_OPA1) of the OPA module; the high-voltage units HV unit8-unit16 are connected to the second output terminal (HV_OPA2) of the OPA module. The current of each high-voltage unit HVunit can be 2mA. HV_OPA1 and HV_OPA2 are the output setting values ​​of the OPA module.

[0180] Each high-voltage unit HV unit corresponds to a channel, and each high-voltage unit HV unit is built with op amps and discrete components, without expensive integrated chips, and has lower costs. Compared with T5830, every 2 units are 1 MC, and each MC can be independently configured as VSIM or MVM mode. This application can achieve that each high-voltage unit HV unit can independently set VSIM or MVM mode.

[0181] Each group of 8 channels is provided with a set voltage by an op amp in the OPA module, which can meet the output setting current required for 64 channels for Datong measurement scheme. Two op amps provide input setting voltage for 128 channels.

[0182] Due to the needs of Datong measurement, the single board area size is also limited. Multiplexers and analog switches can be used to reduce the size, and then each high-voltage unit HV unit can be integrated. At the same time, two high-voltage units HV units (such as Figure 7 as shown) are integrated together; Figure 7In the invention, two high voltage units HV unit and a high voltage channel selection circuit are integrated together, and the integrated unit is named VMON CBB; wherein the high voltage channel selection circuit can adopt a corresponding chip, and thus one chip can realize channel selection of two high voltage units HV unit.

[0183] Figure 7 Middle: The VDD_30V pin of VMON CBB is connected to the VDD_30V power supply; the VL_5V pin of VMON CBB is connected to the VCC_5V power supply; the VSS_-5V pin of VMON CBB is connected to the VSS_-5V power supply; and the GND pin of VMON CBB is connected to the ground GND.

[0184] For PER: the power supply part provides power for op amps and switching devices; the HV_IN pin of VMON CBB receives the output voltage of the OPA module ( Figure 7 Take VMON CBB as an example for demonstration).

[0185] For the DUT SEL part: channel selection input, the independent enable of DUT0 and DUT1 can be configured; DUTa_b_SW_IN1, DUTa_b_SW_IN2, DUTa_b_SW_IN3, and DUTa_b_SW_IN4 of VMON CBB receive the signal DUT0_1_SW_IN1, the signal DUT0_1_SW_IN2, the signal DUT0_1_SW_IN3, and the signal DUT0_1_SW_IN4 through the corresponding resistors (R388, R389, R390, and R391), respectively.

[0186] For DUT0: DUTa_SW_IN1 pin, DUTa_SW_IN2 pin, DUTa_SW_IN3 pin, DUTa_SW_IN4 pin receive signals DUT0_SW_IN1, DUT0_SW_IN2, DUT0_SW_IN3, DUT0_SW_IN4 through corresponding resistors (R392, R393, R394, R395) respectively. DUTa_RANGE_SEL pin receives signal DUT0_RANGE_SEL through resistor R398; VSIM_Ha pin is used as the positive current sampling terminal (VSIM0_H0) of high voltage unit HV unit0; VSIM_La pin is used as the negative current sampling terminal (VSIM0_L0) of high voltage unit HV unit0; MVM_a pin is used as the voltage sampling terminal (MVM0_V0) of high voltage unit HVunit0. The OUTa_A pin is connected to TP1; the OUTa_B pin is connected to TP2; the HV_POGO_a pin serves as the output end (HV_POGO_0) of the high-voltage unit HVunit0; that is, it includes the switch control of DUT0, range selection, VSIM0 interface output, MVM0 interface output, OUT0 test point and DUT0 connection HV_POGO_0.

[0187] For DUT1: DUTb_SW_IN1 pin, DUTb_SW_IN2 pin, DUTb_SW_IN3 pin, DUTb_SW_IN4 pin receive signals DUT1_SW_IN1, DUT1_SW_IN2, DUT1_SW_IN3, and DUT1_SW_IN4 through corresponding resistors (R403, R404, R405, and R406), respectively. DUTb_RANGE_SEL pin receives signal DUT1_RANGE_SEL through resistor R415; VSIM_Hb pin serves as the positive current sampling terminal (VSIM0_H1) of the high-voltage unit HV unit1; VSIM_Lb pin serves as the negative current sampling terminal (VSIM0_L1) of the high-voltage unit HVunit1; MVM_b pin serves as the voltage sampling terminal (MVM0_V1) of the high-voltage unit HVunit1. The OUTb_A pin is connected to TP3; the OUTb_B pin is connected to TP4; the HV_POGO_b pin serves as the output end (HV_POGO_1) of the high-voltage unit HVunit1; that is, it includes the switch control of DUT1, range selection, VSIM1 interface output, MVM1 interface output, OUT1 test point and DUT1 connected to HV_POGO_1.

[0188] It should be noted that HVUnit1 = DUT0, HVUnit2 = DUT1. HVUnit1 and HVUnit2 are both high-voltage units HVunit; OR / 0402 are both specific parameters of resistors.

[0189] like Figure 8 As shown, it shows the expanded diagram of VMON CBB; wherein HVOUTa and HVOUTb are both high-voltage units HVunit, POGO_SW is a channel selection chip (including two high-voltage channel selection circuits); two high-voltage units HVunit multiplex one channel selection chip; that is, VMON CBB consists of 2 HVOUT CBBs and 1 POGO SW.

[0190] In HVOUTa: HV_IN pin receives the output signal of the OPA module; SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTa_SW_IN1, DUTa_SW_IN2, DUTa_SW_IN3, and DUTa_SW_IN4 pins respectively; Set_Range pin is connected to DUTa_RANGE_SEL pin; VSS pin is connected to VSS_-5V pin; VDD pin is connected to VDD_30V pin; GDN pin is grounded; VSIM_H pin is connected to VSIM_Ha pin; VSIM_L pin is connected to VSIM_La pin; OUT_A pin is connected to OUTa_A pin; OUT_B pin is connected to OUTa_B pin; MVM pin is connected to MVM_a pin.

[0191] In HVOUTb: HV_IN pin receives the output signal of the OPA module; SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTb_SW_IN1 pin, DUTb_SW_IN2 pin, DUTb_SW_IN3 pin, and DUTb_SW_IN4 pin respectively; Set_Range pin is connected to DUTb_RANGE_SEL pin; VSS pin is connected to VSS_-5V pin; VDD pin is connected to VDD_30V pin; GDN pin is grounded; VSIM_H pin is connected to VSIM_Hb pin; VSIM_L pin is connected to VSIM_Lb pin; OUT_A pin is connected to OUTb_A pin; OUT_B pin is connected to OUTb_B pin; MVM pin is connected to MVM_b pin.

[0192] In POGO_SW: SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTa_b_SW_IN1, DUTa_b_SW_IN2, DUTa_b_SW_IN3, and DUTa_b_SW_IN4 pins respectively; VSS pin is connected to VSS_-5V pin; VDD pin is connected to VDD_30V pin; GDN pin is grounded; VL pin is connected to VL_5V pin; HV_DUT1 pin is connected to HV_POGO_a_ pin; HV_DUT2 pin is connected to HV_POGO_b_ pin.

[0193] The DUTA pin of HVOUTa is connected to the DUTB_1 pin in POGO_SW; the DUTB pin of HVOUTa is connected to the DUTA_1 pin in POGO_SW; the DUTA pin of HVOUTb is connected to the DUTA_2 pin in POGO_SW; the DUTB pin of HVOUTb is connected to the DUTB_2 pin in POGO_SW.

[0194] Optionally, a high voltage unit HV unit includes: an HV operational amplifier circuit, a current sampling circuit and a switch unit.

[0195] See also Fig. 9 The HV operational amplifier circuit includes: a high voltage operational amplifier HV, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9. The current sampling circuit includes: a tenth resistor R10 and a first switch SPST1. The switch unit includes: a second switch SPST2 and a third switch SPST3; the switch unit may also include: a fourth switch SPST4 and a fifth switch SPST5.

[0196] The non-inverting input terminal of the high-voltage operational amplifier HV serves as the input terminal of the high-voltage unit HV unit, and receives the voltage signal HV_OPA1 or HV_OPA2 output by the OPA module.

[0197] The negative input terminal of the high-voltage operational amplifier HV is connected to one end of the seventh resistor R7.

[0198] The output end of the high voltage operational amplifier HV is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9 respectively, and the connection point is used as the positive current sampling terminal of the high voltage unit HV unit and is connected to an input end of the VSIM channel selection circuit.

[0199] The other end of the ninth resistor R9 is respectively connected to one end of the third switch SPST3, one end of the eighth resistor R8 and one end of the first switch SPST1, and the connection point serves as the negative current sampling terminal of the high voltage unit HV unit and is connected to another input end of the VSIM channel selection circuit.

[0200] It should be noted that the positive and negative electrodes of the current sampling terminal of the high voltage unit HV unit can also be connected to the VSIM channel selection circuit through a buffer respectively.

[0201] The other end of the seventh resistor R7 is connected to the other end of the eighth resistor R8 and one end of the second switch SPST2 respectively, and the connection point serves as a voltage sampling terminal (MVM) of the high voltage unit HV unit and is connected to the input terminal of the MVM channel selection circuit.

[0202] The voltage sampling terminal can measure the output voltage of the high voltage unit HV unit, and can also be used to measure the high voltage value of the DUT at the output terminal HV_POGO of the high voltage channel selection circuit. The voltage sampling terminal can be connected to the input terminal of the MVM channel selection circuit after a buffer is used to isolate the voltage.

[0203] The other end of the first switch SPST1 is connected to the other end of the tenth resistor R10 .

[0204] The other end of the second switch SPST2 is connected to one end of the fourth switch SPST4 , and the connection point serves as a first output end of the high-voltage unit HVunit and is connected to an input end of the high-voltage channel selection circuit.

[0205] The other end of the fourth switch SPST4 serves as an OUTA interface of the high voltage unit HV unit.

[0206] The other end of the third switch SPST3 is connected to one end of the fifth switch SPST5 , and the connection point serves as a second output end of the high-voltage unit HVunit and is connected to another input end of the high-voltage channel selection circuit.

[0207] The other end of the fifth switch SPST5 serves as an OUTB interface of the high voltage unit HV unit.

[0208] The OUTA interface and OUTB interface are reserved interfaces and can be used to measure the voltage value across the feedback resistor and to measure the feedback current.

[0209] That is, by turning off and on the first switch SPST1 in the pin configuration control of the controller FPGA, the ninth resistor R9 and the tenth resistor R10 are connected in parallel and disconnected, thereby changing the output resistance value of the HV operational amplifier to change the output current range.

[0210] By controlling the on and off of each switch in the switch unit, various modes of the high voltage unit HV unit are switched.

[0211] Optionally, the high-voltage channel selection circuit includes: a first channel switch and a second channel switch.

[0212] One end of the first channel switch is connected to a first output end of the high voltage unit HV unit.

[0213] One end of the second channel switch is connected to the second output end of the high voltage unit HV unit.

[0214] The other end of the first channel switch is connected to the other end of the second channel switch, and the connection point serves as an output end of the high-voltage channel selection circuit.

[0215] It should be noted that the high voltage selection circuits corresponding to the two high voltage units HVunit may be integrated together.

[0216] like Fig.10 As shown:

[0217] One end of the first channel switch U72B is connected to the first output end of the high voltage unit HV unit1, and one end of the first channel switch U72B receives the DUTA1 signal.

[0218] One end of the second channel switch U72E is connected to the second output end of the high voltage unit HV unit1, and one end of the second channel switch receives the DUTB1 signal.

[0219] The other end of the first channel switch U72B is connected to the other end of the second channel switch U72E, and the connection point serves as the output end of the first high-voltage channel selection circuit, for example, outputting the HV_DUT1 signal.

[0220] One end of the first channel switch U72C is connected to the first output end of the high voltage unit HV unit2, and one end of the first channel switch U72C receives the DUTA2 signal.

[0221] One end of the second channel switch U72D is connected to the second output end of the high voltage unit HV unit2, and one end of the second channel switch receives the DUTB2 signal.

[0222] The other end of the first channel switch U72C is connected to the other end of the second channel switch U72D, and the connection point serves as the output end of the second high-voltage channel selection circuit, for example, outputting the HV_DUT2 signal.

[0223] By controlling the switch, the connection between DUTA1 or DUTB1 and HV_DUT1 can be established. Similarly, the connection between DUTA2 or DUTB2 and HV_DUT2 can be established.

[0224] like Fig.11 As shown, it shows the connection relationship between 1 ADC channel selection circuit and 4 RC low-pass filter circuits, 2 VSIM channel selection circuits and 1 MVM channel selection circuit.

[0225] The details are as follows:

[0226] 2 VSIM channel selection circuits:

[0227] The left side of the VSIM channel selection circuit is the input signal, which is the control signal from the FPGA, including enable EN and channel control A0, A1, A2, etc. There are also voltages VSIM_H0 / 15 and VSIM_L0 / 15 across the sampling resistors from the 16 HV units.

[0228] The right side of the VSIM channel selection circuit is the output signal, and the output terminals VSIM_OUT_1 and VSIM_OUT_2 of the two VSIM channel selection circuits are respectively connected to the ADC channel selection circuit.

[0229] In other words, the VSIM channel selection module is used to complete the voltage-current conversion across the current sampling resistor and implement 16-to-2 channel selection. The signal definition is as follows:

[0230] MUX enable: EN. MUX channel control: A0, A1, A2. MUX channel 16 select 2: S1-8A corresponds to the sampling resistor L-end voltage sampling. S1-8B corresponds to the sampling resistor H-end voltage sampling. VSIM output: The differential voltage passes through the 16:2MUX to select 1 of the 8 channels for VSIM function sampling. The current value is converted into a voltage value through the current detection amplifier and output through VSIM_OUT1 and VSIM_OUT_2.

[0231] 1 MVM channel selection circuit:

[0232] The left side of the MVM channel selection circuit is the input signal, which is the control signal from the FPGA, including enable EN and channel control A0, A1, A2, etc. There are also output voltage sampling signals MVM0_V0-7 and MVM1_V8-15 from the 16 HV units.

[0233] The right side of the MVM channel selection circuit is the output signal, and the output terminals MVM_OUT1 and MVM_OUT2 of the MVM channel selection circuit are respectively connected to the ADC channel selection circuit.

[0234] In other words, the MVM channel selection circuit is used to complete the high-voltage reduction bias of the HV output voltage / DUT sampling voltage and realize the 16-to-2 channel selection. The signal definition is as follows:

[0235] MUX enable: EN. MUX channel control: A0a, A1a, A2a correspond to DUTa, A0b, A1b, A2b correspond to DUTb. MUX channel 16 select 2: S1-8a corresponds to DUT 0-7 output voltage sampling. S1-8b corresponds to DUT 8-15 output voltage sampling. MVM output: DUT output voltage is 2 8:1 MUX, 16 channels select 2, MVM function sampling, and output through MVM_OUT after voltage bias amplification.

[0236] 1 HV_ADC channel selection circuit + 4 RC low-pass filters:

[0237] On the left side of the ADC channel selection circuit are the input signals from the VSIM channel selection circuit and the MVM channel selection circuit, a total of 4 input signals, as well as the MUX control signals from the FPGA, including channel control IN1, IN2, IN3 and IN4.

[0238] On the right side of the ADC channel selection circuit are 4 switch path output signals, namely VSIM_MUX_OUT1, VSIM_MUX_OUT2, MVM_MUX_OUT1, and MVM_MUX_OUT2. These 4 signals pass through their corresponding RC low-pass filter circuits and enter the channels AIN0, AIN7, BIN0, and BIN7 of the ADC module. In other words, the 4 RC low-pass filter circuits correspond one-to-one to the four output ends of the ADC channel selection circuit; each RC low-pass filter circuit is arranged between the corresponding output end of the ADC channel selection circuit and the ADC module. The ADC module can have multiple channels, such as 16; Fig.11 As shown, only 4 channels are available.

[0239] That is to say, a 4-channel MUX is set in the ADC channel selection circuit to realize the switch control of 2 HV_VSIM channels and 2 HV_MVM channels.

[0240] The analog voltage after SIM and MVM channel selection enters the ADC sampling channel after filtering.

[0241] Optional, such as Fig.12 As shown, the VSIM channel selection circuit includes: two first multiplexing circuits; the first multiplexing circuit includes: a first multiplexing chip U77, a fifth MUX operational amplifier U76A, a sixth MUX operational amplifier U76B, a gain chip GAIN and four multiplexing resistors (including Fig.12The multiplexed resistor R742 is a 10k / 0402 resistor; the multiplexed resistor R741 is a 33R / 0402 resistor; the multiplexed resistor R740 is a 10k / 0402 resistor; and the multiplexed resistor R739 is a 33R / 0402 resistor.

[0242] The VDD pin of the first multiplexing chip U77 is connected to the positive power supply VDD; the VSS pin thereof is connected to the negative power supply VSS. The EPAD pin and the GND pin thereof are both connected to the ground GND. The first multiplexing chip U77 may adopt the ADG5207 chip.

[0243] The non-inverting input terminal +INA of the fifth MUX operational amplifier U76A is connected to the DA pin of the first multiplexing chip U77.

[0244] The negative input terminal -INA of the fifth MUX operational amplifier U76A is connected to the output terminal OUTA of the fifth MUX operational amplifier U76A, one end of the first multiplexing resistor R739, and one end of the second multiplexing resistor R740.

[0245] The non-inverting input terminal +INB of the sixth MUX operational amplifier U76B is connected to the DB pin of the first multiplexing chip U77.

[0246] The other end of the first multiplexing resistor R739 is connected to the -INA pin of the gain chip GAIN.

[0247] The negative input terminal -INB of the sixth MUX operational amplifier U76B is connected to the output terminal OUTB of the sixth MUX operational amplifier U76B, one end of the third multiplexing resistor R741, and one end of the fourth multiplexing resistor R742.

[0248] The other end of the third multiplexing resistor R741 is connected to the +INA pin of the gain chip GAIN.

[0249] The other end of the second multiplexing resistor R740, the other end of the fourth multiplexing resistor R742, and the REF pin of the gain chip GAIN are all grounded.

[0250] The positive power supply terminal of the fifth MUX operational amplifier U76A, the positive power supply terminal of the sixth MUX operational amplifier U76B, and the positive power supply terminal V+ of the gain chip GAIN are connected to the positive power supply VDD.

[0251] The negative power supply terminal of the fifth MUX operational amplifier U76A, the negative power supply terminal of the sixth MUX operational amplifier U76B, and the negative power supply terminal V- of the gain chip GAIN are connected to the negative power supply VSS.

[0252] The fifth MUX operational amplifier U76A and the sixth MUX operational amplifier U76B can use the OPA2196 chip, and of course can also be other chips, which will not be described here one by one.

[0253] The OUT pin of the gain chip GAIN is connected to the anode of the first diode D10, and the connection point serves as the output end of the first multiplexing circuit. The gain chip GAIN can use a gain of 10, and of course, other gains, which will not be described here one by one.

[0254] The input terminal of the first multiplexing chip U77 (such as Fig.12 S1B-S8B, and S1A-S8A) shown as the input terminal of the first multiplexing circuit.

[0255] The EN pin of the first multiplexing chip U77 receives the EN signal; its A0, A1 and A2 pins receive A0, A1 and A2 signals respectively; and its NC1-NC7 are all pins.

[0256] In the gain chip GAIN, +INB, +INC, -INB, -INC and / SHDN are all pins. The gain chip GAIN can adopt the LT1997-1 chip.

[0257] The cathode of the first diode D10 receives the first clamping voltage V_CLAMP_VSIM; the first clamping voltage V_CLAMP_VSIM may be a 15V voltage.

[0258] The first diode D10 may be a diode of DFLS140-7.

[0259] It should be noted that the first multiplexing chip U77 is a 16-to-2 multiplexer, which isolates the voltage value across the current feedback resistor through DA and DB through the U76 voltage follower (including U76A and U76B), and then inputs it to the U78 current detection amplifier to achieve current-voltage conversion. The amplifier has an amplification factor of 10, and the voltage range across the feedback resistor is I*R, about -0.5V to 1V, and the voltage range after amplification is -5V to 10V. The actual ADC sampling range meets -12V to 12V.

[0260] Optionally, the MVM channel selection circuit includes: two second multiplexing circuits, and the second multiplexing circuit includes: a second multiplexing chip and a seventh MUX operational amplifier.

[0261] The input end of the second multiplexing chip serves as the input end of the second multiplexing circuit.

[0262] The D pin of the second multiplexing chip is connected to one end of the fifth multiplexing resistor.

[0263] The other end of the fifth multiplexing resistor is respectively connected to the non-inverting input end of the seventh MUX operational amplifier and one end of the sixth multiplexing resistor, and the other end of the sixth multiplexing resistor is grounded.

[0264] The negative phase input terminal of the seventh MUX operational amplifier is respectively connected to one end of the seventh multiplexing resistor and one end of the eighth multiplexing resistor.

[0265] The other end of the seventh multiplexing resistor receives a bias voltage.

[0266] The output end of the seventh MUX operational amplifier is connected to the other end of the eighth multiplexing resistor and the anode of the second diode respectively, and the connection point serves as the output end of the second multiplexing circuit.

[0267] The cathode of the second diode receives the second clamping voltage V_CLAMP_MVM; the second clamping voltage V_CLAMP_MVM may be a 15V voltage.

[0268] like Fig.13 As shown, in the first second multiplexing circuit: the input end of the second multiplexing chip U88 is used as the input end of the first second multiplexing circuit. The D pin of the second multiplexing chip U88 is connected to one end of the fifth multiplexing resistor R753. The other end of the fifth multiplexing resistor R753 is respectively connected to the positive phase input end of the seventh MUX operational amplifier U85A and one end of the sixth multiplexing resistor R754, and the other end of the sixth multiplexing resistor R754 is grounded. The negative phase input end of the seventh MUX operational amplifier U85A is respectively connected to one end of the seventh multiplexing resistor R751 and one end of the eighth multiplexing resistor R752. The other end of the seventh multiplexing resistor R751 receives the bias voltage VBIAS. The output end of the seventh MUX operational amplifier U85A is respectively connected to the other end of the eighth multiplexing resistor R752 and the anode of the second diode D12, and the connection point is used as the output end MVM_OUTa of the first second multiplexing circuit. The cathode of the second diode D12 receives the second clamping voltage V_CLAMP_MVM.

[0269] In the second second multiplexing circuit: the input end of the second multiplexing chip U87 is used as the input end of the second second multiplexing circuit. The D pin of the second multiplexing chip U87 is connected to one end of the fifth multiplexing resistor R757. The other end of the fifth multiplexing resistor R757 is respectively connected to the positive phase input end of the seventh MUX operational amplifier U85B and one end of the sixth multiplexing resistor R758, and the other end of the sixth multiplexing resistor R758 is grounded. The negative phase input end of the seventh MUX operational amplifier U85B is respectively connected to one end of the seventh multiplexing resistor R755 and one end of the eighth multiplexing resistor R756. The other end of the seventh multiplexing resistor R755 receives the bias voltage VBIAS. The output end of the seventh MUX operational amplifier U85B is respectively connected to the other end of the eighth multiplexing resistor R756 and the anode of the second diode D13, and the connection point is used as the output end MVM_OUTb of the first second multiplexing circuit. The cathode of the second diode D13 receives the second clamping voltage V_CLAMP_MVM.

[0270] The first multiplexing chip U86 and the second multiplexing chip U87 use the ADG5408 chip. The operational amplifier U85B / A both use the OPA2196 chip.

[0271] Resistors R751, R753, R755 and R757 are all 30k / 0603 resistors; resistors R752, R754, R756 and R758 are all 7.5k / 0603 resistors.

[0272] Figure 1-Figure 15 In the figure: +INA and +INB are the non-inverting input terminals of the operational amplifier; -INA and -INB are the non-inverting input terminals of the operational amplifier; OUTA and OUTB are the output terminals of the operational amplifier.

[0273] S1-S8, EN, A0, A1, A2, VDD, VSS, and GND in U87 and U88 respectively receive corresponding signals, such as S1a-S8a signal / S1b-S8b signal, ENa / b signal, A0a-A2a signal / A0b-A2b signal, VDD signal, VSS signal, and GND signal.

[0274] The second multiplexer chip U86 is an 8-to-1 multiplexer. The voltage is biased and amplified by a common-mode adder. The bias voltage VBIAS = 10V. The formula is as follows:

[0275] V out =(V in -10V) / 4;

[0276] The MVM sampling voltage range is -5V to 30V, and after amplification and biasing, it is -1.25V to 5V. The maximum sampling voltage range of the ADC is -12V to 12V.

[0277] Optional, such as Fig.14 As shown, the ADC channel selection circuit includes: four MUX switches, four MUX operational amplifiers, and four MUX resistors.

[0278] One end of the first MUX switch U83B serves as a first input end of the ADC channel selection circuit; the other end of the first MUX switch U83B is respectively connected to one end of the first MUX resistor R747 and the positive input end of the first MUX operational amplifier U82A; the other end of the first MUX resistor R747 is grounded; the positive pole of the power supply end of the first MUX operational amplifier U82A is connected to the positive power supply VDD; the negative pole of the power supply end of the first MUX operational amplifier U82A is connected to the negative power supply VSS; the output end of the first MUX operational amplifier U82A serves as the first output end VSIM_MUX_OUT1 of the ADC channel selection circuit.

[0279] One end of the second MUX switch U83C serves as another first input end of the ADC channel selection circuit; the other end of the second MUX switch U83C is respectively connected to one end of the second MUX resistor R748 and the positive input end of the second MUX operational amplifier U82B; the other end of the second MUX resistor R748 is grounded; the output end of the second MUX operational amplifier U82B serves as the second output end VSIM_MUX_OUT2 of the ADC channel selection circuit.

[0280] One end of the third MUX switch U83D serves as a second input end of the ADC channel selection circuit; the other end of the third MUX switch U83D is respectively connected to one end of the third MUX resistor R749 and the positive input end of the third MUX operational amplifier U84A; the other end of the third MUX resistor R749 is grounded; the positive pole of the power supply end of the third MUX operational amplifier U84A is connected to the positive power supply VDD; the negative pole of the power supply end of the third MUX operational amplifier U84A is connected to the negative power supply VSS; the output end of the third MUX operational amplifier U84A serves as the third output end MVM_MUX_OUT3 of the ADC channel selection circuit.

[0281] One end of the fourth MUX switch U83E serves as another second input end of the ADC channel selection circuit; the other end of the fourth MUX switch U83E is respectively connected to one end of the fourth MUX resistor R750 and the positive input end of the fourth MUX operational amplifier U84B; the other end of the fourth MUX resistor R750 is grounded; the output end of the fourth MUX operational amplifier U84B serves as the fourth output end MVM_MUX_OUT4 of the ADC channel selection circuit.

[0282] The MUX switch U83B\C\D\E is a 4-way analog switch that can be controlled by FPGA to switch on and off the sampling channels of VSIM and MVM. Each channel is independently controlled. After passing through a first-stage op amp, the voltage follower performs isolation protection for the front and rear stages.

[0283] The ADC channel selection circuit may also include: a MUX switch U83A; its IN1-IN4 pins receive SW_IN1-SW_IN4 signals respectively; its VL, VDD, VSS, and GND receive VL signals, VDD signals, VSS signals, and GND signals respectively.

[0284] Resistors R747, R748, R749, and R750 are all 10m / 0603 resistors. MUX switches U83A, U83B, U83C, U83, and U83E are all ADG411 switches. Operational amplifiers U84A, U84B, U84C, and U84D all use OPA2196 chips.

[0285] like Fig.15 As shown in FIG. 1 , a circuit diagram of an ADC module is shown. The ADC module includes an ADC chip.

[0286] The ADC chip may adopt a high-precision 16-bit, 16-channel ADC chip, including 8 A channels and 8 B channels.

[0287] Power supply of ADC chip: AVDD analog voltage uses VCC_5V, DVDD digital voltage uses VCC_3V3. REFIO is the ADC external reference source voltage, which is VCC_2V5.

[0288] Input channels of ADC chip: 16 channels in total. This application uses 4 channels for VSIM and MVM. Fig.11 and Figure 1 AIN0, AIN7, BIN0 and BIN7 shown.

[0289] 128DUTs multi-channel solution: Through MUX multiplexing and switching of switches, 16 DUTs can share one ADC channel in a single mode, thus realizing a multi-channel solution of 16*8=128DUTs.

[0290] ADC chip configuration: Use the GPIO pins of the FPGA to configure the registers of various ADC functions.

[0291] Communication of ADC chip: After the ADC configuration is selected, it communicates with the FPGA through the hardware serial interface SPI, and additional software serial parallel interface and hardware parallel interface are reserved.

[0292] In this embodiment, each high voltage unit is independent, and the application can meet the needs of 128 high voltage output channels, and the remaining ADC pins can be used up to the peak value. The device multiplexing switch control of each 8 channels constitutes a minimum subset, which can be configured according to the needs of the same measurement. By increasing the number of ADC channels, the final same measurement number can be larger, depending on the board size limit.

[0293] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0294] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0295] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high voltage power supply circuit for a test device, characterized in that: The high voltage power supply circuit is independent of the test equipment; The high-voltage power supply circuit includes: a controller, a DAC module, an OPA module, an ADC module and M high-voltage output circuits; the high-voltage output circuit includes: a multiplexing selection circuit, N high-voltage channel selection circuits and N high-voltage units, and the multiplexing selection circuit includes: an ADC channel selection circuit, a VSIM channel selection circuit and an MVM channel selection circuit; M is a positive integer, and N is an integer greater than 1; wherein: The N high-voltage channel selection circuits correspond to the N high-voltage units in a one-to-one manner; The first end of the controller is connected to one end of the high-voltage channel selection circuit through the DAC module, the OPA module, and the high-voltage unit in sequence; The other end of the high-voltage channel selection circuit serves as an output end of the high-voltage power supply circuit and is connected to the device under test; The second end of the controller is connected to the output end of the ADC module; The four input terminals of the ADC module correspond one to one with the four output terminals of the ADC channel selection circuit; each input terminal of the ADC module is correspondingly connected with each output terminal of the ADC channel selection module; The two first input terminals of the ADC channel selection module correspond one to one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is correspondingly connected with each output terminal of the VSIM channel selection circuit; The two second input terminals of the ADC channel selection module correspond one to one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is correspondingly connected with each output terminal of the MVM channel selection circuit; The two input terminals of the VSIM channel selection circuit are connected to the positive and negative electrodes of the current sampling terminal in the high voltage unit correspondingly; An input end of the MVM channel selection circuit is connected to a voltage sampling end of the high voltage unit; The ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high-voltage unit and the high-voltage channel selection circuit are all controlled by the controller.

2. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The OPA module includes: an in-phase adder and a follower; The input end of the in-phase adder is connected to the output end of the DAC module; The output end of the in-phase adder is connected to the input end of the follower; The output end of the follower serves as the output end of the OPA module; The positive pole of the power supply end of the in-phase adder and the positive pole of the power supply end of the follower are both connected to a 30V power supply; The negative electrode of the power supply end of the in-phase adder and the negative electrode of the power supply end of the follower are both connected to a -5V power supply.

3. The high voltage power supply circuit of the test equipment according to claim 2, characterized in that: The in-phase adder comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier and a first capacitor; One end of the third resistor serves as an input end of the in-phase adder; The non-inverting input terminal of the first operational amplifier is respectively connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor; The negative phase input terminal of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor respectively; The output end of the first operational amplifier is connected to the other end of the second resistor, and the connection point serves as the output end of the in-phase adder; The positive and negative electrodes of the power supply terminal of the first operational amplifier serve as the positive and negative electrodes of the power supply terminal of the in-phase adder respectively; The other end of the fourth resistor is connected to a reference power supply; the other end of the first capacitor and the other end of the first resistor are grounded.

4. The high voltage power supply circuit of the test equipment according to claim 2, characterized in that: The follower comprises: two follower units; the connection point after the input ends of the two follower units are connected is used as the input end of the follower; the output ends of the two follower units are respectively used as the output ends of the follower; The follower unit includes: a second operational amplifier, a fifth resistor and a sixth resistor; The non-inverting input terminal of the second operational amplifier serves as the input terminal of the follower unit; The negative input terminal of the second operational amplifier is respectively connected to the output terminal of the second operational amplifier, one end of the fifth resistor and one end of the sixth resistor; The other end of the sixth resistor is grounded; The other end of the fifth resistor serves as the output end of the follower unit; The positive and negative electrodes of the power supply terminals of the second operational amplifier serve as the positive and negative electrodes of the power supply terminals of the follower unit.

5. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: N is 16; the OPA module has 2 output terminals; wherein the input ends of eight of the high voltage units are connected to an output end of the OPA module; The input ends of the other eight high-voltage units are connected to another output end of the OPA module.

6. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The high voltage unit comprises: an HV operational amplifier circuit, a current sampling circuit and a switch unit; the HV operational amplifier circuit comprises: a high voltage operational amplifier, a seventh resistor, an eighth resistor and a ninth resistor; the current sampling circuit comprises: a tenth resistor and a first switch; the switch unit comprises: a second switch and a third switch; The non-inverting input terminal of the high-voltage operational amplifier serves as the input terminal of the high-voltage unit; The negative input terminal of the high-voltage operational amplifier is connected to one end of the seventh resistor; The output end of the high-voltage operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and the connection point serves as the positive electrode of the current sampling end of the high-voltage unit; The other end of the ninth resistor is respectively connected to one end of the third switch, one end of the eighth resistor and one end of the first switch, and the connection point serves as the negative electrode of the current sampling terminal of the high voltage unit; The other end of the seventh resistor is connected to the other end of the eighth resistor and one end of the second switch respectively, and the connection point serves as a voltage sampling end of the high-voltage unit; The other end of the first switch is connected to the other end of the tenth resistor; The other end of the second switch serves as the first output end of the high voltage unit; The other end of the third switch serves as the second output end of the high voltage unit.

7. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The high voltage channel selection circuit comprises: a first channel switch and a second channel switch; One end of the first channel switch is connected to the first output end of the high voltage unit; One end of the second channel switch is connected to the second output end of the high voltage unit; The other end of the first channel switch is connected to the other end of the second channel switch, and the connection point serves as the output end of the high-voltage channel selection circuit.

8. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The ADC channel selection circuit includes: four MUX switches, four MUX operational amplifiers, and four MUX resistors; One end of the first MUX switch serves as a first input end of the ADC channel selection circuit; the other end of the first MUX switch is respectively connected to one end of the first MUX resistor and the positive input end of the first MUX operational amplifier; the other end of the first MUX resistor is grounded; the positive electrode of the power supply end of the first MUX operational amplifier is connected to the positive power supply; the negative electrode of the power supply end of the first MUX operational amplifier is connected to the negative power supply; the output end of the first MUX operational amplifier serves as the first output end of the ADC channel selection circuit; One end of the second MUX switch serves as another first input end of the ADC channel selection circuit; the other end of the second MUX switch is respectively connected to one end of the second MUX resistor and the positive input end of the second MUX operational amplifier; the other end of the second MUX resistor is grounded; the output end of the second MUX operational amplifier serves as the second output end of the ADC channel selection circuit; One end of the third MUX switch serves as a second input end of the ADC channel selection circuit; the other end of the third MUX switch is respectively connected to one end of the third MUX resistor and the positive input end of the third MUX operational amplifier; the other end of the third MUX resistor is grounded; the positive electrode of the power supply end of the third MUX operational amplifier is connected to the positive power supply; the negative electrode of the power supply end of the third MUX operational amplifier is connected to the negative power supply; the output end of the third MUX operational amplifier serves as the third output end of the ADC channel selection circuit; One end of the fourth MUX switch serves as another second input end of the ADC channel selection circuit; the other end of the fourth MUX switch is respectively connected to one end of the fourth MUX resistor and the positive input end of the fourth MUX operational amplifier; the other end of the fourth MUX resistor is grounded; and the output end of the fourth MUX operational amplifier serves as the fourth output end of the ADC channel selection circuit.

9. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The VSIM channel selection circuit comprises: two first multiplexing circuits; the first multiplexing circuit comprises: a first multiplexing chip, a fifth MUX operational amplifier, a sixth MUX operational amplifier, a gain chip and four multiplexing resistors; The VDD pin of the first multiplexing chip is connected to a positive power supply; the VSS pin thereof is connected to a negative power supply; and the EPAD pin and the GND pin thereof are both grounded; The non-inverting input terminal of the fifth MUX operational amplifier is connected to the DA pin of the first multiplexing chip; The negative input terminal of the fifth MUX operational amplifier is connected to the output terminal of the fifth MUX operational amplifier, one end of the first multiplexing resistor, and one end of the second multiplexing resistor; The non-inverting input terminal of the sixth MUX operational amplifier is connected to the DB pin of the first multiplexing chip; The other end of the first multiplexed resistor is connected to the -INA pin of the gain chip; The negative input terminal of the sixth MUX operational amplifier is connected to the output terminal of the sixth MUX operational amplifier, one end of the third multiplexing resistor, and one end of the fourth multiplexing resistor; The other end of the third multiplexed resistor is connected to the +INA pin of the gain chip; The other end of the second multiplexed resistor, the other end of the fourth multiplexed resistor and the REF pin of the gain chip are all grounded; The positive electrode of the power supply end of the fifth MUX operational amplifier, the positive electrode of the power supply end of the sixth MUX operational amplifier, and the positive electrode of the power supply end of the gain chip are connected to a positive power supply; The negative electrode of the power supply terminal of the fifth MUX operational amplifier, the negative electrode of the power supply terminal of the sixth MUX operational amplifier, and the negative electrode of the power supply terminal of the gain chip are connected to a negative power supply; The OUT pin of the gain chip is connected to the anode of the first diode, and the connection point serves as the output end of the first multiplexing circuit; The input end of the first multiplexing chip serves as the input end of the first multiplexing circuit; A cathode of the first diode receives a first clamping voltage.

10. The high voltage power supply circuit of the test equipment according to claim 1, characterized in that: The MVM channel selection circuit comprises: two second multiplexing circuits, wherein the second multiplexing circuit comprises: a second multiplexing chip and a seventh MUX operational amplifier; The input end of the second multiplexing chip serves as the input end of the second multiplexing circuit; The D pin of the second multiplexing chip is connected to one end of the fifth multiplexing resistor; The other end of the fifth multiplexing resistor is respectively connected to the non-inverting input end of the seventh MUX operational amplifier and one end of the sixth multiplexing resistor, and the other end of the sixth multiplexing resistor is grounded; The negative phase input terminal of the seventh MUX operational amplifier is respectively connected to one end of the seventh multiplexing resistor and one end of the eighth multiplexing resistor; The other end of the seventh multiplexed resistor receives a bias voltage; The output end of the seventh MUX operational amplifier is respectively connected to the other end of the eighth multiplexing resistor and the anode of the second diode, and the connection point serves as the output end of the second multiplexing circuit; A cathode of the second diode receives a second clamping voltage.

Images