Face-to-face bonding heterogeneous integrated circuit layout method, system, equipment and medium

Abstract

The invention provides a face-to-face bonding heterogeneous integrated circuit layout method, a face-to-face bonding heterogeneous integrated circuit layout system, face-to-face bonding heterogeneous integrated circuit layout equipment and a medium, which are applied to the technical field of integrated circuit design automation (EDA). The method comprises the following steps: firstly, based on a connection netlist of multiple layers of bare chips, a bare chip layout rule and a unit bonding process library, carrying out layout position iteration on standard units in each layer of bare chips by utilizing a vectorized analysis layout device, and distributing initial solutions between positions of the units on the bare chips to which the units belong and face-to-face bonding positions required by a cross-bare chip wire net; and legalizing each layer of bare chip unit to obtain an optimal region of the bonding position, and traversing all units and the bonding position to obtain a final allocation result.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design automation (Electronics Design Automation, EDA), and in particular to a method, system, device and medium for face-to-face bonding of heterogeneous integrated circuit layout. Background Art

[0002] Three-dimensional integrated circuit (3D IC) refers to the integration of multiple chips by vertical stacking to form a system with higher performance, lower power consumption and smaller size. The emergence of 3D IC provides a new idea for breaking the limit of Moore's Law and continuing the development of the semiconductor industry. 3D technology can be used for heterogeneous integration to balance performance and cost issues. For example, the top die uses the latest node process to implement logic circuits to improve performance; the bottom die uses the previous generation node process to implement memory or analog circuits to reduce costs. With the development of hybrid bonding technology, face-to-face stacking can connect heterogeneous upper and lower dies at a higher density. This has become an important development direction for three-dimensional integrated circuits and urgently needs targeted layout algorithm support. Summary of the invention

[0003] In view of this, the embodiments of this specification provide a method, system, device and medium for face-to-face bonding of heterogeneous integrated circuit layout. For two given bare chips with different processes and the netlist divided into the bare chips, the positions of the units on their respective bare chips and the positions of the face-to-face bonding required for the cross-bare chip wire nets are allocated, so that under the conditions of no overlap between the units and the spacing constraints between the bonds, the total half-circle length of the connecting wire nets in the netlist is minimized, the interconnection delay loss is reduced, and the performance of the integrated circuit after physical realization is improved.

[0004] The embodiments of this specification provide the following technical solutions:

[0005] The embodiment of this specification provides a face-to-face bonding heterogeneous integrated circuit layout method, including:

[0006] Based on the connection netlist of multi-layer dies, die layout rules and cell bonding process library, a vectorized analytical layout is used to iterate the layout position of standard cells in each layer of dies. The density and line length parameters of different layers of dies in the layout are adjusted between iterations until the number of iterations reaches the upper limit or the area overlap rate is less than a given threshold, and an initial solution for the face-to-face bonding position of standard cells in each layer of dies is obtained;

[0007] The Abacus algorithm is used to solve the unit overlap in the initial solution, where the standard unit is adsorbed onto the row to obtain the legalization result of the standard unit;

[0008] Based on the legalization results of the standard cell, the optimal area of ​​the face-to-face bonding position is determined, and the Abacus algorithm is used to make the spacing between bonds meet the spacing constraint requirements, and the optimization results between the legalization of the standard cell and the face-to-face bonding position are obtained;

[0009] Based on the optimization results, the detailed layout of the standard cell is obtained by traversing and globally exchanging cells of the same size, and locally exchanging cells in adjacent rows and fine-tuning the position matching within the row until the number of iterations reaches the upper limit or the line length optimization amount is insufficient;

[0010] Based on the detailed layout of standard cells, the allocation results of the standard cells and the face-to-face bonding horizontal positions in each layer of the die are obtained.

[0011] Preferably, in performing layout position iteration on the standard cells in each layer of bare die using a vectorized analytical layout device, the objective function is modeled as a half-circle line length minimization optimization problem with density constraints, wherein the objective function is:

[0012]

[0013] Where, e is the wire net in netlist E; is the unit v in the network e i The corresponding pin position information, the relative position of the pin is equivalent to the center point of the bonding size information;

[0014] And, the constraint is relaxed into the objective function as a penalty term controlled by the density weight λ:

[0015]

[0016] is the smoothed line length of the units involved in the line network e connection, Objective function constructed for density penalty; two-dimensional term and Vectorize to match the number of independent layout layers stacked on the z-axis;

[0017]

[0018] in, Represents the normalization of the line length weight parameter; density penalty factor The elements in ,λ bottom is the density weight of the lower die, λ top is the density weight of the upper die, λ inter is the density weight between healthy individuals.

[0019] Preferably, the bonding unit v i The size is equivalent to Participate in the iterative calculation of density terms, where is the bonding unit v i The original size information of length and width, d inter is the minimum spacing constraint between bonds.

[0020] Preferably, during global layout calculation, the lower left corner coordinate of the bond modeling With and, after the global layout calculation is completed, the bonding modeling is restored to its original size, and the coordinate position information offset is restored accordingly.

[0021] Preferably, in determining the optimal region for the face-to-face bonding position, the boundary coordinates of the upper and lower bounding boxes in the same direction are sorted respectively, and the bounding region obtained from the boundary coordinates after removing the maximum and minimum values ​​is taken as the optimal region.

[0022] Preferably, after obtaining the optimal region, the bonds are first moved to the center point of the optimal region, and then the row-based Abacus algorithm is used to resolve the overlap of the positions or spacings between the bonds.

[0023] Preferably, when multiple bonds compete for the same optimal area, the bonds that are not in the optimal area are moved to the center of the optimal area, and the remaining bonds remain in place.

[0024] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0025] (1) Through vectorized parsing layout, the synchronous iteration of multi-layer cell layout solutions is achieved. Compared with commercial tools that lock the bond layer wire net allocation and model the layout within the die layer as independent problems, the solution space of this application is wider and the solution optimization process is more continuous and controllable;

[0026] (2) By independently controlling the adaptive update of weights in each layout layer, the aforementioned academic tools can be extended to support dies with different process heights by assuming the same die process height.

[0027] (3) Introducing bonding layer bonding modeling in the global layout to synchronize the movement of standard cells in the die, so that the minimum spacing constraint between bonds can be met while optimizing the cross-die wire network;

[0028] (4) Using row-aligned Abacus to legalize face-to-face bonding to meet spacing constraints, compared with the traditional matrix arrangement, the bonding position has higher freedom and less impact on displacement away from the optimal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is a schematic flow chart of the face-to-face bonding heterogeneous integrated circuit layout method in the present application;

[0031] Figure 2 It is a schematic diagram of the relationship between the optimal bonding placement area and the top / bottom unit bounding box of the wire mesh in this application;

[0032] Figure 3 It is a schematic diagram of the structure of the face-to-face bonding heterogeneous integrated circuit layout system in the present application;

[0033] Figure 4 It is a structural schematic diagram of an electronic device in this application. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0036] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0037] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0039] The process of existing commercial tools for three-dimensional integrated circuits (3D ICs) is usually as follows: first, matrix-based instantiation bonding is used on the layout to maximize utilization and meet the face-to-face bonding spacing constraints set due to the reduction of yield caused by reduced alignment and connection; then, after obtaining the divided netlist, instantiated fixed-position bonding is assigned to each cross-die network according to the timing plan.

[0040] However, the pre-set bonding positions before the unit positions are determined, combined with the low degree of freedom of the simple matrix-type bonding positions, will limit the iterations towards the optimal solution.

[0041] Existing 3D layout algorithms in academia, such as ePlace-3D and NTUPlace-3D, are designed based on TSV (Through-Silicon Via) connection process, which is inconsistent with the current advanced F2F (face-to-face) bonding scenarios. This is because: the insertion of TSV will occupy the available placement position of standard cells, and these algorithms will consider in advance to avoid overlap between standard cells and TSV during layout, which sacrifices optimization for redundant constraints under the face-to-face bonding process that does not occupy the bottom area. In addition, this type of algorithm that processes all cells as a whole in three-dimensional space assumes that the process of each layer of bare chips is consistent, which is also inconsistent with advanced heterogeneous integration scenarios.

[0042] Therefore, traditional methods deal roughly with face-to-face bonded heterogeneous integrated circuits, and even ignore the characteristics of heterogeneous integration scenarios, and cannot provide effective layout solutions for 3D integrated circuits.

[0043] Based on this, this application proposes a new three-dimensional integrated circuit layout algorithm, which can flexibly adapt to the constraints of face-to-face bonding, consider heterogeneous integration scenarios and perform corresponding optimizations.

[0044] This application proposes a new three-dimensional integrated circuit layout scheme, the idea is as follows:

[0045] First, based on the connection netlist divided into upper and lower dies, die layout rules and cell bonding process library, a vectorized integration method based on the existing analytical layouter is proposed to achieve multi-layer synchronous analytical global layout of cells and face-to-face bonding within each layer of die, ensuring the continuity of the solution process. Among them, the internal weight parameters of each layer are updated independently to support dies with different process row heights; and the face-to-face bonding design constraints are modeled according to the iterative density terms to better support the manufacturability of the bonding position design;

[0046] Then, after the legalization of the marked cells in the bare chip is obtained based on the analytical layout results, the position after the global layout of the face-to-face bonding is heuristically optimized through the division of the optimal area. The row-aligned legalization components are used to maximize the optimization of the line length while satisfying the spacing constraints, thereby obtaining the detailed layout of the marked cells. Finally, the horizontal position distribution of the cells and the face-to-face bonding is obtained to complete the overall layout of the three-dimensional integrated circuit.

[0047] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0048] refer to Figure 1 As an example, the analytical global layout problem is modeled as a half-perimeter line length (HPWL) minimization optimization with density constraints.

[0049] The half-perimeter line length (HPWL) minimization optimization with density constraint is modeled as:

[0050]

[0051] Where e is the line net in the netlist E, which can be regarded as the collection of its connected units; is the unit v in the network e i For face-to-face bonding, the relative position of the pins is equivalent to the center point of the bonding size information (rectangle).

[0052] In general, the discontinuous semi-period length form will be smoothed using some approximation function in preparation for the gradient descent method; the constraints will be relaxed into the objective function as a penalty term controlled by the density weight λ.

[0053]

[0054] The smoothed line length of the unit involved in the line net e connection (including the bonding belonging to the cross-die line net) can be a weighted-average model or a log-sum-exp model. The objective function constructed for the density penalty term can use the bell-shaped density model in NTUPlacer or the electrostatic field model in ePlace.

[0055] According to the unit-die allocation, the wire nets connecting the units can be divided into intra-die wire nets and inter-die wire nets. The calculation method of the wire length of the intra-die wire net is the same as that of the 2D layout. For the inter-die wire net, the split is regarded as an independent intra-die wire net in each die, and the wire length is calculated and summed. The split intra-die wire net includes the set of cells of the original wire net in the die, and the face-to-face bonding corresponding to the original wire net. The face-to-face bonding is modeled as a cell with the pin in the middle to adapt to the existing analytical global placer structure.

[0056] For the current 3D layout scenario, the integrated process is achieved by vectorizing the density and line length terms of the above analytical global layout of the objective function. and Are vectorized to match the number of independent layout layers stacked on the z-axis.

[0057]

[0058] Represents the normalization of the line length weight parameter; density penalty factor The elements in the ,are updated separately according to the overlap status of each layout layer, and the updating method is determined by the original 2D analytic layout algorithm used.,This design of independently setting and updating parameters is suitable for heterogeneous architectures with different row heights and cell sizes, and is scalable.

[0059] In order to better support the manufacturability of the bonding position design, the present invention expands on the density distribution of standard cells within the die that the general layout engine is concerned about. The new modeling takes into account factors such as bonding gap and bonding size, and measures the distribution of bonding positions by introducing bonding equivalent size, and incorporates it into the density calculation.

[0060] Specifically, if is the bonding unit v i Original size information (length and width), d inter is the minimum spacing constraint between bonds. In the density term bonding layer modeling of the present invention, the bonding unit v i The size is equivalent to Participate in the iterative calculation of the density term. To maintain the relative position of the pin, the lower left corner coordinate Calculation with Offset.

[0061] After the global layout calculation is completed, the bonding model is restored to its original size, and the coordinate position information offset is also restored accordingly. By considering the density penalty of the bonding layer bonding and controlling the iterative optimization of the density term, the wire length between the bare chips is minimized while ensuring the bonding manufacturability, that is, ensuring the minimum spacing constraint between the bonds.

[0062] The iteration stops when the area overlap rate drops to the set threshold or the number of iterations exceeds the upper limit. After the iteration stops, the row alignment-based legalization algorithm Abacus is called for the cells inside each die to eliminate the overlap between cells.

[0063] For the bonding positions of the cross-die wire nets, they will be optimized after the analytical global layout is completed. Due to the calculation characteristics of the half-circle wire length, given the half-circle wire length calculation bounding box of the cross-die wire net on the top and bottom parts, the optimal bonding layout area can be derived. Without loss of generality, the upper and lower limits x in the x direction of the optimal area can be given l , x r If the upper and lower boundaries of the top and bottom bounding boxes are Sort these 4 values ​​and remove the largest and smallest values ​​to get x l , x r , the boundary results can be found in Figure 2 Hint.

[0064] When bonding in this optimal area, the total half-circle length of the wire net between the bare chips will not increase. However, when moving away from this optimal area, the increase in the total half-circle length is proportional to the shortest distance between the bonding and the border of the optimal area. Therefore, in order to further optimize the wire length, the bonding is first moved to the center point of the optimal area. After that, the row-based Abacus algorithm is used to solve the overlap of the position or spacing between the bonds. Compared with simple matrix matching, the Abacus algorithm places the bonding on a finer granularity, thereby reducing the displacement of the optimal area.

[0065] However, there may be multiple bonds competing for the same optimal area. Based on a natural assumption, the bonds that are still in the optimal area after legalization have a larger margin in the optimal area. Therefore, the bonds that are not in the optimal area can be moved to the center of the optimal area, and the remaining bonds remain in place, and the position is legalized using the Abacus algorithm. This step can be repeated within a limited number of times, and the best solution in all iterations is taken.

[0066] Finally, based on the results of standard cell legalization and face-to-face bonding position optimization, the positions are fine-tuned through global exchange, local exchange, and position matching to optimize the layout of cells of the same size.

[0067] Based on the same inventive concept, the present application also provides a face-to-face bonding heterogeneous integrated circuit layout system, and a face-to-face bonding heterogeneous integrated circuit layout system formed based on the above-mentioned various method examples to automatically complete three-dimensional integrated circuit layout.

[0068] refer to Figure 3 Schematically, a face-to-face bonding heterogeneous integrated circuit layout system may include:

[0069] Layout module 101: based on the connection netlist of the multi-layer die, die layout rules and cell bonding process library, a vectorized analytical layout is used to iterate the layout position of the standard cells in each layer of die, wherein the density and line length parameters of the dies in different layers in the layout are adjusted between iterations until the number of iterations reaches an upper limit or the area overlap rate is less than a given threshold, thereby obtaining an initial solution for the standard cells and face-to-face bonding positions in each layer of die;

[0070] Legalization module 103: using the Abacus algorithm to solve the unit overlap in the initial solution, wherein the standard unit is adsorbed onto the row to obtain the legalization result of the standard unit;

[0071] Optimization module 105: Based on the legalization result of the standard cell, determine the optimal area of ​​the face-to-face bonding position and move it to the center of the area, use the Abacus algorithm to make the spacing between bonds meet the spacing constraint requirements, and obtain the optimization result between the legalization of the standard cell and the face-to-face bonding position;

[0072] Fine-tuning module 107: Based on the optimization results, globally swap cells of the same size by traversing, locally swapping cells in adjacent rows, and fine-tuning the position matching within the row until the number of iterations reaches an upper limit or the line length optimization amount is insufficient, thereby obtaining a detailed layout of the standard cell;

[0073] Output module 109: Based on the detailed layout of the standard cells, the allocation result of the standard cells and the face-to-face bonding horizontal positions in each layer of the die is obtained.

[0074] It should be noted that the setting of the unit module functions and the number of modules in the face-to-face bonding heterogeneous integrated circuit layout system can be set accordingly according to the aforementioned method embodiment, and will not be further described here.

[0075] Based on the same inventive concept, the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: a face-to-face bonding heterogeneous integrated circuit layout method as described in any embodiment of the present application.

[0076] like Figure 4 As shown, the present application also provides a schematic diagram of the structure of an electronic device, which shows the structure of the electronic device 500. The electronic device 500 is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0077] The electronic device 500 may include: at least one processor 510; and a memory 520 communicatively connected to the at least one processor; wherein the memory 520 stores instructions executable by the at least one processor 510, and the instructions are executed by the at least one processor 510 so that the at least one processor 510 can execute: the face-to-face bonding heterogeneous integrated circuit layout method described in any embodiment of the present application.

[0078] It should be noted that the electronic device 500 may be in the form of a general-purpose computing device, for example, it may be a server device.

[0079] In implementation, the components of the electronic device 500 may include but are not limited to: the above-mentioned at least one processor 510, the above-mentioned at least one memory 520, and a bus 530 connecting different system components (including the memory 520 and the processor 510), wherein the bus 530 may include a data bus, an address bus, and a control bus.

[0080] In implementation, the memory 520 may include a volatile memory, such as a random access memory (RAM) 5201 and / or a cache memory 5202 , and may further include a read-only memory (ROM) 5203 .

[0081] The memory 520 may also include a program tool 5205 having a set (at least one) of program modules 5204, such program modules 5204 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include the implementation of a network environment.

[0082] The processor 510 executes various functional applications and data processing by running computer programs stored in the memory 520 .

[0083] The electronic device 500 may also communicate with one or more external devices 540 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 550. Furthermore, the electronic device 500 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 560, which communicates with other modules in the electronic device 500 via a bus 530. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 500, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0084] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0085] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, they execute: a face-to-face bonding heterogeneous integrated circuit layout method as described in any embodiment of the present application.

[0086] It should be noted that the computer storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination thereof.

[0087] In a possible implementation, the present invention may also provide a form of a program product that implements data processing, which includes program code. When the program product runs on a terminal device, the program code is used to enable the terminal device to execute several steps of the method described in any of the aforementioned embodiments.

[0088] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on a user device, partially on a user device, as an independent software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0089] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for layout of face-to-face bonding heterogeneous integrated circuits, characterized in that: include: Based on the connection netlist of multi-layer dies, die layout rules and cell bonding process library, a vectorized analytical layout is used to iterate the layout position of standard cells in each layer of dies. The density and line length parameters of different layers of dies in the layout are adjusted between iterations until the number of iterations reaches the upper limit or the area overlap rate is less than a given threshold, and an initial solution for the face-to-face bonding position of standard cells in each layer of dies is obtained; The Abacus algorithm is used to solve the unit overlap in the initial solution, where the standard unit is adsorbed onto the row to obtain the legalization result of the standard unit; Based on the legalization results of the standard cell, the optimal area of ​​the face-to-face bonding position is determined, and the Abacus algorithm is used to make the spacing between bonds meet the spacing constraint requirements, and the optimization results between the legalization of the standard cell and the face-to-face bonding position are obtained; Based on the optimization results, the detailed layout of the standard cell is obtained by traversing and globally exchanging cells of the same size, and locally exchanging cells in adjacent rows and fine-tuning the position matching within the row until the number of iterations reaches the upper limit or the line length optimization amount is insufficient; Based on the detailed layout of standard cells, the allocation results of the standard cells and the face-to-face bonding horizontal positions in each layer of the die are obtained.

2. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 1, characterized in that: In the process of iterating the layout positions of standard cells in each layer of die using a vectorized analytical layout, the objective function is modeled as a half-circle line length minimization optimization problem with density constraints, where the objective function is: Where, e is the wire net in netlist E; is the unit v in the network e i The corresponding pin position information, the relative position of the pin is equivalent to the center point of the bonding size information; And, the constraint is relaxed into the objective function as a penalty term controlled by the density weight λ: is the smoothed line length of the units involved in the line network e connection, Objective function constructed for density penalty; two-dimensional term and Vectorize to match the number of independent layout layers stacked on the z-axis; in, Represents the normalization of the line length weight parameter; density penalty factor The elements in ,λ bottom is the density weight of the lower die, λ top is the density weight of the upper die, λ inter is the density weight between healthy individuals.

3. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 2, characterized in that: Bonding unit v i The size is equivalent to Participate in the iterative calculation of density terms, where is the bonding unit v i The original size information of length and width, d inter is the minimum spacing constraint between bonds.

4. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 3, characterized in that: During global layout calculation, the lower left corner coordinates of the bond modeling With and, after the global layout calculation is completed, the bonding modeling is restored to its original size, and the coordinate position information offset is restored accordingly.

5. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 1, characterized in that: In determining the optimal region of the face-to-face bonding position, the boundary coordinates of the upper and lower bounding boxes in the same direction are sorted respectively, and the bounding region obtained by the boundary coordinates after removing the maximum and minimum values ​​is taken as the optimal region.

6. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 5, characterized in that: After obtaining the optimal region, the bonds are first moved to the center of the optimal region, and then the row-based Abacus algorithm is used to resolve the overlap of bond positions or spacings.

7. The face-to-face bonding heterogeneous integrated circuit layout method according to claim 6, characterized in that: When multiple bonds compete for the same optimal area, the bonds that are not in the optimal area are moved to the center of the optimal area, and the remaining bonds remain in place.

8. A face-to-face bonding heterogeneous integrated circuit layout system, characterized in that: include: Layout module: Based on the connection netlist of multi-layer dies, die layout rules and cell bonding process library, the layout position of standard cells in each layer of dies is iterated using a vectorized analytical layout device. The density and line length parameters of dies in different layers in the layout device are adjusted between iterations until the number of iterations reaches the upper limit or the area overlap rate is less than a given threshold, and an initial solution for the standard cells and face-to-face bonding positions in each layer of dies is obtained; Legalization module: Use the Abacus algorithm to solve the unit overlap in the initial solution, in which the standard unit is adsorbed onto the row to obtain the legalization result of the standard unit; Optimization module: Based on the legalization results of the standard cell, the optimal area of ​​the face-to-face bonding position is determined and moved to the center of the area. The Abacus algorithm is used to make the spacing between bonds meet the spacing constraint requirements, and the optimization results between the legalization of the standard cell and the face-to-face bonding position are obtained; Fine-tuning module: Based on the optimization results, the detailed layout of the standard cell is obtained by traversing and globally exchanging cells of the same size, and performing local exchanges in adjacent rows and position matching in the row until the number of iterations reaches the upper limit or the line length optimization amount is insufficient; Output module: Based on the detailed layout of standard cells, the allocation results of the standard cells and the face-to-face bonding horizontal positions in each layer of bare chips are obtained.

9. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the face-to-face bonding heterogeneous integrated circuit layout method as described in any one of claims 1-7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the face-to-face bonding heterogeneous integrated circuit layout method according to any one of claims 1-7 is performed.

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