Silicon-based embedded double-face plastic-packaged high-density 3D packaging structure and manufacturing method

Abstract

The invention discloses a silicon-based embedded double-face plastic-packaged high-density 3D packaging structure and a manufacturing method. A chip is mounted on a silicon substrate, a rewiring structure is manufactured on the surface of the silicon substrate, a functional chip is connected to the rewiring structure, the functional chip and the silicon substrate are subjected to plastic packaging respectively, and a first plastic packaging body and a second plastic packaging body are formed; forming a metal rewiring structure on the first plastic package body, and arranging a second metal conductive structure on the metal rewiring structure; and grinding and thinning the second plastic package body until the chip is exposed. According to the method, firstly, a groove is dug in one side of a silicon substrate, a chip is attached to the groove, then a rewiring structure is manufactured and connected with a functional chip, then plastic package thinning is carried out, in order to reduce warping, plastic package is carried out on the other side of the silicon substrate, the plastic package thickness is determined by the warping degree until no warping phenomenon exists, then wiring is carried out, signal three-dimensional interconnection and stress release are achieved through a TMV hole structure, and the reliability of the silicon substrate is improved. And the second plastic packaging body is ground and thinned until the chip is exposed, so that the heat dissipation capability of the packaging structure is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure and a manufacturing method thereof. Background Art

[0002] As the market becomes more and more diversified, applications such as big data, cloud computing, and artificial intelligence have emerged one after another, all of which hope to have higher computing speeds, higher bandwidths, and relatively low costs and power consumption. The increasing diversification of products has placed higher requirements on multi-chip integration. The traditional 3D stacking structure will increase its warping after plastic encapsulation, which is not conducive to subsequent fine wiring and will reduce the product yield. Therefore, there is an urgent need for a structure that makes the entire wafer warp-free before subsequent wiring, which will reduce subsequent rewiring defects and yield losses caused by warping. Summary of the invention

[0003] In order to solve the technical problems existing in the prior art, the purpose of the present invention is to provide a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure and a manufacturing method.

[0004] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0005] A method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure comprises the following steps:

[0006] First, the chip is mounted on the silicon substrate, and then a rewiring structure is made on the surface of the silicon substrate. Then, a functional chip is connected to the rewiring structure. Then, the functional chip and the silicon substrate are plastic-encapsulated respectively to form a first plastic-encapsulated body and a second plastic-encapsulated body. Then, a metal rewiring structure is formed on the first plastic-encapsulated body, and a second metal conductive structure is arranged on the metal rewiring structure. Finally, the second plastic-encapsulated body is ground and thinned until the chip is exposed.

[0007] Furthermore, the production method comprises the following steps:

[0008] Step 1: providing a silicon substrate and preparing a groove on the surface of the silicon substrate;

[0009] Step 2: Fix the chip at the bottom of the groove;

[0010] Step 3: Fill the gap between the chip and the silicon substrate and expose the chip pad of the chip;

[0011] Step 4: Make a rewiring structure on the silicon substrate surface and electrically connect the rewiring structure to the chip pad;

[0012] Step 5: Connecting the functional chip to the rewiring structure;

[0013] Step 6: Filling the gap between the rewiring structure and the functional chip;

[0014] Step 7: Plastic-encapsulating the functional chip to form a first plastic-encapsulated body;

[0015] Step 8: Grind and thin the first plastic package body, grind and thin the side of the silicon base away from the functional chip and perform plastic sealing to form a second plastic package body for controlling warpage;

[0016] Step nine: coating photoresist on the first plastic package body and forming opening II, corresponding to the metal pad on the redistribution structure, for subsequent signal interconnection;

[0017] Step 10: forming a TMV hole structure at a position corresponding to the opening II on the first plastic package body;

[0018] Step 11: Disposing a dielectric layer on the sidewall of the TMV hole structure;

[0019] Step 12: preparing an RDL structure in the TMV hole structure;

[0020] Step 13: forming a metal redistribution structure on the first plastic package body, and providing a second metal conductive structure at the metal pad on the uppermost layer of the metal redistribution structure;

[0021] Step 14: Grind and thin the second plastic package until the chip is exposed to improve the heat dissipation capacity of the entire packaging structure.

[0022] Furthermore, in step 2, a DAF film is attached to one side of the chip, and a chip pad is provided on the other side of the chip opposite thereto. The side of the chip attached with the DAF film is fixed to the bottom of the groove, and the DAF film is removed in step 14.

[0023] Furthermore, in step three, the gap between the chip and the silicon substrate is filled by pressing a dry film, and an opening I is formed in the dry film at a position corresponding to the chip pad of the chip by photolithography technology.

[0024] Furthermore, in step five, the functional chip is bonded to the first metal conductive structure of the redistribution structure through metal bumps.

[0025] Furthermore, in step six, an underfill technique is used to fill the gap between the redistribution structure and the functional chip with an underfill glue.

[0026] Furthermore, in step eleven, the dielectric layer is SiNx or SiOx, and has a thickness of 0.5-2 μm.

[0027] Furthermore, in step thirteen, the second metal conductive structure is composed of Sn, Ag or Cu.

[0028] The present invention also discloses a method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure as described above, characterized in that it includes a silicon base, a chip is arranged on the silicon base and the gap between the two is filled with a dry film, a redistribution structure is also arranged on the silicon base, a functional chip is connected to the redistribution structure, the gap between the redistribution structure and the functional chip is filled with bottom filling glue, the functional chip is externally plastic-sealed to form a first plastic sealing body, a metal redistribution structure is arranged on the first plastic sealing body, and a second metal conductive structure is arranged at the metal pad of the uppermost layer of the metal redistribution structure.

[0029] Furthermore, the functional chip is bonded to the first metal conductive structure of the rewiring structure through a metal bump; a TMV hole structure is provided on the first plastic package body, a dielectric layer is provided on the sidewall of the TMV hole structure, and an RDL structure is provided in the TMV hole structure.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention discloses a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure and a manufacturing method thereof. A groove is firstly dug on one side of the silicon base and a chip is pasted therein, and then a rewiring structure is manufactured and a functional chip is connected, and then the plastic sealing is thinned. To reduce warping, plastic sealing is performed on the other side of the silicon base to form a second plastic sealing body. The thickness of the plastic sealing is determined by the degree of warping. After there is no warping, wiring is performed, and three-dimensional signal interconnection and stress release are realized through a TMV hole structure, so as to further reduce warping. Finally, the second plastic sealing body and a DAF film are ground and thinned until the chip is exposed, which is beneficial to improving the heat dissipation capacity of the entire packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of step 1 of the present invention;

[0033] Figure 2 It is a structural schematic diagram of step 2 of the present invention;

[0034] Figure 3 It is a structural schematic diagram of step three of the present invention;

[0035] Figure 4 It is a structural schematic diagram of step 4 of the present invention;

[0036] Figure 5 It is a structural schematic diagram of step five of the present invention;

[0037] Figure 6 It is a structural schematic diagram of step six of the present invention;

[0038] Figure 7 It is a structural schematic diagram of step seven of the present invention;

[0039] Figure 8 It is a structural schematic diagram of step eight of the present invention;

[0040] Fig. 9 It is a structural schematic diagram of step nine of the present invention;

[0041] Fig.10 It is a structural schematic diagram of step ten of the present invention;

[0042] Fig.11 It is a structural schematic diagram of step eleven of the present invention;

[0043] Fig.12 It is a structural schematic diagram of step twelve of the present invention;

[0044] Fig.13 It is a structural schematic diagram of step thirteen of the present invention;

[0045] Fig.14 It is a structural schematic diagram of step fourteen of the present invention. DETAILED DESCRIPTION

[0046] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0047] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0048] like Figure 1-14 As shown, the present invention discloses a method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure, comprising the following steps:

[0049] Step 1: If Figure 1 As shown, a groove 101 is prepared on the surface of the silicon substrate 1 by photolithography and etching technology;

[0050] Step 2: If Figure 2 As shown, a chip 2 is provided, one side of the chip 2 is attached with a DAF film 201, and the other side of the chip 2 opposite to the chip 2 has a chip pad; the side of the chip 2 attached with the DAF film 201 is fixed to the bottom of the groove 101 by DA (Die attach) technology, and the size of the groove 101 is adapted to the chip 2, and the size of the groove 101 is slightly larger than the chip 2;

[0051] Step 3: If Figure 3 As shown, the gap between the chip 2 and the silicon substrate 1 is filled by pressing the dry film 3, and the position of the dry film 3 corresponding to the chip pad is formed into an opening I by photolithography technology, and the dry film 3 is a photosensitive material;

[0052] Step 4: If Figure 4 As shown, a rewiring structure 4 is manufactured on the surface of the silicon substrate 1, and the rewiring structure 4 includes a metal rewiring layer and a PI passivation layer, wherein the metal rewiring layer is formed on the surface of the silicon substrate 1 by the cooperation of a magnetron sputtering process, a photolithography process and an electroplating process, and a conductive opening is formed on the PI passivation layer by a photolithography process, and the metal lines of the two metal rewiring layers located at the bottom and the top are metal pads, and a first metal conductive structure 401 is formed on the metal pad of the top layer, which can be a solder ball such as a tin ball formed by a ball planting process, or a plated metal bump formed by an electroplating process, which is used for subsequent electrical connection with a flip chip;

[0053] Step 5: If Figure 5 As shown, a function chip 5 is connected to the rewiring structure 4. The function chip 5 can be bonded to the first metal conductive structure 401 of the rewiring structure 4 through a metal bump 501 below the function chip 5 by flip-chip bonding technology, and then wafer reconstruction is achieved by thermal reflow technology;

[0054] Step 6: If Figure 6 As shown, the gap between the redistribution structure 4 and the functional chip 5 is filled with an underfill glue 6 by using an underfill technology to block water vapor and improve reliability;

[0055] Step 7: If Figure 7 As shown, the functional chip 5 is plastic-sealed to form a first plastic-sealed body 7, which plays a role in protecting the functional chip 5;

[0056] Step 8: If Figure 8 As shown, the first plastic package body 7 is ground and thinned, and the side of the silicon base 1 away from the functional chip 5 is ground and thinned and plastic-sealed to form a second plastic package body 8. The thickness of the plastic package is determined according to the degree of warping until there is no warping phenomenon;

[0057] Step 9: If Fig. 9 As shown, a layer of photoresist is coated on the first plastic package 7, and an opening II is formed by a photolithography process to obtain an opening structure 9, and the opening II corresponds to the metal pad on the redistribution structure 4 below the first plastic package 7, so as to facilitate subsequent signal interconnection;

[0058] Step 10: Fig.10 As shown, a TMV hole structure 10 is formed at a position corresponding to the opening II on the first plastic package 7 by using photolithography and etching technology;

[0059] Step 11: Fig.11 As shown, a dielectric layer 1001 is provided on the side wall of the TMV hole structure 10 by CVD, PECVD or PEALD technology, and the dielectric layer 1001 can be SiNx or SiOx, etc. By opening a hole in the first plastic package 7, it is beneficial to release its internal stress and reduce warpage;

[0060] Step 12: Fig.12 As shown, a seed layer is sputtered in the TMV hole structure 10 by PVD technology, and then an RDL structure 1002 is prepared by electroplating. The metal copper on the surface of the RDL structure 1002 can be removed by wet etching or chemical mechanical polishing (CMP).

[0061] Step 13: Fig.13 As shown, a metal rewiring structure is formed by rewiring on the first plastic package 7 through magnetron sputtering, photolithography and electroplating processes, and a second metal conductive structure 11 is formed at the position of the metal pad on the top layer of the metal rewiring structure. The composition of the second metal conductive structure 11 can be Sn, Ag or Cu, etc.;

[0062] Step 14: Fig.14 As shown, the second plastic package body 8 and the DAF film 201 for controlling the warpage are ground and thinned until the chip 2 is exposed, thereby improving the heat dissipation capacity of the entire packaging structure.

[0063] The present invention also discloses a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure, comprising a silicon base 1, a chip 2 is arranged on the silicon base 1 and the gap between the two is filled with a dry film 3, a redistribution structure 4 is also arranged on the silicon base 1, a functional chip 5 is bonded to the first metal conductive structure 401 of the redistribution structure 4 through a metal bump 501, the gap between the redistribution structure 4 and the functional chip 5 is filled with an underfill 6, the outside of the functional chip 5 is plastic-sealed to form a first plastic sealing body 7, a TMV hole structure 10 is arranged on the first plastic sealing body 7, a dielectric layer 1001 is arranged on the side wall of the TMV hole structure 10, an RDL structure 1002 is arranged in the TMV hole structure 10, a metal redistribution structure is arranged on the first plastic sealing body 7, and a second metal conductive structure 11 is arranged at the metal pad on the top layer of the metal redistribution structure.

[0064] Example 1

[0065] like Figure 1-14 As shown, a method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure comprises the following steps:

[0066] Step 1: If Figure 1 As shown, a groove 101 is prepared on the surface of the silicon substrate 1 by photolithography and etching technology;

[0067] Step 2: If Figure 2 As shown, a chip 2 is provided, one side of the chip 2 is attached with a DAF film 201, and the other side of the chip 2 opposite to the chip 2 has a chip pad; the side of the chip 2 attached with the DAF film 201 is fixed to the bottom of the groove 101 by DA (Die attach) technology, and the size of the groove 101 is adapted to the chip 2, and the size of the groove 101 is slightly larger than the chip 2;

[0068] Step 3: If Figure 3 As shown, the gap between the chip 2 and the silicon substrate 1 is filled by pressing the dry film 3, and the position of the dry film 3 corresponding to the chip pad is formed into an opening I by photolithography technology, and the dry film 3 is a photosensitive material;

[0069] Step 4: If Figure 4 As shown, a rewiring structure 4 is manufactured on the surface of the silicon substrate 1, and the rewiring structure 4 includes a metal rewiring layer and a PI passivation layer, wherein the metal rewiring layer is formed on the surface of the silicon substrate 1 by the cooperation of a magnetron sputtering process, a photolithography process and an electroplating process, and a conductive opening is formed on the PI passivation layer by a photolithography process, and the metal lines of the two metal rewiring layers located at the bottom and the top are metal pads, and a first metal conductive structure 401 is formed on the metal pad of the top layer, which can be a solder ball such as a tin ball formed by a ball planting process, or a plated metal bump formed by an electroplating process, which is used for subsequent electrical connection with a flip chip;

[0070] Step 5: If Figure 5 As shown, a function chip 5 is connected to the rewiring structure 4. Specifically, the function chip 5 is bonded to the first metal conductive structure 401 of the rewiring structure 4 through a metal bump 501 below the function chip 5 by flip-chip bonding technology, and then wafer reconstruction is achieved by thermal reflow technology;

[0071] Step 6: If Figure 6 As shown, the gap between the redistribution structure 4 and the functional chip 5 is filled with an underfill glue 6 by using an underfill technology to block water vapor and improve reliability;

[0072] Step 7: If Figure 7 As shown, the functional chip 5 is plastic-sealed to form a first plastic-sealed body 7, which plays a role in protecting the functional chip 5;

[0073] Step 8: If Figure 8 As shown, the first plastic package body 7 is ground and thinned, and the side of the silicon base 1 away from the functional chip 5 is ground and thinned and plastic-sealed to form a second plastic package body 8. The thickness of the plastic package is determined according to the degree of warping until there is no warping phenomenon;

[0074] Step 9: If Fig. 9 As shown, a layer of photoresist is coated on the first plastic package 7, and an opening II is formed by a photolithography process to obtain an opening structure 9, and the opening II corresponds to the metal pad on the redistribution structure 4 below the first plastic package 7, so as to facilitate subsequent signal interconnection;

[0075] Step 10: Fig.10 As shown, a TMV hole structure 10 is formed at a position corresponding to the opening II on the first plastic package 7 by using photolithography and etching technology;

[0076] Step 11: Fig.11 As shown, a dielectric layer 1001 is provided on the side wall of the TMV hole structure 10 by CVD technology, and the dielectric layer 1001 is SiNx. By opening a hole in the first plastic package 7, it is beneficial to release its internal stress and reduce warpage;

[0077] Step 12: Fig.12 As shown, a seed layer is sputtered in the TMV hole structure 10 by PVD technology, and then an RDL structure 1002 is prepared by electroplating, and the metal copper on the surface of the RDL structure 1002 is removed by wet etching;

[0078] Step 13: Fig.13 As shown, a metal rewiring structure is formed by rewiring on the first plastic package 7 through magnetron sputtering, photolithography and electroplating processes, and a second metal conductive structure 11 is formed at the position of the metal pad on the top layer of the metal rewiring structure. The composition of the second metal conductive structure 11 is Sn;

[0079] Step 14: Fig.14 As shown, the second plastic package body 8 and the DAF film 201 for controlling the warpage are ground and thinned until the chip 2 is exposed, thereby improving the heat dissipation capacity of the entire packaging structure.

[0080] A silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure comprises a silicon base 1, a chip 2 is arranged on the silicon base 1 and the gap between the two is filled with a dry film 3, a redistribution structure 4 is also arranged on the silicon base 1, a functional chip 5 is bonded to a first metal conductive structure 401 of the redistribution structure 4 through a metal bump 501, the gap between the redistribution structure 4 and the functional chip 5 is filled with an underfill 6, a first plastic sealing body 7 is formed by plastic sealing on the outside of the functional chip 5, a TMV hole structure 10 is arranged on the first plastic sealing body 7, a dielectric layer 1001 is arranged on the side wall of the TMV hole structure 10, an RDL structure 1002 is arranged in the TMV hole structure 10, a metal redistribution structure is arranged on the first plastic sealing body 7, and a second metal conductive structure 11 is arranged at the metal pad of the uppermost layer of the metal redistribution structure.

[0081] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0082] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure, characterized in that: The following steps are involved: First, the chip is mounted on the silicon substrate, then a rewiring structure is made on the surface of the silicon substrate, and then a functional chip is connected to the rewiring structure, and then the functional chip and the silicon substrate are plastic-sealed respectively to form a first plastic-sealed body and a second plastic-sealed body; Subsequently, a metal redistribution structure is formed on the first plastic package body, and a second metal conductive structure is disposed on the metal redistribution structure; Finally, the second plastic package is ground and thinned until the chip is exposed.

2. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 1, characterized in that: The following steps are involved: Step 1: providing a silicon substrate and preparing a groove on the surface of the silicon substrate; Step 2: Fix the chip at the bottom of the groove; Step 3: Fill the gap between the chip and the silicon substrate and expose the chip pad of the chip; Step 4: Make a rewiring structure on the silicon substrate surface and electrically connect the rewiring structure to the chip pad; Step 5: Connecting the functional chip to the rewiring structure; Step 6: Filling the gap between the rewiring structure and the functional chip; Step 7: Plastic-encapsulating the functional chip to form a first plastic-encapsulated body; Step 8: Grind and thin the first plastic package body, grind and thin the side of the silicon base away from the functional chip and perform plastic sealing to form a second plastic package body for controlling warpage; Step nine: coating photoresist on the first plastic package and forming opening II, corresponding to the metal pad on the redistribution structure, for subsequent signal interconnection; Step 10: forming a TMV hole structure at a position corresponding to the opening II on the first plastic package body; Step 11: Disposing a dielectric layer on the sidewall of the TMV hole structure; Step 12: preparing an RDL structure in the TMV hole structure; Step 13: forming a metal redistribution structure on the first plastic package body, and providing a second metal conductive structure at the metal pad on the uppermost layer of the metal redistribution structure; Step 14: Grind and thin the second plastic package until the chip is exposed to improve the heat dissipation capacity of the entire packaging structure.

3. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step 2, a DAF film is attached to one side of the chip, and a chip pad is provided on the other side of the chip opposite thereto. The side of the chip attached with the DAF film is fixed to the bottom of the groove, and the DAF film is removed in step 14.

4. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step three, the gap between the chip and the silicon substrate is filled by pressing a dry film, and an opening I is formed in the dry film at a position corresponding to the chip pad of the chip by photolithography technology.

5. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step five, the functional chip is bonded to the first metal conductive structure of the redistribution structure through metal bumps.

6. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step six, the gap between the redistribution structure and the functional chip is filled with underfill glue using underfill technology.

7. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step eleven, the dielectric layer is SiNx or SiOx, and has a thickness of 0.5-2 μm.

8. The method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 2, characterized in that: In step thirteen, the second metal conductive structure is made of Sn, Ag or Cu.

9. A silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure manufactured by the method for manufacturing a silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to any one of claims 1 to 8, characterized in that: It includes a silicon base, a chip is arranged on the silicon base and the gap between the two is filled with a dry film, a redistribution structure is also arranged on the silicon base, a functional chip is connected to the redistribution structure, the gap between the redistribution structure and the functional chip is filled with bottom filling glue, the functional chip is externally plastic-sealed to form a first plastic sealing body, a metal redistribution structure is arranged on the first plastic sealing body, and a second metal conductive structure is arranged at the metal pad of the uppermost layer of the metal redistribution structure.

10. The silicon-based embedded double-sided plastic-sealed high-density 3D packaging structure according to claim 9, characterized in that: The functional chip is bonded to the first metal conductive structure of the rewiring structure through a metal bump; a TMV hole structure is arranged on the first plastic package body, a dielectric layer is arranged on the side wall of the TMV hole structure, and an RDL structure is arranged in the TMV hole structure.

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