Method for improving layer deviation precision of circuit board
By setting beer punching and riveting holes on the circuit board, combining riveting and precision detection, the full inspection steps are cancelled, which solves the problem of biasing accuracy of the riveting layer of the circuit board, reduces manufacturing costs, improves work efficiency, and improves products quality.
Patent Information
- Application Number
- CN202411269533.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-01-07
AI Technical Summary
After riveted production, high multi-layer circuit boards require full inspection of the layer accuracy, resulting in increased manufacturing costs, low working efficiency and high product quality risks.
By setting a 2.0mm beer punching hole on the substrate and setting a rivet hole with a diameter of 3.175mm using the OPE punching equipment, performing riveting and accuracy detection, canceling the full inspection step, and mass production is determined based on the detection value.
Improve the precision of the riveted layer, reduce manufacturing costs, accelerate product flow efficiency, improve work efficiency, and improve product quality.
Smart Images
Figure CN119277683A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit board production, and in particular to a method for improving the layer deviation accuracy of a circuit board. Background Art
[0002] At present, high-layer circuit boards need to be fully inspected for layer deviation accuracy after riveting production. If the number exceeds the 4mil accuracy tolerance, the quality risk is high and all of them are scrapped. However, the need for full inspection leads to increased production costs, waste of personnel production capacity, low work efficiency, and poor layer deviation accuracy, which affects product quality. Summary of the invention
[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for improving the layer deviation accuracy of a circuit board, which can improve the layer deviation accuracy of riveting and improve product quality, while eliminating the full inspection step in the relevant technology, reducing manufacturing costs, speeding up product flow time, improving work efficiency, and making work easier and simpler.
[0004] The method for improving the layer deviation accuracy of a circuit board according to an embodiment of the present application includes: Data preparation: Determine the spacing between the punching positions according to the substrate, and set a punching hole with a diameter of 2.0 mm at the punching position; OPE beer punching: a riveting hole with a diameter of 3.175 mm is set according to the beer punching; Riveting: using rivets with a diameter of 3.175 mm to stack and rivet multiple layers of the substrate to obtain an inner layer plate; Riveting accuracy detection: perform layer deviation accuracy detection on the inner layer plate and obtain the detection value; Batch production: Determine the batch production of the inner layer panels according to the detection values.
[0005] The method for improving the layer deviation accuracy of a circuit board according to the embodiment of the present application has at least the following beneficial effects: by adopting the above method, a beer punching hole with a diameter of 2.0 mm is first set, and then a riveting hole with a diameter of 3.175 mm is set in the beer punching hole, thereby improving the riveting layer deviation accuracy and improving product quality. At the same time, it is determined whether to carry out batch production based on the detection value, eliminating the full inspection step in the related technology, reducing manufacturing costs, accelerating product flow timeliness, improving work efficiency, and making work easier and simpler.
[0006] According to the circuit board layer deviation accuracy improvement method described in the embodiment of the present application, after completing the data preparation and before performing OPE beer punching, it also includes: Copper electroplating: copper electroplating is performed on the substrate; Inner layer exposure: exposing the substrate to print circuit patterns; Pattern etching: chemically etching the non-pattern areas of the substrate.
[0007] According to the method for improving the layer deviation accuracy of a circuit board described in an embodiment of the present application, during pattern etching, the copper layer in the punched hole is removed and the substrate is exposed.
[0008] According to the method for improving the layer deviation accuracy of a circuit board described in an embodiment of the present application, in the OPE beer punching, the riveted holes are subjected to copper beer punching treatment.
[0009] According to the method for improving the layer deviation accuracy of a circuit board described in an embodiment of the present application, in the OPE beer punching, a punch needle with a diameter of 3.175 mm is used to set the riveting hole in the beer punching.
[0010] According to the method for improving the layer deviation accuracy of a circuit board described in an embodiment of the present application, in the OPE beer punching hole, the center of the riveting hole coincides with the center of the beer punching hole.
[0011] According to the circuit board layer deviation accuracy improvement method described in the embodiment of the present application, after completing the OPE beer punching and before riveting, it also includes: Graphic inspection: Check the circuit graphics of the substrate; Browning: Chemically roughening the substrate.
[0012] According to the circuit board layer deviation accuracy improvement method described in the embodiment of the present application, in mass production, if the detection value does not exceed the preset value, the inner layer board is mass produced; if the detection value exceeds the preset value, the inner layer board is not mass produced.
[0013] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0015] Figure 1 A flowchart of a method for improving circuit board layer deviation accuracy in some embodiments of the present application; Figure 2 A flowchart of a method for improving circuit board layer deviation accuracy in some embodiments of the present application; Figure 3 This is a flow chart of a method for improving circuit board layer deviation accuracy according to some embodiments of the present application. DETAILED DESCRIPTION
[0016] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0017] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0018] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation, connection and connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0020] Reference Figure 1 , an embodiment of the present invention provides a method for improving layer deviation accuracy of a circuit board, including but not limited to step S110, step S120, step S130, step S140 and step S150.
[0021] Step S110, data preparation: determine the punching position spacing of the riveting holes according to the substrate, and set punching holes with a diameter of 2.0 mm at the punching positions.
[0022] Specifically, the substrate is first cut into plates of suitable sizes to meet production requirements, which can also reduce plate waste and reduce production costs; then the spacing between the punching positions is determined based on the substrate so that the subsequently obtained riveting holes are in predetermined positions to meet production requirements; finally, a punching hole with a diameter of 2.0 mm is set at the punching position to facilitate the subsequent setting of the riveting holes.
[0023] Step S120, OPE beer punching: set a riveting hole with a diameter of 3.175 mm according to the beer punching.
[0024] Specifically, an OPE punching device is used to set a riveting hole with a diameter of 3.175 mm at the beer punching position to facilitate subsequent riveting.
[0025] Reference Figure 2 , after completing Figure 1 After step S110 and before step S120, the method further includes: Step S210, copper electroplating: copper electroplating is performed on the substrate; Step S220, inner layer exposure: exposing the substrate to print circuit patterns; Step S220, pattern etching: chemically etching the non-pattern area of the substrate.
[0026] Specifically, the substrate is subjected to copper electroplating to form a copper layer on the substrate, and the hole walls of the beer punching holes are also formed with a copper layer; then the dry film is pressed onto the substrate, and exposed and developed to print the circuit pattern on the substrate; finally, chemical etching is used to remove the copper layer in the non-pattern area of the substrate, so that a circuit layer is formed on the substrate.
[0027] Furthermore, when chemical etching is used to remove the copper layer, the copper layer on the hole wall of the beer punching hole is also removed at the same time, thereby ensuring that there is no copper residue in the subsequent riveting process and ensuring product quality.
[0028] It can be imagined that in the OPE beer punching, the OPE punching equipment is used, a punch needle with a diameter of 3.175mm is used, and the punch needle is positioned at the beer punching hole with a diameter of 2.0mm, and then the copper is damaged by beer punching, so that the center of the riveted hole obtained coincides with the center of the beer punching hole, thereby improving the layer deviation accuracy of the circuit board and improving product quality.
[0029] Step S130, riveting: using 3.175 mm rivets to stack and rivet the multi-layer substrates to obtain an inner layer board.
[0030] Specifically, the multi-layer substrates are aligned and stacked so that the riveting holes of each substrate are in the same position, and then the multi-layer substrates are riveted with rivets with a diameter of 3.175 mm to obtain the inner layer, so as to facilitate the subsequent layer deviation accuracy detection of the riveted structure. During the riveting process, the diameter tolerance of the rivet is +0 / -0.05 mm, which can improve the riveting accuracy and product quality.
[0031] Reference Figure 3 In some embodiments, upon completion of Figure 1After step S130 and before step S140, the method further includes: Step S310, pattern inspection: inspecting the circuit pattern of the substrate; Step S320, browning: chemically roughening the substrate.
[0032] Specifically, the circuit pattern of the substrate is inspected by using AOI scanning equipment, so as to determine whether the substrate meets the production requirements based on the inspection results to ensure zero defect leakage. When the inspection results meet the production requirements, the copper surface on the substrate is roughened by chemical solution to increase the bonding area, thereby improving the bonding force between the prepreg and the copper surface of the substrate. By adopting the above method, product quality can be improved and production costs can be reduced.
[0033] Step S140, riveting accuracy detection: performing layer deviation accuracy detection on the inner layer board and obtaining the detection value.
[0034] Specifically, the inner layer board is placed in an x-ray detector for layer deviation accuracy detection, thereby obtaining the detection value of the inner layer board to facilitate determination of subsequent work, avoid product scrapping, reduce production costs, and ensure product quality.
[0035] Step S150, batch production: determine the inner layer boards to be batch produced according to the detection values.
[0036] Specifically, after the test value is obtained, it is determined whether to carry out batch production of the inner layer board according to the result of the test value. The preset value is set to 1mil. If the test value does not exceed 1mil, the inner layer board is mass produced; if the test value exceeds 1mil, the inner layer board is not mass produced. By adopting the above method, it is determined whether to carry out batch production according to the obtained test value. At this time, the full inspection step in the related technology is cancelled, the manufacturing cost is reduced, the product flow time is accelerated, the work efficiency is improved, and the work is easier and simpler.
[0037] The method for improving the layer deviation accuracy of the circuit board described in the embodiment of the present application first determines the spacing of the beer punching positions according to the substrate, and sets beer punching holes with a diameter of 2.0mm at the beer punching positions; then uses the OPE punching equipment to set rivet holes with a diameter of 3.175mm at the beer punching holes; then uses rivets with a diameter of 3.175mm to stack and rivet the multi-layer substrates to obtain the inner layer board; finally, the inner layer board is tested for layer deviation accuracy by an x-ray detector, and it is determined whether the inner layer board is mass-produced based on the test value. By adopting the above method, the beer punching holes are first set to 2.0mm, and then the rivet holes with a diameter of 3.175mm are set in the beer punching holes, so that the accuracy of the riveting layer deviation can be improved, the product quality can be improved, and at the same time, it can be determined whether to carry out mass production based on the test value, eliminating the full inspection step in the related technology, reducing manufacturing costs, accelerating product flow timeliness, improving work efficiency, and making work easier and simpler.
[0038] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0039] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.
Claims
1. A method for improving the layer deviation accuracy of a circuit board, characterized in that: include: Data preparation: Determine the spacing between the punching positions according to the substrate, and set a punching hole with a diameter of 2.0 mm at the punching position; OPE beer punching: a riveting hole with a diameter of 3.175 mm is set according to the beer punching; Riveting: using rivets with a diameter of 3.175 mm to stack and rivet multiple layers of the substrate to obtain an inner layer plate; Riveting accuracy detection: perform layer deviation accuracy detection on the inner layer plate and obtain the detection value; Batch production: Determine the batch production of the inner layer panels according to the detection values.
2. The method for improving the layer deviation accuracy of a circuit board according to claim 1, characterized in that: After completing the data preparation and before punching the OPE beer, it also includes: Copper electroplating: copper electroplating is performed on the substrate; Inner layer exposure: exposing the substrate to print circuit patterns; Pattern etching: chemically etching the non-pattern areas of the substrate.
3. The method for improving the layer deviation accuracy of a circuit board according to claim 2, characterized in that: During pattern etching, the copper layer within the beer punched holes is removed and the substrate is exposed.
4. The method for improving the layer deviation accuracy of a circuit board according to claim 2, characterized in that: In the OPE beer punching, the riveting holes are subjected to copper beer punching treatment.
5. The method for improving the layer deviation accuracy of a circuit board according to claim 4, characterized in that: In the OPE beer punching, a punch needle with a diameter of 3.175 mm is used to set the riveting hole in the beer punching.
6. The method for improving the layer deviation accuracy of a circuit board according to claim 5, characterized in that: In the OPE beer punching hole, the center of the riveting hole coincides with the center of the beer punching hole.
7. The method for improving the layer deviation accuracy of a circuit board according to claim 2, characterized in that: After punching the OPE beer and before riveting, it also includes: Graphic inspection: Check the circuit graphics of the substrate; Browning: Chemically roughening the substrate.
8. The method for improving the layer deviation accuracy of a circuit board according to claim 1, characterized in that: In batch production, if the detection value does not exceed the preset value, the inner layer board is batch produced; if the detection value exceeds the preset value, the inner layer board is not batch produced.