Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a source region, a drain region and a gate structure. The source region is located in the substrate. The drain region is located in the substrate. The gate structure is disposed on the substrate and between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. The second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. The second sub-gate insulating layer is separated from the first sub-gate insulating layer. The first sub-gate insulating layer has a first thickness, the second sub-gate insulating layer has a second thickness, and the second thickness is greater than the first thickness.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure with a separated gate and a manufacturing method thereof. Background Art

[0002] With the development of integrated circuit technology, composite semiconductor structures with different transistors have become one of the important structures that constitute integrated circuits. In composite semiconductor structures, different transistors have different requirements for providing critical voltages. For example, for transistors that withstand higher voltage values, thicker gate insulation layers are usually selected to prevent other core areas from being unable to withstand high voltages and causing electrical breakdown effects. However, an overly thick gate insulation layer cannot obtain the desired switching current. In addition, as the critical dimensions of semiconductor structures are miniaturized, integrated circuits are becoming more and more dense, and the manufacturing process steps are becoming increasingly complex. Summary of the invention

[0003] The present invention relates to a semiconductor structure and a manufacturing method thereof, which can withstand high voltage and have better electrical performance, and solve the problems of flatness and height difference caused by the existing manufacturing process.

[0004] According to one aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate, a source region, a drain region and a gate structure. The source region is located in the substrate. The drain region is located in the substrate. The gate structure is arranged on the substrate and is located between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. The second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. The second sub-gate insulating layer is separated from the first sub-gate insulating layer. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness, and the second thickness is greater than the first thickness.

[0005] According to another aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first transistor, and a second transistor. The substrate has a first component region and a second component region. The first transistor is formed in the first component region of the substrate and includes a first gate structure. The first gate structure includes a first sub-gate insulating layer and a second sub-gate insulating layer separated from each other, the first sub-gate insulating layer having a first thickness, the second sub-gate insulating layer having a second thickness, and the second thickness is greater than the first thickness. The second transistor is formed in the second component region of the substrate and includes a second gate structure. The second gate structure includes a second gate insulating layer, the second gate insulating layer having a third thickness, and the third thickness is approximately equal to the first thickness.

[0006] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided. The method comprises the following steps. First, a substrate is provided, the substrate having a first component area and a second component area. Then, a first transistor and a second transistor are formed in the first component area and the second component area of ​​the substrate, respectively. The first transistor comprises a first gate structure, the first gate structure comprises a first sub-gate insulating layer and a second sub-gate insulating layer separated from each other. The first sub-gate insulating layer has a first thickness, the second sub-gate insulating layer has a second thickness, and the second thickness is greater than the first thickness. The second transistor comprises a second gate structure, the second gate structure comprises a second gate insulating layer. The first sub-gate insulating layer and the second gate insulating layer are formed by patterning the same gate insulating material layer.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an embodiment of the present invention, illustrating a cross-sectional schematic diagram of a semiconductor structure;

[0009] Figure 2 is another embodiment of the present invention, illustrating a cross-sectional schematic diagram of a semiconductor structure;

[0010] Figure 3 is another embodiment of the present invention, illustrating a cross-sectional schematic diagram of a semiconductor structure;

[0011] Figure 4 is another embodiment of the present invention, illustrating a cross-sectional schematic diagram of a semiconductor structure;

[0012] Figure 5 The present invention Figure 2 A flowchart of a method for manufacturing a semiconductor structure of an embodiment;

[0013] Figure 6 The present invention Figure 4 A flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will describe in detail various embodiments of the present invention, and will be illustrated with the accompanying drawings. In addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and any easy replacement, modification, and equivalent changes of the embodiments are included in the scope of the present invention, and are subject to the subsequent claims. In the description of the specification, in order to enable the reader to have a more complete understanding of the present invention, many specific details and implementation examples are provided; however, these specific details and implementation examples should not be regarded as limitations of the present invention. In addition, well-known steps or elements are not described in detail to avoid unnecessary limitations of the present invention.

[0015] It should be noted that the drawings of the present invention are simplified to facilitate the clear description of the contents of the embodiments and highlight the features of the present invention. The size ratios on the drawings are not drawn in proportion to the actual products. Therefore, the specification and drawings are only used to describe the embodiments and are not used to limit the scope of protection of the present invention. The same element symbols are used to represent the same elements.

[0016] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., are used to modify elements. They do not imply or represent any previous ordinal number of the element, nor do they represent the order of one element and another element, or the order of manufacturing methods. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0017] In addition, the term “thickness” used herein, unless otherwise specified, refers to the linear distance between the upper and lower surfaces of the device structure (eg, insulating layer).

[0018] In addition, similar terms such as "about", "almost", "substantially", "approximately", etc., may be used here to mean "at", "close to", "almost at", "within 3-5%", "within an acceptable manufacturing tolerance range", or any logical combination thereof. Similarly, the terms "vertical" or "horizontal" may additionally include a range of "within 3-5%" in the vertical or horizontal direction. In addition, for ease of description, spatially relative terms such as "below", "below", "below", "above", "above", "on", etc. are used herein to describe the relationship between one device or feature as shown in the figure and another (or multiple) device or feature. In addition to the orientations shown in the drawings, spatially relative terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways, such as rotated 90 degrees or in other orientations, and the spatially related descriptors used herein may also be interpreted accordingly.

[0019] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present invention. Figure 1 , the semiconductor structure 100 may include a substrate 101, a gate structure 110, a source region 113, and a drain region 114. The source region 113 and the drain region 114 are located in the substrate 101. The gate structure 110 is disposed on the substrate 101 and is located between the source region 113 and the drain region 114. The gate structure 110, the source region 113, and the drain region 114 may constitute a transistor T1, and may be used as a gate G1, a source S1, and a drain D1 respectively through plug contacts (not shown) to receive external applied voltages.

[0020] The gate structure 110 may include a first sub-gate structure 111 and a second sub-gate structure 112. The first sub-gate structure 111 is adjacent to the source region 113; correspondingly, the second sub-gate structure 112 is adjacent to the drain region 114. In addition, the first sub-gate structure 111 and the second sub-gate structure 112 are separated from each other. The first sub-gate structure 111 may include a first sub-gate insulating layer 111a and a first sub-gate electrode layer 111b formed on the first sub-gate insulating layer 111a. The second sub-gate structure 112 may include a second sub-gate insulating layer 112a and a second sub-gate electrode layer 112b formed on the second sub-gate insulating layer 112a.

[0021] In one embodiment, the semiconductor structure 100 may further include a connection region 115. The connection region 115 is located in the substrate 101 and is connected to the first sub-gate insulating layer 111a and the second sub-gate insulating layer 112a. The connection region 115 may be a heavily doped region, a lightly doped region, or a well region, and may have the same conductivity type as the source region 113 and the drain region 114. For example, when the conductivity type of the source region 113 and the drain region 114 is N-type, the connection region 115 may provide heavy doping, light doping, or form an N-type well region with N-type dopants.

[0022] In one embodiment, the semiconductor structure 100 may further include a well region 116. The well region 116 is located in the substrate 101, and the source region 113, the drain region 114, and the connection region 115 are located in the well region 116. The well region 116 may have a conductivity type different from that of the source region 113 and the drain region 114. For example, when the conductivity type of the source region 113 and the drain region 114 is N-type, the well region 116 may be doped with P-type dopants.

[0023] In one embodiment, the semiconductor structure 100 may further include a drift region (drift region) 117. The drift region 117 is located in the well region 116, the drain region 114 is located in the drift region 117, and the second sub-gate structure 112 is located at the boundary between the well region 116 and the drift region 117. The drift region 117 may have the same conductivity type as the drain region 114, and may be lightly doped compared to the drain region 114. For example, when the conductivity type of the drain region 114 is N-type, the drift region 117 may be lightly doped with N-type dopants.

[0024] The first sub-gate insulating layer 111a and the second sub-gate insulating layer 112a may have different thicknesses. Specifically, the first sub-gate insulating layer 111a may have a first thickness H1, and the second sub-gate insulating layer 112a may have a second thickness H2, wherein the second thickness H2 is greater than the first thickness H1. Since a high voltage is usually applied to the drain region 114, the second sub-gate insulating layer 112a closer to the drain region 114 may be formed with a thicker thickness to prevent the second sub-gate insulating layer 112a from being broken due to the high voltage, thereby adversely affecting the device characteristics. In addition, the first sub-gate insulating layer 111a farther from the drain region 114 may be formed with a thinner thickness, thereby maintaining the desired switching current and better gate control capability, thereby improving the electrical performance of the device.

[0025] In addition, when viewed horizontally from a cross section of the semiconductor structure 100 (vertical to the horizontally extending upper surface 101u of the substrate 101), that is, from Figure 1 From the perspective of the drawing, the upper surfaces of the formed first sub-gate electrode layer 111b and the second sub-gate electrode layer 112b are substantially coplanar. In other words, the first sub-gate electrode layer 111b and the second sub-gate electrode layer 112b do not have a height difference, so when forming a plug contact (not shown) connecting the first sub-gate electrode layer 111b and the second sub-gate electrode layer 112b, no contact connection problem will occur.

[0026] In one embodiment, the lower surface F1 of the first sub-gate insulating layer 111a and the lower surface F2 of the second sub-gate insulating layer 112a may be located on the upper surface 101u of the substrate 101. In other words, when viewed from the cross section of the semiconductor structure 100 (vertical to the horizontally extending upper surface 101u of the substrate 101), that is, from Figure 1 When viewed from the perspective of the drawing, the lower surface F1 of the first sub-gate insulating layer 111a and the lower surface F2 of the second sub-gate insulating layer 112a may be substantially coplanar with the upper surface 101u of the substrate 101. In this embodiment, the first thickness H1 of the first sub-gate insulating layer 111a may be the same as the thickness of the gate insulating layer in a low-voltage transistor, and the second thickness H2 of the second sub-gate insulating layer 112a may be the same as the thickness of the gate insulating layer in an input / output transistor. For example, if the low-voltage transistor is a core device in the core region of the semiconductor structure, the first thickness H1 of the first sub-gate insulating layer 111a may be less than or equal to 25 angstroms. If the input / output transistor is an input / output element (I / O device) in the input / output region of the semiconductor structure, the second thickness H2 of the second sub-gate insulating layer 112a may be less than or equal to 40 angstroms.

[0027] For details, please refer to Figure 2 , which is a cross-sectional schematic diagram of a semiconductor structure 200 according to another embodiment of the present invention. The semiconductor structure 200 may be a composite semiconductor structure, and its substrate 101 may have a first device region R1, a second device region R2, and a third device region R3. It should be understood that, Figure 2 The relative positions of the first device region R1, the second device region R2 and the third device region R3 are only for illustration and are not intended to limit the present invention. These device regions R1 to R3 may be configured with different semiconductor devices, such as the first transistor T1, the second transistor T2 and the third transistor T3. The configuration of the first transistor T1 has been described in detail in Figure 1 The description is in the relevant content and will not be repeated here.

[0028] The first device region R1, the second device region R2 and the third device region R3 may have different operating voltage ranges, respectively. In one embodiment, the second device region R2 may be a low voltage region, and the second transistor T2 may be a low voltage transistor, such as a core device. The second transistor T2 may include a second gate structure 120, a source region 123 and a drain region 124. The second gate structure 120 is disposed on the substrate 101 and is located between the source region 123 and the drain region 124. The source region 123 and the drain region 124 may be formed in the well region 125. The second gate structure 120, the source region 123 and the drain region 124 may be used as a gate G2, a source S2 and a drain D2, respectively, via plug contacts (not shown) to receive an external applied voltage. The second gate structure 120 may include a second gate insulating layer 120a and a second gate electrode layer 120b formed on the second gate insulating layer 120a.

[0029] The first sub-gate insulating layer 111a of the first gate structure 110 of the first transistor T1 and the second gate insulating layer 120a of the second gate structure 120 of the second transistor T1 may belong to the same patterned film layer. That is, the first sub-gate insulating layer 111a and the second gate insulating layer 120a may be manufactured in the same manufacturing process, so that the first thickness H1 of the first sub-gate insulating layer 111a is substantially equal to the third thickness H3 of the second gate insulating layer 120a, for example, less than or equal to 25 angstroms.

[0030] The third device region R3 may be a high voltage region, and the third transistor T3 may be an input / output transistor. The third transistor T3 may include a third gate structure 130, a source region 133, and a drain region 134. The third gate structure 130 is disposed on the substrate 101 and is located between the source region 133 and the drain region 134. The source region 133 and the drain region 134 may be formed in the well region 135. The third gate structure 130, the source region 133, and the drain region 134 may be used as a gate G3, a source S3, and a drain D3, respectively, via plug contacts (not shown) to receive an external applied voltage. The third gate structure 130 may include a third gate insulating layer 130a and a third gate electrode layer 130b formed on the third gate insulating layer 130a.

[0031] The second sub-gate insulating layer 112a of the first gate structure 110 of the first transistor T1 and the third gate insulating layer 130a of the third gate structure 130 of the third transistor T3 may belong to the same patterned film layer. That is, the second sub-gate insulating layer 112a and the third gate insulating layer 130a may be manufactured in the same manufacturing process, so that the second thickness H2 of the second sub-gate insulating layer 112a is substantially equal to the fourth thickness H4 of the third gate insulating layer 130a, for example, less than or equal to 40 angstroms.

[0032] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor structure 300 according to yet another embodiment of the present invention. Figure 3 The semiconductor structure 300 of the embodiment is largely similar to Figure 1 The semiconductor structure 100 of the embodiment is different in the gate structure 210 of the transistor T1'. The gate structure 210, source region 113 and drain region 114 of the transistor T1' can be used as gate G1', source S1 and drain D1 respectively through plug contacts (not shown) to receive external applied voltage.

[0033] The gate structure 210 may include a first sub-gate structure 211 and a second sub-gate structure 212. The first sub-gate structure 211 is adjacent to the source region 113; correspondingly, the second sub-gate structure 212 is adjacent to the drain region 114. In addition, the first sub-gate structure 211 and the second sub-gate structure 212 are separated from each other. The first sub-gate structure 211 may include a first sub-gate insulating layer 211a and a first sub-gate electrode layer 211b formed on the first sub-gate insulating layer 211a. The second sub-gate structure 212 may include a second sub-gate insulating layer 212a and a second sub-gate electrode layer 212b formed on the second sub-gate insulating layer 212a.

[0034] Similar to Figure 1In the transistor T1 of the embodiment, the second thickness H2' of the second sub-gate insulating layer 212a may be greater than the first thickness H1' of the first sub-gate insulating layer 211a. In addition, the first thickness H1' of the first sub-gate insulating layer 211a may be greater than Figure 1 In the embodiment, the first thickness H1 and the second thickness H2′ of the second sub-gate insulating layer 212a may be greater than Figure 1 The second thickness H2 in the embodiment. Therefore, compared with Figure 1 The transistor T1 and the transistor T1 ′ of the embodiment can withstand a higher voltage value.

[0035] Here, the substrate 101 may have a recess R recessed from the upper surface 101u. The lower surface F1' of the first sub-gate insulating layer 211a may be located on the upper surface 101u of the substrate 101, and the second sub-gate insulating layer 212a may be formed in the recess R, so that the lower surface F2' of the second sub-gate insulating layer 212a is located below the upper surface 101u of the substrate 101. Therefore, the second sub-gate insulating layer 212a may have a thickness greater than Figure 1 In addition, since the recess R is formed on the substrate 101, even if the second sub-gate insulating layer 212a is thicker, there is no height difference between the second sub-gate electrode layer 212b and the first sub-gate electrode layer 211b, thus avoiding the problem of contact connection.

[0036] In one embodiment, the first thickness H1' of the first sub-gate insulating layer 211a may be the same as the thickness of the gate insulating layer in an input / output transistor, and the second thickness H2' of the second sub-gate insulating layer 212a may be thicker than the thickness of the gate insulating layer in the input / output transistor to withstand a higher voltage. For example, if the input / output transistor is an input / output element (I / O device) in the input / output region of the semiconductor structure, the first thickness H1' of the first sub-gate insulating layer 211a may be less than or equal to 40 angstroms. The second thickness H2′ of the second sub-gate insulating layer 212 a may be greater than 40 angstroms. In other embodiments, the first thickness H1′ of the first sub-gate insulating layer 211a may be the same as the thickness of the gate insulating layer in the core element in the core region of the semiconductor structure, for example, less than or equal to 25 angstroms. The second thickness H2′ of the second sub-gate insulating layer 212a may be thicker than the thickness of the gate insulating layer in the input / output transistor, for example, greater than 40 angstroms. To withstand higher voltage.

[0037] For details, please refer to Figure 4, which is a cross-sectional schematic diagram of a semiconductor structure 400 according to another embodiment of the present invention. The semiconductor structure 400 may be a composite semiconductor structure, and its substrate 101 may have at least a first device region R1' and a second device region R2'. It should be understood that, Figure 4 The relative positions of the first device region R1' and the second device region R2' are only for illustration and are not intended to limit the present invention. The device regions R1-R2 may be configured with different semiconductor devices, such as the first transistor T1 and the second transistor T2'. The configuration of the first transistor T1' has been described in Figure 3 The first transistor T1' may be a high voltage transistor, which is different from the input / output transistor or Figure 1 The transistor T1 of the embodiment, the first transistor T1 ′ can withstand a higher voltage value.

[0038] The first element region R1' and the second element region R2' may have different operating voltage ranges, respectively. In one embodiment, the second element region R2' may be a high voltage region, and the second transistor T2' may be an input / output transistor. In another embodiment, the second element region R2' may be a low voltage region, and the second transistor T2' may be a low voltage transistor, such as a core element. The second transistor T2' may include a second gate structure 220, a source region 123, and a drain region 124. The second gate structure 220 is disposed on the substrate 101 and is located between the source region 123 and the drain region 124. The source region 123 and the drain region 124 may be formed in the well region 125. The second gate structure 220, the source region 123, and the drain region 124 may be used as the gate G2', the source S2, and the drain D2, respectively, via plug contacts (not shown) to receive external applied voltages. The second gate structure 220 may include a second gate insulating layer 220 a and a second gate electrode layer 220 b formed on the second gate insulating layer 220 a .

[0039] The first sub-gate insulating layer 211a of the first gate structure 210 of the first transistor T1' and the second gate insulating layer 220a of the second gate structure 220 of the second transistor T2' may belong to the same patterned film layer. In other words, the first sub-gate insulating layer 211a and the second gate insulating layer 220a may be manufactured in the same manufacturing process, so that the first thickness H1' of the first sub-gate insulating layer 211a is substantially equal to the third thickness H3' of the second gate insulating layer 220a. For example, if the second transistor T2' is an input / output transistor, the first thickness H1' may be less than or equal to 40 angstroms. If the second transistor T2' is a core device, the first thickness H1' may be less than or equal to 25 angstroms.

[0040] Regarding the second sub-gate insulating layer 212 a of the first gate structure 210 of the first transistor T1 ′, the second sub-gate insulating layer 212 a thicker than the first thickness H1 ′ may be formed after the step of forming the recess R of the substrate 101 .

[0041] Figure 5 According to the present invention Figure 2 Flow chart of a method for manufacturing a semiconductor structure 200 according to an embodiment. Figure 6 According to the present invention Figure 4 Flow chart of a method for manufacturing a semiconductor structure 400 according to an embodiment. Figure 5 , Figure 6 The manufacturing method of the semiconductor structure 200 , 400 is briefly described. It should be understood that the manufacturing method of the semiconductor device 200 , 400 may also include other steps existing in the art.

[0042] Please refer to Figure 5 , Figure 6 As shown in step S501, a substrate 101 is provided, and the substrate has at least a first device region R1, R1' and a second device region R2, R2'. Next, as shown in step S502, first transistors T1, T1' and second transistors T2, T2' are formed in the first device region R1, R1' and the second device region R2, R2' of the substrate 101, respectively. The first gate structure 110, 210 of the first transistor T1, T1' includes a first sub-gate structure 111, 211 and a second sub-gate structure 112, 212 separated from each other. The first sub-gate insulating layer 111a, 211a of the first sub-gate structure 111, 211 has a first thickness H1, H1', ​​and the second sub-gate insulating layer 112a, 212a of the second sub-gate structure 112, 212 has a second thickness H2, H2'. The second thickness H2, H2' is greater than the first thickness H1, H1'. The second gate structure 120, 220 of the second transistor T2, T2' comprises a second gate insulating layer 120a, 220a. The first sub-gate insulating layer 111a, 211a and the second gate insulating layer 120a, 220a are formed by patterning the same gate insulating material layer.

[0043] Please refer to Figure 6 The method further includes step S503 of forming a third transistor T3 in the third device region R3 of the substrate 101. The third gate structure 130 of the third transistor T3 includes a third gate insulating layer 130a. The second sub-gate insulating layer 112a and the third gate insulating layer 130a are formed by patterning the same gate insulating material layer.

[0044] As described above, the present invention forms a thicker thickness in the second sub-gate insulating layer closer to the drain region to prevent the second sub-gate insulating layer from being broken due to high voltage and thus having an adverse effect on the device characteristics; and forms a thinner thickness in the first sub-gate insulating layer farther from the drain region, thereby maintaining the desired switching current and better gate control capability, thereby improving the electrical performance of the device. In addition, the first sub-gate insulating layer and the second sub-gate insulating layer are separated from each other and are made separately, avoiding the problem of contact connection between the first sub-gate electrode layer and the second sub-gate electrode layer.

[0045] In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A source region is located in the substrate; A drain region is located in the substrate; as well as The gate structure is disposed on the substrate and located between the source region and the drain region, comprising: A first sub-gate structure, adjacent to the source region, the first sub-gate structure comprising a first sub-gate insulating layer; and A second sub-gate structure, adjacent to the drain region, the second sub-gate structure comprising a second sub-gate insulating layer, the second sub-gate insulating layer being separated from the first sub-gate insulating layer; The first sub-gate insulating layer has a first thickness, the second sub-gate insulating layer has a second thickness, and the second thickness is greater than the first thickness.

2. The semiconductor structure according to claim 1, wherein: The invention also comprises a connection area which is located in the substrate and connected to the first sub-gate insulating layer and the second sub-gate insulating layer.

3. The semiconductor structure according to claim 2, wherein: It also includes a well region located in the substrate, the source region, the drain region and the connection region are located in the well region, wherein the well region has a first conductivity type, and the source region, the drain region and the connection region have a second conductivity type different from the first conductivity type.

4. The semiconductor structure according to claim 3, characterized in that It also includes a drift region located in the well region, the drain region is located in the drift region, the second sub-gate structure is located at the boundary between the well region and the drift region, and the drift region has the second conductivity type.

5. The semiconductor structure according to claim 1, wherein: The substrate has an upper surface extending horizontally, and the lower surface of the first sub-gate insulating layer and the lower surface of the second sub-gate insulating layer are located on the upper surface of the substrate.

6. The semiconductor structure according to claim 1, wherein: The substrate has a horizontally extending upper surface and a recessed portion recessed from the upper surface. The lower surface of the first sub-gate insulating layer is located on the upper surface of the substrate. The second sub-gate insulating layer is formed in the recessed portion so that the lower surface of the second sub-gate insulating layer is located below the upper surface of the substrate.

7. A semiconductor structure, characterized in that: include: A substrate having a first device region and a second device region; A first transistor is formed in the first device region of the substrate and includes a first gate structure, wherein the first gate structure includes a first sub-gate insulating layer and a second sub-gate insulating layer separated from each other, wherein the first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness, wherein the second thickness is greater than the first thickness; as well as The second transistor is formed in the second device region of the substrate and includes a second gate structure. The second gate structure includes a second gate insulating layer. The second gate insulating layer has a third thickness, and the third thickness is substantially equal to the first thickness.

8. The semiconductor structure according to claim 7, wherein: The first sub-gate insulating layer and the second gate insulating layer belong to the same patterned film layer.

9. The semiconductor structure according to claim 7, wherein: The first transistor is a high voltage transistor, and the second transistor is a low voltage transistor.

10. The semiconductor structure according to claim 9, wherein: The third thickness of the second gate insulating layer of the low voltage transistor is less than or equal to 25 angstroms 11. The semiconductor structure according to claim 7, wherein: The first transistor is a high voltage transistor, and the second transistor is an input / output transistor.

12. The semiconductor structure according to claim 11, wherein: The third thickness of the second gate insulating layer of the input / output transistor is less than or equal to 40 angstroms 13. The semiconductor structure according to claim 11, wherein: The second thickness of the second sub-gate insulating layer of the first transistor is greater than 40 angstroms 14. The semiconductor structure according to claim 7, wherein: The substrate also has a third component area, and the semiconductor structure also includes a third transistor formed in the third component area of ​​the substrate and includes a third gate structure. The third gate structure includes a third gate insulation layer, and the third gate insulation layer has a fourth thickness, which is approximately equal to the second thickness.

15. The semiconductor structure according to claim 14, wherein: The second sub-gate insulating layer and the third gate insulating layer belong to the same patterned film layer.

16. The semiconductor structure according to claim 14, wherein: The second transistor is a low voltage transistor, and the third transistor is an input / output transistor.

17. The semiconductor structure according to claim 16, wherein: The third thickness of the second gate insulating layer of the low voltage transistor is less than or equal to 25 angstroms and the fourth thickness of the third gate insulating layer of the input / output transistor is less than or equal to 40 angstroms 18. The semiconductor structure according to claim 7, wherein: The first transistor also includes a source region, a drain region and a connection region, which are located in the substrate. The first sub-gate insulating layer is adjacent to the source region, the second sub-gate insulating layer is adjacent to the drain region, and the connection region is connected to the first sub-gate insulating layer and the second sub-gate insulating layer.

19. The semiconductor structure according to claim 18, wherein: The first transistor also includes a well region located in the substrate, the source region, the drain region and the connection region are located in the well region, wherein the well region has a first conductivity type, and the source region, the drain region and the connection region have a second conductivity type different from the first conductivity type.

20. The semiconductor structure according to claim 19, wherein: The first transistor further includes a drift region located in the well region, the drain region is located in the drift region, and the second sub-gate insulating layer is located at a boundary between the well region and the drift region, wherein the drift region has the second conductivity type.

21. The semiconductor structure according to claim 7, wherein: The substrate has a horizontally extending upper surface. The lower surfaces of the first sub-gate insulating layer and the second sub-gate insulating layer are substantially coplanar with the upper surface of the substrate when viewed horizontally on a cross section perpendicular to the upper surface of the substrate.

22. The semiconductor structure according to claim 7, wherein: The substrate has a horizontally extending upper surface, the lower surface of the first sub-gate insulating layer is substantially coplanar with the upper surface of the substrate when viewed horizontally on a cross-section perpendicular to the upper surface of the substrate, and the lower surface of the second sub-gate insulating layer is substantially lower than the upper surface of the substrate when viewed horizontally on a cross-section perpendicular to the upper surface of the substrate.

23. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first device region and a second device region; as well as A first transistor and a second transistor are formed in the first element region and the second element region of the substrate respectively, the first transistor includes a first gate structure, the first gate structure includes a first sub-gate insulation layer and a second sub-gate insulation layer separated from each other, the first sub-gate insulation layer has a first thickness, the second sub-gate insulation layer has a second thickness, the second thickness is greater than the first thickness, the second transistor includes a second gate structure, the second gate structure includes a second gate insulation layer, wherein the first sub-gate insulation layer and the second gate insulation layer are formed by patterning the same gate insulation material layer.

24. The method for manufacturing a semiconductor structure according to claim 23, wherein: Also includes: A third transistor is formed in a third device region of the substrate. The third transistor includes a third gate structure. The third gate structure includes a third gate insulating layer. The second sub-gate insulating layer and the third gate insulating layer are formed by patterning the same gate insulating material layer.

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