Semiconductor light emitting device, bonded structure, and method for manufacturing

Abstract

Provided is a semiconductor light-emitting device having a structure in which a sub-mounting substrate on which a light-emitting element is mounted is ultrasonically bonded to a metal substrate, the semiconductor light-emitting device having a highly reliable bonding surface. The light-emitting device includes a light-emitting element, a ceramic sub-mounting substrate on which the light-emitting element is mounted, and a metal mounting substrate on which the sub-mounting substrate is mounted. The sub-mounting substrate is provided with a metal layer on a bonding surface bonded to the mounting substrate. The metal layer of the sub-mounting substrate and the mounting substrate are directly bonded without a bonding material therebetween. The joining surface contains pores. The content ratio of the voids in the joining surface is greater in the central region than in the peripheral region in the main plane.

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting device having a structure in which a submount substrate carrying a semiconductor light emitting element is directly bonded to a metal substrate. Background Art

[0002] In the past, there is a known semiconductor light-emitting device in which a submount substrate having a light-emitting element bonded to a chip is mounted on a metal mounting substrate having excellent thermal conductivity. As a submount substrate, a metal layer is usually provided on the upper and lower surfaces of a ceramic substrate such as aluminum nitride. The metal mounting substrate has a wiring pattern formed on the surface of the metal substrate through an insulating layer. When the submount substrate is mounted on the metal mounting substrate, an adhesive with high thermal conductivity (solder, metal bumps, or heat transfer adhesive with metal filler added) is used.

[0003] In the case of soldering, for example, a solder material is printed in a predetermined pattern on a metal substrate, a submount substrate is placed thereon, and a heating process (230° C. to 260° C.) is performed in a reflow furnace or the like to form a joint.

[0004] In the case of metal bump bonding, for example, gold balls of about 10 μm to 100 μm are ultrasonically bonded to a metal substrate at intervals of 10 μm to 100 μm or more, and then a submount substrate is placed on them and bump bonding is performed using ultrasound.

[0005] When bonding is performed using a silver filler resin, for example, the silver filler resin is printed on a metal substrate, a submount substrate is placed thereon, and bonding is performed by thermal curing (50° C. to 150° C., for about 2 hours).

[0006] In addition, ultrasonic bonding techniques are known for directly bonding two metal materials without using an adhesive, as described in Patent Documents 1 and 2. Patent Document 3 discloses a technique for ultrasonically bonding an electrode pad of a light-emitting element of a bare chip to a pattern electrode of a submount substrate. Patent Document 4 discloses a technique for ultrasonically bonding a cover material of a package that seals a light-emitting element to a frame.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 1999-010362

[0010] Patent Document 2: Japanese Patent Application Publication No. 2010-023052

[0011] Patent Document 3: Japanese Patent Application Publication No. 2022-065415

[0012] Patent Document 4: Japanese Patent Application Publication No. 2022-018490 Summary of the invention

[0013] Problems to be solved by the invention

[0014] When a submount substrate with a light-emitting element bonded to a chip is bonded to a metal substrate, in the case of soldering, sometimes the light-emitting surface is tilted due to the distribution of solder thickness at the joint, resulting in a defective product. In addition, when the solder thickness is thin (for example, less than 100μ), the crack resistance of the solder deteriorates, and sometimes it cannot withstand thermal shock and causes the weld to break. In addition, if the solder thickness becomes thicker, the thermal resistance increases. The light-emitting part of the light-emitting element may be contaminated by the antioxidant (flux) contained in the solder.

[0015] When the submount substrate is bonded to the metal substrate using gold bumps, the bonding portion becomes thicker. In addition, the thermal resistance increases due to the space between the bumps. In addition, gold bumps are expensive, and the device for bonding the bumps is also expensive, so there is also the problem of increased manufacturing cost.

[0016] When a resin containing metal fillers is used to bond a submount substrate to a metal substrate, the thermal conductivity of the bonding material is low, so the thermal resistance of the bonding portion becomes larger. In addition, since the resin containing metal fillers is in a liquid state, there is also a problem of deviation in the thickness of the adhesive layer and large deviation in the thermal resistance of the bonding portion. Furthermore, the thickness of the bonding portion becomes uneven in the in-plane direction, and sometimes an inclination angle is generated on the light-emitting surface, resulting in a defective product.

[0017] When the submount substrate and the metal substrate are bonded together, if ultrasonic bonding can be used, the two can be directly bonded together without requiring bonding materials, and thus problems such as a decrease in thermal conductivity at the bonded portion will not occur.

[0018] However, when ultrasonically bonding a submount substrate having a light emitting element mounted thereon to a metal substrate, a force is applied to the light emitting element when the submount substrate is pressed against the metal substrate by an ultrasonic tool, and the light emitting element may be damaged.

[0019] On the other hand, if the order of ultrasonically bonding only the submount substrate to the metal substrate and then bonding the light emitting element chip to the submount substrate is adopted, the ceramic substrate constituting the submount substrate and the metal substrate have greatly different thermal expansion coefficients, so the bonding surface between the submount substrate and the metal substrate may be broken due to high temperature heating during chip bonding of the light emitting element. In addition, the eutectic point of AuSn eutectic is higher than the temperature range in which the manufacturer guarantees the performance of the mounting substrate, so AuSn eutectic material cannot be used as a die bonding material.

[0020] In addition, even if the problem of applying force to the light-emitting element is solved, the sub-mount substrate carrying the light-emitting element is ultrasonically bonded to the metal substrate. Since the thermal expansion coefficients of the ceramic substrate and the metal substrate are very different, cracks are likely to occur on the bonding surface due to the heat generated by the light-emitting element during use.

[0021] In the ultrasonic bonding technology of Patent Document 3, since the electrode pads of the bare chip with a small bonding area are used, the pressure applied to the bare chip is also small. In the ultrasonic bonding technology of Patent Document 4, since the cover member of the semiconductor package is bonded, it is a structure that does not apply pressure to the light emitting element. Therefore, even if the technologies of Patent Documents 3 and 4 are used, the problem of applying pressure to the light emitting element or the problem of fracture or cracking of the bonding surface between the submount substrate and the metal substrate cannot be solved.

[0022] An object of the present invention is to provide a semiconductor light emitting device having a structure in which a submount substrate having a light emitting element mounted thereon is ultrasonically bonded to a metal substrate, and the reliability of the bonding surface is high.

[0023] Means for solving problems

[0024] In order to achieve the above-mentioned object, the semiconductor light-emitting device of the present invention comprises a light-emitting element, a ceramic submount substrate on which the light-emitting element is mounted, and a metal mounting substrate on which the submount substrate is mounted. The submount substrate has a metal layer on a bonding surface bonded to the mounting substrate. The metal layer of the submount substrate is directly bonded to the mounting substrate without a bonding material, and contains pores on its bonding surface. The central area within the main plane of the bonding surface has more pores than the peripheral area.

[0025] Effects of the Invention

[0026] According to the semiconductor light emitting device of the present invention, although the submount substrate carrying the light emitting element is ultrasonically bonded to the metal substrate, the central region of the bonding surface includes a void, so that thermal stress can be relaxed and reliability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 (a) and (b) are cross-sectional views of the semiconductor light emitting device according to the embodiment, and (c) is an explanatory diagram showing the distribution of voids on the bonding surface 40.

[0028] Figure 2 This is a flowchart showing the manufacturing process of the semiconductor light emitting device according to the embodiment.

[0029] Figure 3 (a) to (g) are cross-sectional views showing the manufacturing process of the semiconductor light emitting device according to the embodiment.

[0030] Figure 4 (a) is Figure 3 (d) is an enlarged view of the process, and (b) and (c) are a top view and a cross-sectional view of the fixing fixture 50.

[0031] Figure 5 It is an explanatory diagram showing pressure distribution in the ultrasonic bonding step according to the embodiment.

[0032] Figure 6 This is an explanatory diagram showing a metal joining process using ultrasonic waves.

[0033] Figure 7 (a) and (b) are images of the bonding surface of the semiconductor light emitting device according to the embodiment taken using an ultrasonic microscope, and (c) is a graph showing changes in ultrasonic reflectivity of the bonding surface of the semiconductor light emitting device according to the embodiment.

[0034] Figure 8 This is a cross-sectional photograph of a semiconductor light-emitting device according to an embodiment.

[0035] Fig. 9 (a) is a diagram illustrating a simulation model of thermal stress of a semiconductor light-emitting device according to an embodiment, (b) is a diagram showing the distribution of thermal stress of a simulation result, and (c) is a graph showing the relationship between the thermal stress relief effect and the pore content.

[0036] Fig.10 It is a cross-sectional view showing an ultrasonic bonding process according to a modification of the embodiment.

[0037] Description of Reference Numerals

[0038] 10 Light-emitting elements

[0039] 11 Component bonding materials

[0040] 20 Submount substrate

[0041] 21Ceramic substrate

[0042] 22 Wiring pattern

[0043] 23 Back metal layer

[0044] 30 Mounting substrate

[0045] 31 metal substrate

[0046] 31a Loading area

[0047] 32 Insulation layer

[0048] 33 Circuit Pattern

[0049] 40 Joint surface

[0050] 41 Central Area

[0051] 42 Peripheral area

[0052] 50 Fixing fixture

[0053] 51 Hollow

[0054] 60 Ultrasonic Tools

[0055] 61 Hollow

[0056] 71 Lead

[0057] 72 leads

[0058] 80 phosphor plate

[0059] 81 frame

[0060] 82 Sealing resin DETAILED DESCRIPTION

[0061] A semiconductor light emitting device according to one embodiment of the present invention is described below.

[0062] <<<Implementation Method>>>

[0063] <Structure of semiconductor light emitting device>

[0064] use Figure 1 The structure of the semiconductor light emitting device according to the embodiment will be described. Figure 1 (a) and (b) are cross-sectional views of the semiconductor light emitting device of this embodiment. Figure 1 (a) is an example in which the upper surface of the metal substrate 31 is a flat surface. Figure 1 (b) is an example in which a step is provided on the upper surface of the metal substrate 31 . Figure 1 (c) is an explanatory diagram showing the distribution of pores on the bonding surface.

[0065] In the semiconductor light emitting device of the present embodiment, the light emitting element 10 is bonded to a sub-mount substrate 20 whose base is a ceramic substrate, and the lower surface of the sub-mount substrate 20 is bonded to the mounting substrate 30 .

[0066] (Submount Substrate 20)

[0067] The submount substrate 20 includes a ceramic substrate 21 as a base, a pair of wiring patterns 22 arranged on the upper surface of the ceramic substrate 21, and a back metal layer 23 arranged on the entire lower surface of the ceramic substrate 21. On the wiring pattern 22 on the upper surface, a light-emitting element 10 is chip-bonded by an element bonding material 11. As the ceramic substrate 21, a ceramic substrate of a material with excellent thermal conductivity (for example, AlN, SiN, Al2O3, etc.) is used. As the back metal layer 23, it is preferably a metal film with excellent thermal conductivity and excellent adhesion to the ceramic substrate 21, and the hardness of the outermost metal is the same as or lower than the hardness of the metal substrate 31 of the mounting substrate 30. In addition, as the element bonding material 11, a conductive paste, a solder material, a eutectic bonding material such as AuSn can be used.

[0068] For example, a metal laminate film is used in which a Cu layer / N layer / Pd layer / Au layer is stacked in sequence from the ceramic substrate 21 side. The hardness of the outermost Au layer is the same as that of the metal substrate 31 of the mounting substrate 30. However, the outermost surface is not limited to the Au layer, and a metal with high corrosion resistance is preferred. As an example, in the case of a Cu layer / Ni layer / (Pd layer) / Au layer, the film thickness can be 50μm / 4μm / 0.1μm / 0.1μm, respectively.

[0069] In addition, although the ceramic substrate 21 is used here, a sapphire substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, a carbon nitride (SiC) substrate, or the like may also be used.

[0070] (Mounting substrate 30)

[0071] The mounting substrate 30 is a structure in which an insulating layer 32 is provided on the surface of a metal substrate 31 as a base, and a circuit pattern 33 is mounted thereon. The metal substrate 31 is made of a metal with excellent thermal conductivity (for example, an Al substrate or a Cu substrate). A mounting area 31a for mounting the sub-mounting substrate 20 is set on the metal substrate 31. The mounting area 31a is not provided with an insulating layer 32 and a circuit pattern 33, and the upper surface of the metal substrate 31 is exposed. The metal substrate 31 can be as follows Figure 1 The upper surface is flat as in (a), or Figure 1 As shown in (b), the upper surface of the mounting region 31 a is formed to be higher than the surrounding area by the thickness of the insulating layer 32 and the circuit pattern 33 .

[0072] The insulating layer 32 is made of a material that can insulate the circuit pattern 33 from the metal substrate 31 at a predetermined withstand voltage. The thermal conductivity of the material of the insulating layer 32 is very low compared to metals. For example, a fibrous reinforcing material called a prepreg is uniformly impregnated with a thermosetting resin such as epoxy resin, the semi-cured material is processed into a desired pattern, mounted on the metal substrate 31, and then cured to form the insulating layer 32. The circuit pattern 33 is made of a metal with low electrical resistance (e.g., Cu).

[0073] (Joint surface 40)

[0074] The submount substrate 20 is mounted on the mounting area 31a of the metal substrate 31, and the lower surface of the back metal layer 23 of the submount substrate 20 is directly bonded to the upper surface of the metal substrate 31 by ultrasonic bonding without the aid of bonding materials. That is, the metal on the lowermost surface of the back metal layer 23 of the submount substrate 20 and the metal substrate 31 are intermetallicly bonded by atomic forces between dissimilar metals without bonding materials. Here, the Au of the back metal layer 23 on the side of the submount substrate 20 is intermetallicly bonded to the Al of the metal substrate 31. That is, the interface between the bottom surface of the submount substrate 20 and the upper surface of the mounting substrate 30 constitutes a bonding surface, and specifically, the interface between the entire lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 constitutes a bonding surface.

[0075] In addition, regarding the combination of the back metal layer 23 and the metal substrate 31 on the bonding surface, as long as hard metals (such as Ni, etc.) are avoided on the outermost surface of the bonding, other metals can also be used. In addition to Al-Au bonding, for example, it can also be Al-Al bonding, Cu-Au bonding, Au-Au bonding, etc.

[0076] (Porosity)

[0077] The bonding surface 40 between the lower surface of the back metal layer 23 of the sub-mount substrate 20 and the upper surface of the metal substrate 31 is ultrasonically bonded so that minute voids are included in the bonding interface.

[0078] The pore size is preferably 5 μm or less, and particularly preferably 1 μm or less on average.

[0079] The content of pores per unit area in the joint surface 40 varies depending on the position in the main plane of the joint surface 40. The central region 41 of the joint surface 40 includes more pores than the region 42 of the peripheral portion.

[0080] Specifically, the content of pores is preferably 5% to 15% per unit area in the central region 41, and 0% to 5% per unit area in the peripheral region. It is particularly preferably 1.0% to 15% per unit area in the central region 41, and 0% to 5% per unit area in the peripheral region 42.

[0081] Furthermore, when the light emitting element 10 is viewed from above, the central region 41 includes the bottom surface region of the light emitting element 10 .

[0082] The central region 41 is preferably spaced apart from the periphery of the bonding surface 40 (periphery of the submount substrate 20 ) by a distance in a range of 5% to 30% of the vertical and horizontal dimensions of the submount substrate 20 .

[0083] The size of the pores depends on the surface roughness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 before bonding, as well as the conditions during ultrasonic bonding, so by controlling these, pores of 5 μm or less can be formed on the bonding surface. The surface roughness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 before bonding is preferably Rz(23)<5μm, Rz(31)<8μm, and particularly preferably Rz(23)<3μm, Rz(31)<5μm.

[0084] More specifically, among the surface of the back metal layer 23 of the submount substrate 20 and the surface of the metal substrate 31 before bonding in the bonding process, the surface with greater surface roughness preferably has a surface roughness Rz (maximum height) of not less than 0.5 μm and not more than 5 μm.

[0085] In order to avoid applying pressure to the light emitting element 10 during ultrasonic bonding, the size of the central region 41 containing many pores depends on the opening area of ​​the cavity provided in the fixing jig. The opening area has upper and lower limits depending on the bonding conditions such as the size of the light emitting element 10 and the size and thickness of the ceramic substrate 21. Therefore, by finding these conditions in advance, bonding can be performed in a manner that contains many pores in the central region 41 of a desired size.

[0086] The shape of the central region 41 depends on the opening shape of the cavity of the fixing jig during ultrasonic bonding, and therefore, may be formed in any shape other than a circle, such as a quadrilateral.

[0087] The opening area and shape of the fixing jig and the setting conditions during ultrasonic bonding will be described in detail later.

[0088] <Function of the Joint Surface 40>

[0089] As described above, in this embodiment, since the submount substrate 20 is directly bonded to the metal substrate 31 of the mounting substrate 30 without using a bonding material at the bonding surface 40, the thermal resistance of the bonding surface 40 can be reduced to the maximum extent. As a result, the heat generated by the light emitting element 10 can be conducted to the metal substrate 31 via the element bonding material 11, the submount substrate 20 and the bonding surface 40 and dissipated.

[0090] Since no bonding material is used on the bonding surface 40 , there is no variation in thermal resistance due to thickness distribution of the bonding material, and the heat of the light emitting element 10 can be uniformly conducted from the entire bonding surface 40 .

[0091] In addition, in the bonding surface 40, the central region 41 is configured to contain pores of more than 5% and less than 15%, and the peripheral region 42 contains pores of more than 0% and less than 5%. Therefore, even if internal stress is generated in the bonding surface 40 due to the heat of the light-emitting element 10 due to the great difference in thermal expansion coefficients between the ceramic substrate 21 and the metal substrate 31, the stress can be relieved by shrinking or expanding the pores. At this time, the central region 41 contains more pores than the peripheral region 42, so the temperature rise directly below the light-emitting element 10 is the largest, and the stress can be relieved in the region where the greatest stress is generated. In addition, the peripheral region 42 has a smaller amount of pores than the central region 41, so the contact area between the back metal layer 23 of the sub-mounting substrate 20 and the metal substrate 31 of the mounting substrate 30 is large, and the bonding strength is high. Therefore, even if thermal stress is applied, it is firmly bonded and the generation of cracks is suppressed.

[0092] Ultrasonic bonding is performed at room temperature, so no intermetallic compounds are generated on the bonding surface. In addition, since high-temperature heating is not required, there is also an advantage that the thermal influence on the light emitting element 10 during bonding is small.

[0093] <Manufacturing process of semiconductor light emitting device>

[0094] Next, a method for manufacturing the semiconductor light emitting device of this embodiment will be described.

[0095] Figure 2 is a flow chart showing the manufacturing process, Figure 3 (a) to (g) are cross-sectional views showing the manufacturing process. Figure 4 (a) is Figure 3 An enlarged view of the process (d), Figure 4 (b) and (c) are a top view and a cross-sectional view of the fixing fixture 50 . Figure 5 Indicates the pressure distribution during ultrasonic bonding. Figure 6 Indicates the metal joining process based on ultrasonic waves.

[0096] (Process S1)

[0097] First, if Figure 3 As shown in FIG. 2( a ), the light emitting element 10 is mounted (die-bonded) on the wiring pattern 22 on the upper surface of the mounting substrate 20 using AuSn eutectic as the element bonding material 11 .

[0098] (Process S2)

[0099] like Figure 3 As shown in (b) , the sub-mount substrate 20 is placed on the fixing jig 50 with the upper surface of the light emitting element 10 facing downward.

[0100] The fixing fixture 50 is provided with a hollow portion 51 in the center for accommodating the light emitting element 10, a first step portion 52 for accommodating and supporting the submount substrate 20 is provided on the outer side thereof, and a second step portion 53 for accommodating the mounting substrate 30 is further provided on the outer side thereof (see Figure 3 (b) Figure 4 (a)~(c)).

[0101] On the submount substrate 20, the light emitting element 10 has been mounted in step S1. If the submount substrate 20 is mounted on the first step portion 52 of the fixing fixture 50, the light emitting element 10 is accommodated in the cavity portion 51 and does not contact the fixing fixture 50. Figure 3 In the step S4 of step (d), the submount substrate 20 can be supported by the fixing jig 50 so that no pressure is applied to the light emitting element 10 .

[0102] Here, as the central region 41 having many pores on the bonding surface 40, in order to form a circular region (see Figure 1 (b)), the opening shape of the cavity portion 51 is set to be circular. In addition, the opening size of the cavity portion 51 needs to be set larger than the size of the light-emitting element 10. In addition, since the sub-mount substrate 20 is supported by the area of ​​the lower surface of the first step portion 52 excluding the opening of the cavity portion 51, it is necessary to ensure that the area of ​​the first step portion 52 can fully support the sub-mount substrate 20 based on the size, material, thickness, bonding conditions, etc. of the sub-mount substrate 20. Therefore, the size of the opening of the cavity portion 51 is set to be larger than the size of the light-emitting element 10 and smaller than the size that can ensure the minimum area required for the lower surface of the first step portion 52.

[0103] (Process S3)

[0104] Then, if Figure 3 As shown in (c) , the mounting substrate 30 is placed on the sub-mount substrate 20 in the fixing jig 50 .

[0105] (Process S4)

[0106] Then, if Figure 3(d) and Figure 4 As shown in (a), the ultrasonic tool 60 is brought into contact with the mounting substrate 30 on the mounting substrate 30, as shown in Figure 5 As shown, the ultrasonic tool 60 applies ultrasonic energy to the metal substrate while pressing the mounting substrate 30 in a direction pressed against the sub-mount substrate 20 .

[0107] Therefore, if Figure 6 As shown in (1), pressure and ultrasonic vibration from the ultrasonic tool 60 are applied to the metal substrate 31 of the mounting substrate 30 and the back metal layer 23 of the sub-mounting substrate 20, as shown in Figure 6 As shown in (2), friction / plastic flow occurs between the surface of the metal substrate 31 and the back metal layer 23 in contact, as shown in FIG. Figure 6 As shown in (3), the oxide film on the metal surface is repelled and the new surface of the metal is exposed. Centered on the exposed contact portion of the metal, the metal substrate 31 and the back metal layer 23 are deformed, and the contact area is increased, so that Figure 6 As shown in (4), the entire contact surface is solid-phase bonded by atomic force. This solid-phase bonding is different from melt bonding, and bonding is performed in a solid-phase state near room temperature which is much lower than the melting point of the metal material.

[0108] At this time, since the cavity 51 is provided in the fixing jig 50, the peripheral portion of the submount substrate 20 where the light emitting element 10 is not provided is supported by the first step portion 52 around the cavity 51. Figure 5 As shown by the middle arrow, at the bonding surface 40 during bonding, the pressure applied to the central area is smaller than the pressure applied to the peripheral area, resulting in a pressure distribution. Therefore, in the peripheral area 42 of the bonding surface 40, the surface unevenness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 are deformed by pressure and ultrasonic vibration, and the contact area is increased, so it is difficult to produce pores and they are firmly bonded. On the other hand, in the central area 41 of the bonding surface 40, the pressure is smaller than that of the peripheral area, so a part of the gap between the surface unevenness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 remains, forming pores.

[0109] Thus, it is possible to form the bonding surface 40 composed of the central region 41 including many pores and the peripheral region 42 including fewer pores.

[0110] It should be noted that the vibration mode of the ultrasonic tool 60 can also be linear vibration, but the ultrasonic composite vibration (circular or elliptical vibration formed by adding linear vibration to torsional vibration) vibrates in a circular shape, so it is easier to apply pressure to the outer periphery of the joining surface 40, and the outer periphery of the joining surface can be joined more firmly.

[0111] (Process S5)

[0112] Next, the mounted substrate 30 and the sub-mounted substrate 20 after bonding are taken out from the fixing jig 50. Figure 3 As shown in (e), the upper surface electrode of the light emitting element 10 is connected to one of a pair of wiring patterns 22 of the submount substrate 20 by wire bonding with a wire 71. Furthermore, the pair of wiring patterns 22 and the circuit pattern 33 on the mounting substrate 30 are respectively connected by a pair of wires 72 by wire bonding.

[0113] When the light emitting element 10 is a flip chip, the lead wires 71 are not required. When the light emitting element 10 has two upper surface electrodes, the pair of wiring patterns 22 of the sub-mount substrate 20 are connected by two lead wires 71 , respectively.

[0114] (Step S6)

[0115] Then, if Figure 3 As shown in (f) , a fluorescent plate 80 is mounted on the upper surface of the light emitting element 10 , and a light reflective frame 81 is mounted on the mounting substrate 30 at a predetermined distance from the sub-mount substrate 20 .

[0116] (Step S7)

[0117] Finally, if Figure 3 As shown in (g), a sealing resin 82 in which a light reflective filler is dispersed is filled inside the frame 81 except the upper surface of the phosphor plate 80 so as to embed the light emitting element 10 and the submount substrate 20, and is cured.

[0118] In this way, a semiconductor light emitting device can be manufactured.

[0119] In addition, steps S6 and S7 may be performed as needed.

[0120] In addition, any surface concavo-convex structure can be provided on the surface of the ultrasonic tool that contacts the mounting substrate 30 and the surface of the first step portion 52 of the fixing jig 50 that contacts the sub-mount substrate 20. Thus, ultrasonic energy can be efficiently applied to the bonding surface 40. In this case, the concavo-convex structure is transferred to each surface of the sub-mount substrate 20 or the mounting substrate 30 that contacts the concavo-convex structure.

[0121] In addition, in the semiconductor light emitting device and the manufacturing method thereof of the present embodiment, one light emitting element 10 is described, but a plurality of light emitting elements may be arranged on the submount substrate. In this case, when placing the semiconductor light emitting device on the fixing fixture in step S2, a plurality of light emitting elements may be accommodated in one cavity, and a plurality of cavity portions may be appropriately accommodated in the light emitting elements.

[0122] [Example]

[0123] As an example, a semiconductor light emitting device was manufactured by the manufacturing method of the above-mentioned embodiment.

[0124] (Mounting substrate 30)

[0125] The mounting substrate 30 uses a metal substrate 31 made of Al and having a size of 36 mm×36 mm×2.0 mmt.

[0126] (Submount Substrate 20)

[0127] As the sub-mount substrate 20 , a ceramic substrate 21 is made of AlN, the outermost surface of the back metal layer 23 is Au, and the size is 3.0 mm×4.0 mm×0.48 mm.

[0128] (Ultrasonic tools)

[0129] The material of the ultrasonic tool 60 is tool steel, and the contact area with the mounting substrate 30 is equal to or larger than the area of ​​the bonding surface 40. The surface of the ultrasonic tool 60 in contact with the mounting substrate 30 is provided with knurling (periodic fine concave-convex) as an anti-slip surface treatment.

[0130] (Fix fixture 50)

[0131] The fixing jig 50 is made of stainless steel (pre-hardened). In addition, the first step portion 52 of the support mounting substrate 20 of the fixing jig 50 may be knurled similarly to the ultrasonic tool 60 .

[0132] The diameter φ of the opening of the cavity 51 of the fixing jig 50 is 1.8 mm. The size of the light emitting element 10 is approximately 1 mm square.

[0133] (Joining conditions)

[0134] The ultrasonic mode was set to composite vibration, and the settings were as follows: frequency: 20 kHz, static pressure: 2000 N or less, oscillation time: 2.0 seconds or less, AMPL (current ratio equivalent to vibration amplitude): 100% or less.

[0135] Specifically, the settings are as follows: frequency: 20 kHz, AMPL: 10% to 80% (0% to 100%), static pressure: 100 N to 1000 N (0 N to 2000 N), and oscillation time: 0.1 second to 2.0 seconds (0 second to 5.0 seconds).

[0136] <Cross-sectional Photograph of Joining Surface 40>

[0137] Figure 8 (a) and Figure 8 (b) shows a cross-sectional photograph of the bonding surface 40 obtained in the example.

[0138] Figure 8 (a) is a cross-sectional view of a bonding surface obtained by ultrasonically bonding an Al substrate as the metal substrate 31 and a Cu / Ni / Pd / Au laminated film (outermost surface: Au layer) as the back metal layer 23 .

[0139] according to Figure 8 (a), the surface of the metal substrate (Al substrate) 31 has a bonding surface similar to the surface unevenness of the Au layer of the back metal layer 23 as the bonding object. It can be seen that in ultrasonic bonding, a bonding surface is formed along the surface shape of the side with greater hardness (Au layer of the back metal layer 23). Therefore, in the case where the surface unevenness of the side with greater hardness is too large in the bonding surface, it is believed that the side with less hardness cannot completely follow its surface shape and generate pores.

[0140] Figure 8 (b) is a cross-sectional view of the bonding surface obtained by ultrasonically bonding a Cu substrate with Au / Pd / Ni laminated on the surface (outermost Au layer) as the metal substrate 31 and a back metal layer 23 using a Cu / Ni / Pd / Au laminated film (outermost: Au layer).

[0141] The surface of both sides of the bonding surface is Au layer, so the bonding surface is formed by the reconstruction of Au metal in the plane. Figure 8 (b) Through the surface reconstruction of the Au metal, the bonding surface is not a simple surface, and the lower surface of the Au layer of the back metal layer 23 and the upper surface of the Au layer of the metal substrate 31 are alternately contacted and non-contacted, and the non-contacted parts become pores.

[0142] Depend on Figure 8 (b) It can be confirmed that micropores of 5 μm or less and about 1 μm are formed.

[0143] <Method for Confirming Porosity Distribution>

[0144] Here, a method for obtaining the amount of voids on the bonding surface of a semiconductor light-emitting device will be described.

[0145] When an image of the bonding surface 40 is taken from the upper surface of the light emitting element 10 by an ultrasonic microscope (C-SAM: Constant-depth mode Scanning Acoustic Microscorpe), the ultrasonic microscope image becomes an image in which the bonding portion without pores on the bonding surface 40 is black (low reflectivity) and the bonding portion with pores is white (high reflectivity) (refer to Figure 7 Thus, the pore volume can be calculated based on the grayscale of the ultrasonic microscope image. Figure 7(b) is an image of the bonding surface 40 with adjusted grayscale. It can be seen that the central area is whiter than the peripheral area and has a larger amount of pores.

[0146] Figure 7 (c) is to be based on Figure 7 The ultrasonic reflectivity of the bonding surface 40 obtained by the grayscale of (a) is plotted as a graph. The ultrasonic reflectivity of the outer side of the bonding surface, that is, the interface region with the air, is 100%, and it is therefore considered that the ultrasonic reflectivity in the bonding surface represents the surface density of the pores. Figure 7 As can be seen from the graph (c), the reflectivity of the central area of ​​the bonding surface is significantly lower than that of the peripheral area, and voids are distributed.

[0147] in addition, Figure 7 The ultrasonic reflectivity of the central region 41 of (c) is 5% to 10%, and the surface density of the pores in the central region 41 can be assumed to be 5% to 10%.

[0148] <Thermal stress simulation results>

[0149] Here, it was confirmed through simulation that the thermal stress of the joint surface 40 can be alleviated by including 5% to 15% of pores per unit area in the central region 41 of the joint surface 40 .

[0150] A model of a semiconductor light emitting element in which pores with a size (width) of 1 μm are arranged at equal intervals at a ratio of 5%, 10%, and 15% per unit area in the central region 41 of the bonding surface 40 and no pores are arranged in the peripheral region 42 ( Fig. 9 (a)) The thermal stress distribution at Ta = 150°C (Ta: T [atmosphere], ambient temperature (around the joint)) was calculated using a two-dimensional simplified model. The calculation was performed using a known analysis simulation software (Femted (registered trademark), manufactured by Murata Manufacturing Co., Ltd.). Fig. 9 (b) shows the calculation result.

[0151] In addition, as a comparative example, the thermal stress distribution was also calculated for a model in which both the central region 41 and the peripheral region 42 contained no voids (0%). The results are shown in FIG. Fig. 9 (b).

[0152] in addition, Fig. 9 The diagram of (c) Fig. 9 The value of the thermal stress at the end of the joint surface 40 is shown in the thermal stress distribution (b). Fig. 9 (c) shows that the thermal stress of the model containing pores in the central region 41 at a ratio of 5%, 10%, and 15% according to the present embodiment is significantly reduced compared to the comparative example without pores (0%). In addition, the greater the pore content, the more the thermal stress is reduced.

[0153] Therefore, it was confirmed that the thermal stress was reduced by forming a structure of the bonding surface 40 in which microscopic pores of a degree that did not have a significant effect on heat conduction were formed in the central region 41 of the bonding surface 40 and no pores were formed in the peripheral portion. Thus, the generation of cracks in the peripheral portion of the bonding surface 40 caused by thermal shock was suppressed, and reliability was improved.

[0154] It should be noted that if the central region 41 containing pores is further widened, it is foreseeable that stress will be further relaxed, but since the peripheral region 42 is reduced, the bonding strength of the peripheral portion is reduced, and the pores in the peripheral portion may promote the generation of cracks. That is, there is a trade-off relationship between stress relaxation and cracks generated at the outermost periphery of the joint surface 40, so the area size of the central region 41 is preferably set to a range that can take into account both the stress relaxation amount and the bonding strength of the outermost periphery. In addition, if the pore ratio of the central region 41 is considered not to affect the thermal resistance, the ratio of pores per unit area is preferably less than about 30%, and more preferably less than about 15%.

[0155] The inventors have experimentally confirmed that even if there is a cavity directly below the element, the thermal resistance does not change significantly when a bonding area of ​​70% or more can be ensured.

[0156] In addition, according to the inventor's experiments, it is the size of the pores that affects the thermal resistance. Even if the pore ratio of pores with a size of 10 μm or less in the central region 41 is large, it will not have a great impact on the thermal resistance. However, when the pore ratio in the central region 41 increases, large pores are likely to be generated. Therefore, as described above, the ratio of pores per unit area is preferably less than about 30%, and more preferably less than about 15%.

[0157] <<Modifications>>

[0158] In the above embodiment, Figure 2 In the ultrasonic bonding step of step S4 of the process, Figure 3 (d) Figure 4 As shown in (a), the ultrasonic tool 60 is pressed against the back side of the mounting substrate 30 to apply ultrasonic vibration to the mounting substrate 30, but as a modified example, it can also be as follows Fig.10 As shown, the ultrasonic tool 60 is pressed against the upper surface of the sub-mount substrate 20 .

[0159] In this case, the ultrasonic tool 60 is provided with a cavity 61 for accommodating the light emitting element 10 so that the ultrasonic tool 60 does not come into contact with the light emitting element 10 .

[0160] The fixing jig 50 only needs to be provided with a recessed portion that supports the mounting substrate 30 .

[0161] With Figure 4 Compared with the case where a larger mounting substrate 30 is vibrated as in the ultrasonic bonding of (a), the modified example Fig.10 The ultrasonic bonding process only requires vibrating the smaller submount substrate 20, so it can be more Figure 4 (a) The small ultrasonic energy minimizes damage to the submount substrate 20 and bonds the bonding surface 40. Thus, even when the mounting substrate 30 is thick, ultrasonic energy can be efficiently applied to the bonding surface without attenuating the ultrasonic energy.

[0162] The technology of the semiconductor light emitting device of this embodiment can be used for a lamp light source unit or a white light source module.

Claims

1. A semiconductor light emitting device, characterized in that: The semiconductor light emitting device comprises: a light emitting element; a submount substrate on which the light emitting element is mounted; and a metal mounting substrate on which the submount substrate is mounted. The sub-mount substrate has a metal layer on a bonding surface with the mounting substrate. The metal layer of the submount substrate is directly bonded to the mounting substrate without a bonding material, and a gap is included in the bonding surface. The content of pores per unit area in the bonding surface is greater in a central region within a principal plane of the bonding surface than in a peripheral region.

2. The semiconductor light emitting device according to claim 1, characterized in that: The surface density of the pores is 5% or more and 15% or less in the central region, and is 5% or less in the peripheral region.

3. The semiconductor light emitting device according to claim 1, characterized in that: When the light emitting element is viewed from above, the central area is larger than a bottom area of ​​the light emitting element.

4. The semiconductor light emitting device according to claim 1, characterized in that: The size of the pores is 5 μm or less.

5. The semiconductor light emitting device according to claim 1, characterized in that: The metal layer provided on the bonding surface of the sub-mount substrate to be bonded to the mounting substrate has a hardness lower than that of the metal mounting substrate.

6. The semiconductor light emitting device according to claim 1, characterized in that: The metal mounting substrate is made of Al, Cu or an alloy thereof. The submount substrate has a ceramic substrate as a base, and the ceramic substrate is made of any one of AlN, SiN, and Al2O3. The metal layer is formed on a bonding surface of the ceramic substrate to be bonded to the mounting substrate, and the metal layer is an Au layer.

7. A joint structure, characterized in that: The joint structure comprises: a ceramic substrate having a metal layer formed on one surface; and a metal substrate joined to the surface of the ceramic substrate having the metal layer formed thereon. The metal layer of the ceramic substrate is directly bonded to the metal substrate without a bonding material, and pores are included in the bonding surface. The content of pores per unit area in the bonding surface is greater in a central region within a principal plane of the bonding surface than in a peripheral region.

8. A method for manufacturing a semiconductor light emitting device, characterized in that: It has the following processes: a step of arranging a submount substrate having a light emitting element mounted on an upper surface and a metal layer on a lower surface so as to overlap with a metal mounting substrate, the mounting substrate being arranged on the lower surface side of the submount substrate; and In the bonding process, an ultrasonic tool is pressed against the upper surface of the sub-mounting substrate or the lower surface of the mounting substrate, and the ultrasonic tool is ultrasonically vibrated while pressing the peripheral area of ​​the sub-mounting substrate with a force greater than that of the central area, thereby directly bonding the bonding surface to the metal layer of the sub-mounting substrate and making the central area of ​​the bonding surface contain pores.

9. The method for manufacturing a semiconductor light emitting device according to claim 8, characterized in that: In the bonding step, the surface of the metal layer of the submount substrate and the surface of the metal mounting substrate having a larger surface roughness have a surface roughness Rz, that is, a maximum height of 0.5 μm to 5 μm.

10. The method for manufacturing a semiconductor light emitting device according to claim 9, characterized in that: In the bonding step, a film thickness of the metal layer of the sub-mount substrate before bonding is larger than a value of Rz of the surface roughness.

11. The method for manufacturing a semiconductor light emitting device according to claim 8, characterized in that: In the configuration step, the submount substrate is mounted on a fixing jig in such a manner that the light emitting element is located below the submount substrate, and the mounting substrate is mounted on the submount substrate in such a manner that the upper surface of the mounting substrate contacts the submount substrate. The bonding step is a step of applying ultrasonic vibration by pressing the ultrasonic tool from above the mounting substrate supported by the fixing jig. The fixing jig is provided with a hollow portion for preventing the light emitting device from contacting the fixing jig.

12. The method for manufacturing a semiconductor light emitting device according to claim 8, characterized in that: In the configuration step, the mounting substrate is mounted on a fixing jig, and the sub-mount substrate is mounted on the mounting substrate. The bonding step is a step of applying ultrasonic vibration by pressing the ultrasonic tool from the upper surface of the submount substrate. The ultrasonic tool is provided with a cavity portion for preventing the light emitting device from contacting the ultrasonic tool.

13. The method for manufacturing a semiconductor light emitting device according to claim 11, characterized in that: The opening size of the cavity portion of the fixing fixture is larger than the size of the light emitting element.

Images