Voltage output circuit and battery management system

Abstract

The embodiment of the invention provides a voltage output circuit and a battery management system, and the voltage output circuit comprises a first switch module which comprises a first transistor and a second transistor; the switch control module is used for controlling the control end voltage of the first transistor and the second transistor so as to control the first transistor and the second transistor to be switched on or switched off; wherein the first transistor and the second transistor are N-type transistors, in the process that the switch control module controls the first transistor and the second transistor, the control end voltage of the first transistor changes along with the first input voltage, and the control end voltage of the second transistor changes along with the first output voltage. The area of the first transistor and the area of the second transistor can be reduced while small on-resistance of the transistors is guaranteed, and therefore the area of the voltage output circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a voltage output circuit and a battery management system. Background Art

[0002] At present, batteries are core components of new energy vehicles, power tools, drones, industrial robots, consumer electronics and other products. It is necessary to accurately monitor the battery voltage to ensure the normal operation of electronic equipment. In related technologies, battery voltage measurement is usually performed using a voltage output circuit (or a high-voltage transmission gate) and an analog-to-digital converter, wherein the voltage output circuit can transmit the voltage of a certain battery section of the high voltage, and the analog-to-digital converter can measure the voltage of a certain battery section transmitted by the voltage output circuit, thereby obtaining the voltage measurement data of a certain battery section according to the conversion result of the analog-to-digital converter.

[0003] In the related art, the voltage output circuit usually uses an LDMOS tube (Laterally Diffused Metal Oxide Semiconductor) to control whether to output the voltage of a certain battery. Although the LDMOS tube can withstand high voltage between the drain and the source (for example, the voltage difference between the drain and the source can be as high as 60V), the gate and the source of the LDMOS tube generally cannot withstand high voltage (for example, the voltage difference between the drain and the source is generally 5V to 6V). Therefore, when the gate voltage of the LDMOS tube needs to be designed with special care, the current traditional voltage output circuit usually uses an LDPMOS tube for battery voltage transmission control.

[0004] However, since the carrier mobility of a P-type transistor is generally 1 / 3 to 1 / 2 of that of an N-type transistor, in order to ensure a smaller on-resistance, a conventional voltage output circuit generally requires a larger LDPMOS transistor to be designed, which results in an increase in the area of ​​the voltage output circuit. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a voltage output circuit and a battery management system to solve the above technical problems.

[0006] In a first aspect, an embodiment of the present application provides a voltage output circuit, comprising:

[0007] A first switch module, the first switch module includes a first transistor and a second transistor, the second end of the first transistor and the second end of the second transistor are connected to each other, the first end of the first transistor is used to access a first input voltage, and the second end of the second transistor is used to output a first output voltage;

[0008] A switch control module, the switch control module is used to control the control terminal voltage of the first transistor according to the first input voltage feedback, and to control the control terminal voltage of the second transistor according to the first output voltage feedback, so as to control the first transistor and the second transistor to be turned on or off;

[0009] Among them, the first transistor and the second transistor are N-type transistors. In the process of the switch control module controlling the first transistor and the second transistor, the control terminal voltage of the first transistor follows the first input voltage change, and the control terminal voltage of the second transistor follows the first output voltage change. The voltage difference between the control terminal voltage of the second transistor and the first output voltage is greater than the threshold voltage of the second transistor and less than the maximum gate-source voltage of the second transistor.

[0010] In a second aspect, the present application provides a battery management system, comprising:

[0011] Multiple battery cells connected in series;

[0012] The voltage output circuit as described in the first aspect, the voltage output circuit is used to control the battery voltage output of at least one battery unit;

[0013] Analog-to-digital converter, the analog-to-digital converter is used to perform analog-to-digital conversion on the output voltage provided by the voltage output circuit.

[0014] The present application allows the first end of the first transistor to be connected to the first input voltage, and in the process of the switch control module controlling the first transistor and the second transistor to be turned on, the second end of the second transistor can output the first output voltage. Since the control end voltage of the second transistor changes with the first output voltage when the switch control module controls the first transistor and the second transistor to be turned on, the voltage difference between the control end voltage of the second transistor and the first output voltage is greater than the threshold voltage of the second transistor and less than the maximum gate-source voltage of the second transistor, so that not only the second transistor can be turned on, but also the phenomenon of damage caused by excessive voltage difference between the control end and the first end of the second transistor can be avoided. At the same time, since the first transistor and the second transistor are N-type transistors, compared with the voltage output circuit of the traditional voltage output circuit using P-type transistors, the present application can also reduce the area of ​​the first transistor and the second transistor while ensuring a smaller on-resistance of the transistor, thereby facilitating the reduction of the area of ​​the voltage output circuit.

[0015] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A circuit diagram of a high-voltage transmission gate in the related art is shown.

[0018] Figure 2 A schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0019] Figure 3 A schematic diagram showing a change of the control terminal voltage of the second transistor and the first output voltage in an embodiment of the present application is shown.

[0020] Figure 4 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0021] Figure 5 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0022] Figure 6 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0023] Figure 7 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0024] Figure 8 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0025] Fig. 9 A schematic diagram showing a change of the control terminal voltage and the second output voltage of the fourth transistor in the embodiment of the present application is shown.

[0026] Fig.10 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0027] Fig.11 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0028] Fig.12 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0029] Fig.13 Another schematic diagram of a voltage output circuit in an embodiment of the present application is shown.

[0030] Fig.14A schematic diagram of a battery management system in an embodiment of the present application is shown.

[0031] Among them, 100 voltage output circuit, 200 battery unit, 300 analog-to-digital converter, 10 first switch module, 20 switch control module, 21 first current source unit, 22 first impedance unit, 23 first voltage clamping unit, 24 second impedance unit, 25 second current source unit, 26 third impedance unit, 27 second voltage clamping unit, 28 fourth impedance unit, 30 second switch module;

[0032] A first input voltage Vcn, a first output voltage Voutp, a second input voltage Vcn-1, a second output voltage Voutn, a control terminal voltage Vc_M1 of the first transistor, a control terminal voltage Vc_M2 of the second transistor, a control terminal voltage Vc_M3 of the third transistor, a control terminal voltage Vc_M4 of the fourth transistor, a second terminal voltage Vdrp of the first impedance unit, a second terminal voltage Vdrn of the third impedance unit, a first preset voltage Vbat, a first current I1, a second current I2, a third current I3, a fourth current I4, a first control signal EN, a first bias voltage BN, and a second control signal ENN;

[0033] A first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a first node m1, and a second node m2. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0035] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0036] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0037] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0038] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0039] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0040] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0041] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0042] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain.

[0043] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0044] At present, the high-voltage transmission gate usually uses LDPMOS tube to control whether to output voltage, for example, see Figure 1 , Figure 1 A circuit diagram of a high-voltage transmission gate in the related art is shown, and the high-voltage transmission gate includes a PMOS tube MP1, a PMOS tube MP2, a voltage-dividing resistor R01, a voltage-dividing resistor R02 and an NMOS tube MN1. The sources of the PMOS tube MP1 and the PMOS tube MP2 are connected to each other, the drain of the PMOS tube MP1 is connected to the input voltage Vin, and the drain of the PMOS tube MP2 is used to provide an output voltage Vout. The voltage-dividing resistor R01 and the voltage-dividing resistor R02 are connected in series, and the gates of the PMOS tube MP1 and the PMOS tube MP2 are connected to a node M0. The control signal VC controls the voltage of the node M0 through the NMOS tube MN1, thereby realizing the control of turning on and off the PMOS tube MP1 and the PMOS tube MP2.

[0045] Specifically, when the NMOS tube MN1 is in the cut-off state, the voltage of the node M0 is equivalent to the input voltage Vin, and the source voltage and gate voltage of the PMOS tube MP1 and the PMOS tube MP2 are equivalent, so the high-voltage transmission gate does not provide the output voltage Vout; and when the control signal VC controls the NMOS tube MN1 to be turned on, the voltage of the node M0 under the voltage division of the voltage-dividing resistor R01, the voltage-dividing resistor R02 and the NMOS tube MN1 is: V_M0=Vin*(R02+Ron) / (R01+R02+Ron), Ron is the resistance when the NMOS tube MN1 is turned on, so the voltage difference between the source and gate voltage of the PMOS tube MP1 and the PMOS tube MP2 will exceed their threshold voltage, and the PMOS tube MP1 and the PMOS tube MP2 will be turned on, and finally the high-voltage transmission gate will provide the output voltage Vout.

[0046] However, since the carrier mobility of a P-type transistor is generally 1 / 3 to 1 / 2 of that of an N-type transistor, in order to ensure a smaller on-resistance, a conventional voltage output circuit generally requires a larger LDPMOS transistor to be designed, which results in an increase in the area of ​​the voltage output circuit.

[0047] To this end, the present application provides a voltage output circuit and a battery management system, which are described in detail below.

[0048] First, see Figure 2 , Figure 2 A schematic diagram of a voltage output circuit 100 in an embodiment of the present application is shown, wherein the voltage output circuit 100 includes a first switch module 10 and a switch control module 20 .

[0049] Specifically, the first switch module 10 can control whether the first input voltage Vcn connected thereto is output in response to the control of the switch control module 20. The first switch module 10 includes a first transistor M1 and a second transistor M2, the second end of the first transistor M1 and the second end of the second transistor M2 are connected to each other, the first end of the first transistor M1 is used to connect the first input voltage Vcn, and the first end of the second transistor M2 is used to output the first output voltage Voutp. When the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned on, the second end of the second transistor M2 can output the first output voltage Voutp.

[0050] The switch control module 20 is used to control the control terminal voltage Vc_M1 of the first transistor M1 and the control terminal voltage Vc_M2 of the second transistor M2, so as to control the first transistor M1 and the second transistor M2 to be turned on or off. Specifically, the switch control module 20 can feedback control the control terminal voltage Vc_M1 of the first transistor M1 according to the first terminal voltage of the first transistor M1 (i.e., the first input voltage Vcn), so as to ensure that the voltage difference between the gate and the source of the first transistor M1 is greater than the threshold voltage of its conduction when the first transistor M1 is turned on, and finally the first transistor M1 is in the on state; at the same time, the switch control module 20 can feedback control the control terminal voltage Vc_M2 of the second transistor M2 according to the first terminal voltage of the second transistor M2 (i.e., the first output voltage Voutp), so as to ensure that the voltage difference between the gate and the source of the second transistor M2 is greater than the threshold voltage of its conduction when the second transistor M2 is turned on, and finally the first transistor M1 is in the on state.

[0051] Exemplarily, the switch control module 20 may include a BOOST boost circuit so as to generate a control terminal voltage Vc_M1 of the first transistor M1 with a higher voltage according to the first terminal voltage of the first transistor M1 (i.e., the first input voltage Vcn) through the BOOST boost circuit, or to generate a control terminal voltage Vc_M2 of the second transistor M2 with a higher voltage according to the first terminal voltage of the second transistor M2 (i.e., the first output voltage Voutp) through the BOOST boost circuit.

[0052] It should be noted that the first transistor M1 and the second transistor M2 are N-type transistors (such as NMOS transistors or N-type IGBT transistors, etc.). N-type transistors have better carrier mobility than P-type transistors. Therefore, the areas of the first transistor M1 and the second transistor M2 in the first switch module 10 can be reduced while ensuring a smaller on-resistance. However, the first transistor M1 and the second transistor M2 use N-type transistors. Although this can solve the technical problem that the circuit area of ​​the P-type transistor is large, it will cause the phenomenon that it is difficult to control the control terminal voltage Vc_M2 (i.e., the gate voltage) of the first transistor M1 and the second transistor M2. The reason is that the N-type transistor is turned on at a high potential, and the control terminal of the second transistor M2 needs to be connected to a control voltage higher than the first output voltage Voutp. However, when the first transistor M1 and the second transistor M2 are turned on, the first terminal of the second transistor M2 outputs the first output voltage Voutp, and the first output voltage Voutp gradually rises to a value close to the first input voltage Vcn. In addition, the gate and source of the second transistor M2 generally cannot withstand high voltage (for example, the voltage difference between the drain and the source is generally 5V to 6V). Therefore, for the control terminal voltage Vc_M2 of the second transistor M2, it is necessary to avoid inputting too high or too low control voltage to cause the second transistor M2 to fail. This also leads to the technical problem that the control terminal voltage Vc_M2 of the second transistor M2 is more difficult to control when the first transistor M1 and the second transistor M2 use N-type transistors.

[0053] In the embodiment of the present application, during the process of the switch control module 20 controlling the first transistor M1 and the second transistor M2, since the control terminal voltage Vc_M1 of the first transistor M1 changes with the first input voltage Vcn, and the control terminal voltage Vc_M2 of the second transistor M2 changes with the first output voltage Voutp, the present application can not only ensure the normal operation of the first transistor M1 and the second transistor M2, but also avoid the phenomenon that the voltage difference between the control terminal and the first terminal of the first transistor M1 and the second transistor M2 is too large and thus causes damage.

[0054] For example, see Figure 2 When the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned on, if the first input voltage Vcn fluctuates, the control terminal voltage Vc_M1 of the first transistor M1 fluctuates with the first input voltage Vcn. Therefore, the voltage difference △V_M1 between the control terminal voltage Vc_M1 of the first transistor M1 and the first input voltage Vcn can be made greater than the threshold voltage of the first transistor M1 and less than the maximum gate-source voltage of the first transistor M1, thereby ensuring that the first transistor M1 is normally turned on and avoiding the phenomenon that the first transistor M1 is damaged due to the excessive voltage difference between the control terminal and the first terminal.

[0055] At the same time, when the first output voltage Voutp rises during the conduction of the first transistor M1 and the second transistor M2, the control terminal voltage Vc_M2 of the second transistor M2 also rises with the first output voltage Voutp, so that the voltage difference △V_M2 between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp can be greater than the threshold voltage of the second transistor M2 and less than the maximum gate-source voltage of the second transistor M2, thereby ensuring that the second transistor M2 is normally turned on and avoiding the phenomenon that the second transistor M2 is damaged due to the excessive voltage difference between the control terminal and the first terminal.

[0056] It can be seen that, since the switch control module 20 of the present application can control the control terminal voltage Vc_M1 of the first transistor M1 to follow the change of the first input voltage Vcn, and the control terminal voltage Vc_M2 of the second transistor M2 to follow the change of the first output voltage Voutp, on the one hand, it can not only ensure that the first transistor M1 and the second transistor M2 are turned on and work normally, but also on the other hand, it can avoid the phenomenon that the voltage difference between the control terminal and the first terminal voltage of the first transistor M1 and the second transistor M2 is too large and damaged. At the same time, since the first transistor M1 and the second transistor M2 are N-type transistors (i.e., N-type transistors), compared with the traditional voltage output circuit 100 using P-type transistors with a relatively large circuit area, the present application can also reduce the area of ​​the first transistor M1 and the second transistor M2 while ensuring a small on-resistance of the transistor, thereby facilitating the reduction of the area of ​​the voltage output circuit 100.

[0057] It should be pointed out that during the conduction process of the first transistor M1 and the second transistor M2, the first terminal voltage of the second transistor M2 (i.e., the first output voltage Voutp) gradually increases. As for the first transistor M1, since the first terminal voltage of the first transistor M1 (i.e., the first input voltage Vcn) is usually stable, when controlling the conduction of the first transistor M1, it is only necessary to input a stable control voltage with a higher voltage to the control terminal of the first transistor M1; when controlling the cutoff of the first transistor M1, it is only necessary to input a stable control voltage with a voltage lower than the first input voltage Vcn to the control terminal of the first transistor M1. Those skilled in the art can use various circuits to control the voltage of the control terminal of the first transistor M1 according to actual needs, such as BOOST boost voltage, BUCK step-down circuit, charge pump, bandgap reference circuit, etc., and this application does not make specific limitations.

[0058] In some embodiments of the present application, when the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned off, the control terminal voltage Vc_M2 of the second transistor M2 is less than the first terminal voltage of the second transistor M2, and the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is less than the maximum gate-source voltage of the second transistor M2.

[0059] For example, see Figure 3 , Figure 3 A schematic diagram of a change of the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp in an embodiment of the present application is shown. Before time t0, the switch control module 20 controls the first transistor M1 and the second transistor M2 to be in the off state, and at this time, the control terminal voltage Vc_M2 of the second transistor M2 is less than the first terminal voltage of the second transistor M2; and after time t0, the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned on, and at this time, the control terminal voltage Vc_M2 of the second transistor M2 follows the first terminal voltage of the second transistor M2 and is greater than the first terminal voltage of the second transistor M2, so that the voltage difference △V_M2 between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is greater than the threshold voltage of the second transistor M2 and less than the maximum gate-source voltage of the second transistor M2.

[0060] It should be noted that, since the first transistor M1 and the second transistor M2 are N-type transistors (i.e., high-potential conduction transistors), and before the switch control module 20 controls the first transistor M1 and the second transistor M2 to turn on, the control terminal voltage Vc_M2 of the second transistor M2 is less than the first terminal voltage of the second transistor M2, then the control terminal voltage Vc_M2 of the second transistor M2 with a lower voltage can ensure that the second transistor M2 is in a cut-off state, thereby ensuring that the voltage output circuit 100 is in a turned-off state and stops outputting the first output voltage Voutp. At the same time, since before the switch control module 20 controls the first transistor M1 and the second transistor M2 to turn on, the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is less than the maximum gate-source voltage of the second transistor M2, it can also avoid the phenomenon that the voltage difference △V_M2 between the control terminal and the first terminal of the second transistor M2 is too large when the voltage output circuit 100 is turned off, causing the second transistor M2 to be damaged.

[0061] It can be understood that in some possible embodiments, when the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned off, the control terminal voltage Vc_M2 of the second transistor M2 may also be greater than the first output voltage Voutp, and it is only necessary to ensure that the voltage difference △V_M2 between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is less than the threshold voltage Vth of the second transistor M2.

[0062] In some embodiments of the present application, see Figure 4 , Figure 4 Another schematic diagram of the voltage output circuit 100 in an embodiment of the present application is shown, wherein the switch control module 20 includes a first current source unit 21, a first impedance unit 22 and a first voltage clamping unit 23; the first current source unit 21 is used to input a first current I1 to a first end of the first impedance unit 22, and the first voltage clamping unit 23 is used to clamp a second end voltage Vdrp of the first impedance unit 22; wherein the first end of the first impedance unit 22 is connected to a control end of the second transistor M2, and the second end voltage Vdrp of the first impedance unit 22 changes with the first output voltage Voutp, so that the control end voltage Vc_M2 of the second transistor M2 changes with the first output voltage Voutp.

[0063] It should be noted that, since the first current source unit 21 inputs the first current I1 to the first end of the first impedance unit 22, and the first voltage clamping unit 23 clamps the second end voltage Vdrp of the first impedance unit 22, it can be known that the control end voltage Vc_M2 of the second transistor M2 satisfies the following formula:

[0064] Vc_M2=I1*R1+Vdrp

[0065] Wherein, I1 is the magnitude of the first current I1 output by the first current source unit 21 , R1 is the impedance of the first impedance unit 22 , and Vdrp is the second terminal voltage of the first impedance unit 22 clamped by the first voltage clamping unit 23 .

[0066] It can be seen that since the term I1*R1 in the above formula remains unchanged, and the second terminal voltage Vdrp of the first impedance unit 22 changes with the first output voltage Voutp, the control terminal voltage Vc_M2 of the second transistor M2 can be made to change with the first output voltage Voutp, and by changing the first current I1 and the impedance of the first impedance unit 22, it can be ensured that the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is greater than the threshold voltage of the second transistor M2 and less than the maximum gate-source voltage of the second transistor M2.

[0067] In some embodiments of the present application, see Figure 5 , Figure 5 Another schematic diagram of the voltage output circuit 100 in an embodiment of the present application is shown, wherein the switch control module 20 also includes a second impedance unit 24; the first current source unit 21 is also used to input the second current I2 to the first end of the second impedance unit 24, the second end of the second impedance unit 24 is used to access the first input voltage Vcn, and the first end of the second impedance unit 24 is connected to the control end of the first transistor M1.

[0068] It should be noted that, since the first current source unit 21 inputs the second current I2 to the first end of the second impedance unit 24, and the second end of the second impedance unit 24 is connected to the first input voltage Vcn, it can be known that the control terminal voltage Vc_M1 of the first transistor M1 satisfies the following formula:

[0069] Vc_M1=I2*R2+Vcn;

[0070] Wherein, R2 is the impedance of the second impedance unit 24 .

[0071] It can be seen from the above formula that since the first end of the first transistor M1 is connected to the first input voltage Vcn, by changing the second current I2 and the impedance of the second impedance unit 24, the voltage difference between the control terminal voltage Vc_M1 of the first transistor M1 and the first input voltage Vcn can be made greater than the threshold voltage of the first transistor M1 and less than the maximum gate-source voltage of the first transistor M1, thereby ensuring that the first transistor M1 is turned on and avoiding the phenomenon that the first transistor M1 is damaged due to excessive difference in source and gate voltage.

[0072] As an exemplary embodiment of the first voltage clamping unit 23, see Figure 6 , Figure 6 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the first voltage clamping unit 23 includes a fifth transistor M5 and a sixth transistor M6; the second end of the fifth transistor M5 is connected to the first preset voltage Vbat, the first end of the fifth transistor M5 is connected to the second end of the sixth transistor M6, and the first end of the sixth transistor M6 is connected to the ground end; wherein the control end of the fifth transistor M5 is connected to the first end of the second transistor M2, the control end of the sixth transistor M6 is used to access the first control signal EN, and the second end of the first impedance unit 22 is connected to the first node m1 between the fifth transistor M5 and the sixth transistor M6.

[0073] It should be noted that the first preset voltage Vbat may be a highest cell voltage greater than the first input voltage Vcn. When the first control signal EN controls the sixth transistor M6 to be turned on, since the control terminal of the fifth transistor M5 is connected to the first output voltage Voutp, after the fifth transistor M5 is turned on, the voltage drop generated by the voltage of the first node m1 (i.e., the second terminal of the fifth transistor M5) relative to the control terminal voltage of the fifth transistor M5 is fixed to the threshold voltage of the fifth transistor M5. Therefore, the second terminal voltage Vdrp of the first impedance unit 22 satisfies the following formula:

[0074] Vdrp=Voutp-Vth_M5

[0075] Wherein, Vth_M5 is the threshold voltage of the fifth transistor M5.

[0076] Therefore, the control terminal voltage Vc_M2 of the second transistor M2 satisfies the following formula:

[0077] Vc_M2=I1*R1+Voutp-Vth_M5

[0078] It can be seen that since the items I1*R1 and Vth_M5 in the above formula are fixed values, the control terminal voltage Vc_M2 of the second transistor M2 can follow the change of the first output voltage Voutp, and by changing the size of the first current I1, the impedance of the first impedance unit 22 and / or the threshold voltage size of the fifth transistor M5, it can be ensured that the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is greater than the threshold voltage of the second transistor M2 and less than the maximum gate-source voltage of the second transistor M2.

[0079] At the same time, when the first current source unit 21 stops outputting the first current I1 and the sixth transistor M6 is in the cut-off state, the voltage of the first node m1 is substantially equal to the control terminal voltage Vc_M2 of the second transistor M2 and satisfies the following formula:

[0080] Voutp-Vc_M2 <Vth_M5

[0081] It can be seen from the above formula that when the switch control module 20 controls the first transistor M1 and the second transistor M2 to be turned off, the control terminal voltage Vc_M2 of the second transistor M2 also changes with the first terminal voltage of the second transistor M2 (i.e., the first output voltage Voutp), and the control terminal voltage Vc_M2 of the second transistor M2 is less than the first terminal voltage of the second transistor M2 (i.e., the first output voltage Voutp), and the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp is also less than its threshold voltage, so that the voltage difference between the control terminal voltage Vc_M2 of the second transistor M2 and the first output voltage Voutp can be made smaller than the maximum gate-source voltage of the second transistor M2, and finally avoids the phenomenon that the voltage difference △V_M2 between the control terminal and the first terminal of the second transistor M2 is too large when the voltage output circuit 100 is turned off, resulting in damage to the second transistor M2.

[0082] It should be noted that the above embodiment uses the fifth transistor M5 and the sixth transistor M6 as NMOS transistors as examples to illustrate how to clamp the second terminal voltage Vdrp of the first impedance unit 22. In some possible embodiments, a PMOS transistor may also be used to clamp the second terminal voltage Vdrp of the first impedance unit 22.

[0083] In some embodiments of the present application, see Figure 7 , Figure 7 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the first voltage clamping unit 23 includes a seventh transistor M7 and an eighth transistor M8; the second end of the seventh transistor M7 is connected to the first end of the sixth transistor M6, and the first end of the seventh transistor M7 is connected to the ground end; the second end of the eighth transistor M8 is connected to the first end of the sixth transistor M6, and the first end of the eighth transistor M8 is connected to the ground end; wherein the control end of the seventh transistor M7 is connected to the first bias voltage BN, and the control end of the eighth transistor M8 is connected to the second control signal ENN, and the levels of the first control signal EN and the second control signal ENN are opposite.

[0084] It should be noted that when the first control signal EN controls the sixth transistor M6 to be turned on, the second control signal ENN controls the eighth transistor M8 to be turned off, and the first bias voltage BN controls the seventh transistor M7 to bias the current flowing through it, thereby ensuring that the fifth transistor M5 is turned on and operates normally; and when the first control signal EN controls the sixth transistor M6 to be turned off, the second control signal ENN controls the eighth transistor M8 to be turned on, and the first bias voltage BN controls the seventh transistor M7 to be turned off, so that when the voltage output circuit 100 is turned off, the eighth transistor M8 can be used to ensure that the first end of the sixth transistor M6 is grounded, thereby avoiding the phenomenon of node voltage floating between the sixth transistor M6 and the seventh transistor M7.

[0085] It can be understood that in some possible embodiments, the first bias voltage BN can also be directly used to control the control terminal of the sixth transistor M6, so as to ensure that the fifth transistor M5 is normally turned on and works.

[0086] It should be pointed out that Figure 7 The circuit diagram of the first current source unit 21, the first impedance unit 22, and the second impedance unit 24 is also shown. Figure 7 The first current source unit 21 adopts PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6 and a current source IS1, the first impedance unit 22 adopts a first resistor R1, and the second impedance unit 24 adopts a second resistor R2. The diagram should not be understood as limiting the first current source unit 21, the first impedance unit 22, and the second impedance unit 24 in the claims of the present application. Those skilled in the art can set the corresponding circuits of the first current source unit 21, the first impedance unit 22, and the second impedance unit 24 according to actual needs. For example, for the first current source unit 21, a current mirror composed of NMOS tubes can also be used to replace the PMOS tubes MP1, MP3 and MP5 that are current mirrors of each other or the PMOS tubes MP2, MP4 and MP6 that are current mirrors of each other. For another example, the first impedance unit 22 and the second impedance unit 24 can adopt multiple resistors connected in series and / or in parallel.

[0087] In some embodiments of the present application, see Figure 8 , Figure 8 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the voltage output circuit 100 further includes a second switch module 30, the second switch module 30 includes a third transistor M3 and a fourth transistor M4, the second end of the third transistor M3 and the second end of the fourth transistor M4 are connected to each other, the first end of the third transistor M3 is used to access the second input voltage Vcn-1, and the second end of the fourth transistor M4 is used to output the second output voltage Voutn; the switch control module 20 is further used to feedback control the control terminal voltage of the third transistor M3 according to the second input voltage Vcn-1, and feedback control the control terminal voltage Vc_M4 of the fourth transistor M4 according to the second output voltage Voutn, so as to control the third transistor M3 and the fourth transistor M4 to be turned on or off; wherein the third transistor M3 and the fourth transistor M4 are N-type transistors, and in the process of the switch control module 20 controlling the third transistor M3 and the fourth transistor M4, the control terminal voltage Vc_M3 of the third transistor M3 changes with the second input voltage Vcn-1, and the control terminal voltage Vc_M4 of the fourth transistor M4 changes with the second output voltage Voutn.

[0088] It should be noted that the first input voltage Vcn may refer to the voltage of a certain battery cell, and the second input voltage Vcn-1 may refer to the voltage of another battery cell. Therefore, by controlling the first transistor M1 and the second transistor M2 through the switch control module 20, a differential voltage output between the two batteries can be achieved, so that the analog-to-digital converter 300 can convert the differential voltage between the two batteries and realize the voltage measurement between the two batteries.

[0089] Similarly, since during the process of the switch control module 20 controlling the third transistor M3 and the fourth transistor M4, the control terminal voltage Vc_M3 of the third transistor M3 changes following the second input voltage Vcn-1, and the control terminal voltage Vc_M4 of the fourth transistor M4 changes following the second output voltage Voutn, the present application can not only ensure the normal operation of the third transistor M3 and the fourth transistor M4, but also avoid the phenomenon that the voltage difference between the control terminal and the first terminal of the third transistor M3 and the fourth transistor M4 is too large and thus causes damage.

[0090] For example, when the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to be turned on, if the second input voltage Vcn-1 fluctuates, the control terminal voltage Vc_M3 of the third transistor M3 fluctuates along with the second input voltage Vcn-1, so that the voltage difference △V_M3 between the control terminal voltage Vc_M3 of the third transistor M3 and the second input voltage Vcn-1 can be made greater than the threshold voltage of the third transistor M3 and less than the maximum gate-source voltage of the third transistor M3, so as to ensure that the third transistor M3 is normally turned on and avoid the phenomenon that the third transistor M31 is damaged due to the excessive voltage difference between the control terminal and the first terminal.

[0091] Also, see Figure 8 , when the second output voltage Voutn rises during the conduction of the third transistor M3 and the fourth transistor M4, the control terminal voltage Vc_M4 of the fourth transistor M4 also rises with the second output voltage Voutn, so that the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn can be greater than the threshold voltage of the fourth transistor M4 and less than the maximum gate-source voltage of the fourth transistor M4, so as to ensure that the fourth transistor M4 is normally turned on and avoid the phenomenon that the fourth transistor M4 is damaged due to the excessive voltage difference between the control terminal and the first terminal. At the same time, since the third transistor M3 and the fourth transistor M4 are N-type transistors, compared with the traditional voltage output circuit 100 using a P-type transistor voltage output circuit, the present application can also reduce the area of ​​the third transistor M3 and the fourth transistor M4 while ensuring a smaller on-resistance of the transistor, thereby facilitating a reduction in the area of ​​the voltage output circuit 100.

[0092] In some embodiments of the present application, when the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to be turned off, the control terminal voltage Vc_M4 of the fourth transistor M4 is less than the first terminal voltage of the second quad transistor, and the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn is less than the maximum gate-source voltage of the second transistor M2.

[0093] For example, see Fig. 9 , Fig. 9 A schematic diagram showing a change of the control terminal voltage Vc_M4 and the second output voltage Voutn of the fourth transistor M4 in the embodiment of the present application is shown. Before time t1, the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to be in the cut-off state. At this time, the control terminal voltage Vc_M4 of the fourth transistor M4 is less than the first terminal voltage of the fourth transistor M4 (i.e., the second output voltage Voutn); and after time t1, the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to be turned on. At this time, the control terminal voltage of the second and fourth transistors follows the first terminal voltage of the fourth transistor M4 (i.e., the second output voltage Voutn) and is greater than the first terminal voltage of the fourth transistor M4, so that the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn is greater than the threshold voltage of the fourth transistor M4 and less than the maximum gate-source voltage of the fourth transistor M4, and finally ensures the normal operation of the fourth transistor M4.

[0094] It should be noted that, since the third transistor M3 and the fourth transistor M4 are N-type transistors (i.e., high-potential conduction transistors), and before the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to turn on, the control terminal voltage Vc_M4 of the fourth transistor M4 is less than the first terminal voltage of the fourth transistor M4, then the control terminal voltage Vc_M4 of the fourth transistor M4 with a lower voltage can ensure that the fourth transistor M4 is in a cut-off state, thereby ensuring that the voltage output circuit 100 is in a turned-off state and stops outputting the second output voltage Voutn. At the same time, since before the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to turn on, the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn is less than the maximum gate-source voltage of the fourth transistor M4, it can avoid the phenomenon that the voltage difference between the control terminal and the second terminal of the fourth transistor M4 is too large when the voltage output circuit 100 is turned off, causing the fourth transistor M4 to be damaged.

[0095] In some embodiments of the present application, see Fig.10 , Fig.10Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the switch control module 20 includes a second current source unit 25, a third impedance unit 26 and a second voltage clamping unit 27; the second current source unit 25 is used to input a third current I3 to a first end of the third impedance unit 26, and the second voltage clamping unit 27 is used to clamp a second end voltage of the third impedance unit 26; wherein the first end of the third impedance unit 26 is connected to the control end of the fourth transistor M4, and the second end voltage of the third impedance unit 26 changes with the second output voltage Voutn, so that the control end voltage Vc M4 of the fourth transistor M4 changes with the second output voltage Voutn.

[0096] It should be noted that, since the second current source unit 25 inputs the third current I3 to the first end of the third impedance unit 26, the second voltage clamping unit 27 clamps the second end voltage of the third impedance unit 26, it can be known that the control end voltage Vc_M4 of the fourth transistor M4 satisfies the following formula:

[0097] Vc_M4=I3*R3+Vdrn

[0098] Wherein, R3 is the impedance of the third impedance unit 26, and Vdrn is the second terminal voltage Vdrn of the third impedance unit 26 clamped by the second voltage clamping unit 27;

[0099] It can be seen that since the I3*R3 term in the above formula remains unchanged, and the second-end voltage Vdrn of the third impedance unit 26 changes with the second output voltage Voutn, the control-end voltage Vc_M4 of the fourth transistor M4 connected to the first end of the third impedance unit 26 can change with the second output voltage Voutn, and by changing the third current I3 and the impedance of the third impedance unit 26, it can be ensured that the voltage difference between the control-end voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn is greater than the threshold voltage of the fourth transistor M4 and less than the maximum gate-source voltage of the fourth transistor M4.

[0100] In some embodiments of the present application, see Fig.10 , wherein the switch control module 20 also includes a fourth impedance unit 28; the second current source unit 25 is also used to input a fourth current I4 to the first end of the fourth impedance unit 28, the second end of the fourth impedance unit 28 is used to access the second input voltage Vcn-1, and the first end of the fourth impedance unit 28 is connected to the control end of the third transistor M3.

[0101] It should be noted that, since the second current source unit 25 inputs the fourth current I4 to the first end of the fourth impedance unit 28, and the second end of the third impedance unit 26 is connected to the second input voltage Vcn-1, it can be known that the control terminal voltage Vc_M3 of the third transistor M3 satisfies the following formula:

[0102] Vc_M3=I4*R4+Vcn-1;

[0103] Wherein, R4 is the impedance of the fourth impedance unit 28 .

[0104] It can be seen from the above formula that since the first end of the third transistor M3 is connected to the second input voltage Vcn-1, by changing the fourth current I4 and the impedance of the fourth impedance unit 28, the voltage difference between the control terminal voltage Vc_M3 of the third transistor M3 and the first input voltage Vcn can be made greater than the threshold voltage of the third transistor M3 and less than the maximum gate-source voltage of the third transistor M3, thereby ensuring that the third transistor M3 is turned on and avoiding the phenomenon that the third transistor M3 is damaged due to excessive difference in source and gate voltage.

[0105] In some embodiments of the present application, see Fig.11 , Fig.11 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the second voltage clamping unit 27 includes a ninth transistor M9 and a tenth transistor M10; the second end of the ninth transistor M9 is connected to the first preset voltage Vbat, the first end of the ninth transistor M9 is connected to the second end of the tenth transistor M10, and the first end of the tenth transistor M10 is connected to the ground end; wherein the control end of the ninth transistor M9 is connected to the first end of the fourth transistor M4, the control end of the tenth transistor M10 is used to access the first control signal EN, and the second end of the third impedance unit 26 is connected to the second node m2 between the ninth transistor M9 and the tenth transistor M10.

[0106] It should be noted that when the first control signal EN controls the tenth transistor M10 to be turned on, since the control terminal of the ninth transistor M9 is connected to the second output voltage Voutn, after the ninth transistor M9 is turned on, the voltage drop generated by the voltage of the second node m2 (i.e., the second terminal of the ninth transistor M9) relative to the control terminal voltage of the ninth transistor M9 is the threshold voltage of the ninth transistor M9, and therefore the second terminal voltage of the second impedance unit 24 satisfies the following formula:

[0107] Vdrn=Voutn-Vth_M9

[0108] Wherein, Vth_M9 is the threshold voltage of the fifth transistor M5.

[0109] Therefore, the control terminal voltage Vc_M4 of the fourth transistor M4 satisfies the following formula:

[0110] Vc_M4=I3*R3+Voutn-Vth_M9

[0111] It can be seen that since the items I3*R3 and Vth_M9 in the above formula are fixed values, the control terminal voltage Vc_M4 of the fourth transistor M4 can follow the change of the second output voltage Voutn, and by changing the size of the third current I3, the impedance of the third impedance unit 26 and / or the threshold voltage Vth_M9 of the ninth transistor M9, it can be ensured that the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn is greater than the threshold voltage of the fourth transistor M4 and less than the maximum gate-source voltage of the fourth transistor M4.

[0112] At the same time, when the second current source unit 25 stops outputting the third current I3 and the sixth transistor M+ is in the cut-off state, the voltage of the second node m2 is substantially equal to the control terminal voltage Vc_M4 of the fourth transistor M4 and satisfies the following formula:

[0113] Voutn-Vc_M4 <Vth_M9

[0114] It can be seen from the above formula that when the switch control module 20 controls the third transistor M3 and the fourth transistor M4 to be turned off, the control terminal voltage Vc_M4 of the fourth transistor M2 is less than the first terminal voltage of the fourth transistor M4 (i.e., the second output voltage Voutn), and the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the first output voltage Voutn is also its threshold voltage, so the voltage difference between the control terminal voltage Vc_M4 of the fourth transistor M4 and the second output voltage Voutn can be made smaller than the maximum gate-source voltage of the fourth transistor M4, and finally avoids the phenomenon that the voltage difference △V_M4 between the control terminal and the first terminal of the fourth transistor M4 is too large when the voltage output circuit 100 is turned off, thereby causing the fourth transistor M4 to be damaged.

[0115] In some embodiments of the present application, see Fig.12 , Fig.12 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein the second voltage clamping unit 27 includes an eleventh transistor M11 and a twelfth transistor M12; the second end of the eleventh transistor M11 is connected to the first end of the tenth transistor M10, and the first end of the eleventh transistor M11 is connected to the ground end; the second end of the twelfth transistor M12 is connected to the first end of the tenth transistor M10, and the first end of the twelfth transistor M12 is connected to the ground end; wherein the control end of the eleventh transistor M11 is connected to the first bias voltage BN, and the control end of the twelfth transistor M12 is connected to the second control signal ENN, and the levels of the first control signal EN and the second control signal ENN are opposite.

[0116] It should be noted that when the first control signal EN controls the tenth transistor M10 to be turned on, the second control signal ENN controls the twelfth transistor M12 to be turned off, and the first bias voltage BN controls the eleventh transistor M11 to bias the current flowing through it, thereby ensuring that the ninth transistor M9 is turned on and operates normally; and when the first control signal EN controls the tenth transistor M10 to be turned off, the second control signal ENN controls the twelfth transistor M12 to be turned on, and the first bias voltage BN controls the eleventh transistor M11 to be turned off, so that when the voltage output circuit 100 is turned off, the twelfth transistor M12 can be used to ensure that the first end of the tenth transistor M10 is grounded, thereby avoiding the phenomenon of node voltage floating between the tenth transistor M10 and the eleventh transistor M11.

[0117] It can be understood that in some possible embodiments, the first bias voltage BN can also be directly used to control the control terminal of the tenth transistor M10, so as to ensure that the ninth transistor M9 is turned on and operates normally.

[0118] It is worth noting that the above contents about the voltage output circuit 100 are intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can make equivalent modified designs or further designs under the guidance of the present application. For example, the first impedance unit 22 and the second impedance unit 24 can be replaced by multiple resistors connected in series and / or in parallel. Fig.12 The third resistor R3 and the fourth resistor R4 in the embodiment can be replaced by a current mirror composed of NMOS tubes. Fig.12 The PMOS tubes MP7, MP9 and MP11 are current mirrors to each other or the PMOS tubes MP8, MP10 and MP12 are current mirrors to each other; for another example, refer to Fig.13 , Fig.13 Another schematic diagram of the voltage output circuit 100 in the embodiment of the present application is shown, wherein voltage zener diodes D1, D2, D3, D4, D5, D6, D7, D8 and current limiting resistors R5, R6, R7, R8, R9 can also be set to achieve protection and current limiting of key electronic components; for another example, in the figure of the present application, the first preset voltage Vbat can be the highest battery cell voltage, and the voltage Vcp used by the first current source unit 21 and the second current source unit 25 can be the highest battery cell voltage generated by a BOOST boost circuit or a charge pump, but in fact it is not limited to this, for example, the first preset voltage Vbat and the voltage Vcp can both be the highest battery cell voltage, or a voltage signal generated by the highest battery cell voltage through a BOOST boost circuit or a charge pump.

[0119] In order to better implement the voltage output circuit 100 in the embodiment of the present application, based on the voltage output circuit 100, the present application also provides a battery management system, the battery management system includes a plurality of battery cells 200 connected in series, the voltage output circuit 100 as described in any of the above embodiments, and an analog-to-digital converter 300, wherein the voltage output circuit 100 is used to control the battery voltage output of at least one battery cell 200; the analog-to-digital converter 300, the analog-to-digital converter 300 is used to perform analog-to-digital conversion on the output voltage provided by the voltage output circuit 100 to achieve measurement of the battery voltage.

[0120] As an example, see Fig.14 , Fig.14 A schematic diagram of a battery management system in an embodiment of the present application is shown, wherein a group of switches S1 and switches S2 are respectively set at both ends of each battery cell 200, each switch S1 can control the voltage input of the corresponding battery to the first end of the first transistor M1 of the first switch module 10, and each switch S2 can control the voltage input of the battery to the first end of the third transistor M3 of the second switch module 30. Finally, under the control of the voltage control module, the analog-to-digital converter 300 can measure the voltage of any battery cell 200, thereby identifying and managing the voltage of each battery cell 200.

[0121] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A voltage output circuit, characterized in that: include: A first switch module, the first switch module comprises a first transistor and a second transistor, the second end of the first transistor and the second end of the second transistor are connected to each other, the first end of the first transistor is used to access a first input voltage, and the second end of the second transistor is used to output a first output voltage; a switch control module, the switch control module being used to control the control terminal voltage of the first transistor according to the first input voltage feedback, and to control the control terminal voltage of the second transistor according to the first output voltage feedback, so as to control the first transistor and the second transistor to be turned on or off; Among them, the first transistor and the second transistor are N-type transistors. When the switch control module controls the first transistor and the second transistor, the control terminal voltage of the first transistor changes with the first input voltage, and the control terminal voltage of the second transistor changes with the first output voltage.

2. The voltage output circuit according to claim 1, characterized in that: The switch control module includes a first current source unit, a first impedance unit and a first voltage clamp unit; The first current source unit is used to input a first current to a first end of the first impedance unit, and the first voltage clamping unit is used to clamp a voltage at a second end of the first impedance unit; The first end of the first impedance unit is connected to the control end of the second transistor, and the voltage of the second end of the first impedance unit changes with the first output voltage, so that the voltage of the control end of the second transistor changes with the first output voltage.

3. The voltage output circuit according to claim 2, characterized in that: The first voltage clamping unit includes a fifth transistor and a sixth transistor; The second end of the fifth transistor is connected to the first preset voltage, the first end of the fifth transistor is connected to the second end of the sixth transistor, and the first end of the sixth transistor is connected to the ground end; The control end of the fifth transistor is connected to the first end of the second transistor, the control end of the sixth transistor is used to access a first control signal, and the second end of the first impedance unit is connected to a first node between the fifth transistor and the sixth transistor.

4. The voltage output circuit according to claim 3, characterized in that: The first voltage clamping unit includes a seventh transistor and an eighth transistor; The second end of the seventh transistor is connected to the first end of the sixth transistor, and the first end of the seventh transistor is connected to the ground end; The second end of the eighth transistor is connected to the first end of the sixth transistor, and the first end of the eighth transistor is connected to the ground end; The control terminal of the seventh transistor is connected to a first bias voltage, the control terminal of the eighth transistor is connected to a second control signal, and the first control signal and the second control signal have opposite levels.

5. The voltage output circuit according to claim 2, characterized in that: The switch control module further includes a second impedance unit; The first current source unit is further used to input a second current to a first end of the second impedance unit, a second end of the second impedance unit is used to access the first input voltage, and a first end of the second impedance unit is connected to a control end of the first transistor.

6. The voltage output circuit according to claim 1, wherein: The voltage output circuit further includes a second switch module, the second switch module includes a third transistor and a fourth transistor, the second end of the third transistor is connected to the second end of the fourth transistor, the first end of the third transistor is used to access the second input voltage, and the second end of the fourth transistor is used to output the second output voltage; The switch control module is further used to control the control terminal voltage of the third transistor according to the second input voltage feedback, and to control the control terminal voltage of the fourth transistor according to the second output voltage feedback, so as to control the third transistor and the fourth transistor to be turned on or off; Among them, the third transistor and the fourth transistor are N-type transistors. In the process of the switch control module controlling the third transistor and the fourth transistor, the control terminal voltage of the third transistor follows the change of the second input voltage, and the control terminal voltage of the fourth transistor follows the change of the second output voltage.

7. The voltage output circuit according to claim 6, characterized in that: The switch control module includes a second current source unit, a third impedance unit and a second voltage clamping unit; The second current source unit is used to input a third current to the first end of the third impedance unit, and the second voltage clamping unit is used to clamp the voltage at the second end of the third impedance unit; The first end of the third impedance unit is connected to the control end of the fourth transistor, and the voltage of the second end of the third impedance unit changes with the second output voltage, so that the voltage of the control end of the fourth transistor changes with the second output voltage.

8. The voltage output circuit according to claim 7, characterized in that: The second voltage clamping unit includes a ninth transistor and a tenth transistor; The second end of the ninth transistor is connected to the first preset voltage, the first end of the ninth transistor is connected to the second end of the tenth transistor, and the first end of the tenth transistor is connected to the ground end; The control end of the ninth transistor is connected to the first end of the fourth transistor, the control end of the tenth transistor is used to access the first control signal, and the second end of the third impedance unit is connected to the second node between the ninth transistor and the tenth transistor.

9. The voltage output circuit according to claim 8, characterized in that: The second voltage clamping unit further includes an eleventh transistor and a twelfth transistor; The second end of the eleventh transistor is connected to the first end of the tenth transistor, and the first end of the eleventh transistor is connected to the ground end; The second end of the twelfth transistor is connected to the first end of the tenth transistor, and the first end of the twelfth transistor is connected to the ground end; The control terminal of the eleventh transistor is connected to a first bias voltage, the control terminal of the twelfth transistor is connected to a second control signal, and the first control signal and the second control signal have opposite levels.

10. The voltage output circuit according to claim 7, characterized in that: The switch control module further includes a fourth impedance unit; The second current source unit is further used to input a fourth current to a first end of the fourth impedance unit, a second end of the fourth impedance unit is used to access the second input voltage, and a first end of the fourth impedance unit is connected to a control end of the third transistor.

11. A battery management system, characterized in that: include: Multiple battery cells connected in series; The voltage output circuit according to any one of claims 1 to 10, wherein the voltage output circuit is used to control the battery voltage output of at least one battery cell; An analog-to-digital converter is used to perform analog-to-digital conversion on the output voltage provided by the voltage output circuit.

Images