Circuit board structure with embedded fine circuit and manufacturing method thereof

Abstract

The invention provides a circuit board structure with an embedded thin circuit and a manufacturing method thereof, the circuit board structure comprises at least one circuit layer, a padlock structure, at least one insulating layer and a dielectric layer, the insulating layer and the dielectric layer are laminated along the thickness direction, the circuit layer comprises the thin circuit, a part of the circuit layer is embedded in the insulating layer, and the padlock structure is embedded in the dielectric layer. The other part of the circuit layer is embedded in the dielectric layer, and one side, deviating from the dielectric layer, of the circuit layer is exposed from the surface, deviating from the dielectric layer, of the insulating layer; the padlock structure is embedded in the dielectric layer and is connected with the thin circuit. A part of the thin circuit is embedded in the insulating layer, a part of the thin circuit is embedded in the dielectric layer, and the buckling and locking structure is embedded in the dielectric layer to connect the thin circuit, so that the adhesion capability of the thin circuit can be greatly enhanced.

Description

Technical Field

[0001] The present application relates to the field of circuit boards, and in particular to a circuit board structure with embedded fine circuits and a manufacturing method thereof. Background Art

[0002] In order to meet the requirements of high-density integration, the width of lines on circuit boards is getting smaller and smaller, but the adhesion of thin lines is poor, and there is a risk of line floating. Summary of the invention

[0003] In order to solve the above deficiencies of the prior art, the present application provides a method for manufacturing a circuit board structure with embedded fine circuits.

[0004] In addition, it is necessary to provide a circuit board structure with embedded thin circuits.

[0005] The present application provides a circuit board structure with embedded fine circuits, the circuit board structure comprising at least one circuit layer, a locking structure, and at least one insulating layer and a dielectric layer stacked along the thickness direction, the circuit layer comprising fine circuits, part of the circuit layer being embedded in the insulating layer, and another part of the circuit layer being embedded in the dielectric layer, and a side of the circuit layer facing away from the dielectric layer being exposed from a surface of the insulating layer facing away from the dielectric layer; the locking structure being embedded in the dielectric layer and connecting the fine circuits.

[0006] In some embodiments, a width of one end of the thin line facing the dielectric layer is not less than a width of one end of the thin line facing the insulating layer.

[0007] In some embodiments, the width of one end of the locking structure connected to the thin line is greater than the width of the thin line.

[0008] In some embodiments, the circuit board structure includes two circuit layers, two snap-lock structures and two insulating layers, the two insulating layers are respectively arranged on opposite sides of the dielectric layer, the two snap-lock structures are arranged facing each other and correspondingly, and the two circuit layers are arranged correspondingly.

[0009] In some embodiments, each of the circuit layers further includes a pad, a conductive body is disposed in the dielectric layer, and the conductive body electrically connects two opposite pads.

[0010] In some embodiments, a surface of the circuit layer facing away from the dielectric layer is flush with a surface of the insulating layer facing away from the dielectric layer.

[0011] The present application also provides a method for manufacturing a circuit board structure with embedded thin circuits, comprising the following steps:

[0012] Providing an insulating carrier, and stacking an insulating layer on one side of the insulating carrier along the thickness direction;

[0013] A plurality of openings are formed through the insulating layer;

[0014] Electroplating to form a circuit layer in the opening, wherein the circuit layer includes fine circuits;

[0015] A locking structure is formed on a side of the insulating layer away from the insulating carrier, wherein the locking structure is connected to the thin circuit;

[0016] Removing part of the insulating layer along the thickness direction so that a gap is formed between the locking structure and the insulating layer to obtain a circuit substrate;

[0017] A dielectric layer is pressed on one side of the circuit substrate, the dielectric layer fills the gap and adheres to the insulating layer, and the locking structure and part of the circuit layer are embedded in the dielectric layer;

[0018] The insulating carrier is removed to obtain a circuit board structure with embedded fine circuits.

[0019] In some embodiments, the step of “pressing a dielectric layer on one side of the circuit substrate” includes:

[0020] A circuit substrate, a dielectric layer and another circuit substrate are stacked and pressed together. During stacking, the two thin circuits are facing each other and arranged correspondingly. After pressing together, an insulating layer is respectively bonded to opposite sides of the dielectric layer.

[0021] In some embodiments, a conductive body is provided in the dielectric layer, and the circuit layer further includes a pad spaced apart from the fine circuit;

[0022] The step of “stacking and laminating one circuit substrate, one dielectric layer and another circuit substrate” includes:

[0023] During stacking, the two ends of the conductive body are respectively arranged corresponding to one of the pads; after pressing, the conductive body is electrically connected to the two pads.

[0024] In some embodiments, the step of “opening a plurality of openings through the insulating layer” includes:

[0025] The insulating layer is exposed and developed to form a plurality of the openings, wherein the width of the openings on a side away from the insulating carrier is not less than the width of the openings on a side facing the insulating carrier.

[0026] Compared with the prior art, the circuit board structure with embedded fine circuits provided in the present application can greatly enhance the adhesion ability of the fine circuits by embedding part of the fine circuits in the insulating layer and part of the fine circuits in the dielectric layer, and embedding a locking structure in the dielectric layer to connect the fine circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic cross-sectional view of an insulating carrier provided in accordance with an embodiment of the present application.

[0028] Figure 2 for Figure 1 The schematic cross-sectional view of the insulating carrier after the insulating layer is provided is shown.

[0029] Figure 3 For Figure 2 The schematic cross-sectional view of the insulating layer after the opening is provided is shown.

[0030] Figure 4 For Figure 3 The schematic cross-sectional view of the opening after copper plating to form a circuit layer is shown.

[0031] Figure 5 For Figure 4 The schematic cross-sectional view shows that the circuit layer is away from the surface of the insulating carrier to form a locking structure.

[0032] Figure 6 To remove the portion from the side away from the insulating carrier Figure 5 A schematic cross-sectional view of the circuit substrate obtained after removing the insulating layer is shown.

[0033] Figure 7 For the general Figure 6 The circuit substrate, a dielectric layer and another Figure 6 The cross-sectional view of the circuit substrate after stacking is shown.

[0034] Figure 8 For the general Figure 7 The schematic cross-sectional view of a circuit board structure is shown in which a circuit substrate, a dielectric layer, and the insulating carrier are removed after the circuit substrate is pressed together.

[0035] Main component symbols

[0036] Circuit board structure 100

[0037] Insulation carrier board 10

[0038] Insulation layer 11

[0039] Opening 112

[0040] Circuit layer 20

[0041] Copper layer 201

[0042] Thin Line 22

[0043] Pad 24

[0044] Lock structure 30

[0045] Gap R

[0046] Circuit board 1

[0047] Dielectric layer 4

[0048] Conductor 42

[0049] Thickness direction A

[0050] Width W1, W2

[0051] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0053] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. When an element is considered to be "set on" another element, it may be directly set on the other element or there may be a central element at the same time.

[0054] See also Figures 1 to 8 The present application provides a method for manufacturing a circuit board structure 100 having an embedded thin circuit, comprising the following steps:

[0055] Step S1, see Figure 1 , an insulating carrier board 10 is provided.

[0056] The insulating carrier 10 only serves as a temporary load-bearing member and may be made of glass or ceramic.

[0057] In some embodiments, the insulating carrier 10 may be a peelable insulating carrier to facilitate subsequent removal.

[0058] Step S2, see Figure 2 An insulating layer 11 is disposed on one side of the insulating carrier 10 .

[0059] Specifically, the insulating substrate 10 has a thickness direction A, and a photosensitive resin may be printed on one side of the insulating substrate 10 along the thickness direction A to form the insulating layer 11 , that is, the insulating layer 11 may be patterned by exposure and development.

[0060] In other embodiments, a photoresist layer may be attached to one side of the insulating carrier 10 instead of the insulating layer 11 .

[0061] Step S3, see Figure 3 A plurality of openings 112 are formed through the insulating layer 11 , and the width of the openings 112 facing away from the insulating carrier 10 is not less than the width of the openings 112 facing the insulating carrier 10 .

[0062] Specifically, exposure and development processing can be performed on a predetermined area of ​​the insulating layer 11 according to a predetermined size to form a plurality of openings 112 of a specific size, and the openings 112 penetrate the insulating layer 11 along the thickness direction A. The openings 112 formed by exposure and development have a uniform width in the thickness direction A.

[0063] Step S4, see Figure 4 , copper is plated in the opening 112 to form a circuit layer 20 , and the circuit layer 20 includes thin circuits 22 and pads 24 that are spaced apart.

[0064] Specifically, the circuit layer 20 is formed in the opening 112 by using chemical plating or electroplating. A copper layer 201 is also formed on the surface of the insulating layer 11 which is away from the insulating carrier 10 .

[0065] In the conventional technology, the fine circuit formed by electroplating after laser drilling of blind holes is usually wide at the top and narrow at the bottom, that is, the width of the end used for connection is smaller, which will lead to reduced adhesion when the width of the fine circuit itself is very small. In the present application, the fine circuit 22 is formed by copper plating in the opening 112 formed by exposure and development, and the width of the end of the fine circuit 22 away from the insulating carrier 10 is not less than the width of the end of the fine circuit 22 facing the insulating carrier 10, which can effectively improve the adhesion of the fine circuit 22. In this embodiment, the width W1 of the fine circuit 22 formed in the opening 112 in the thickness direction A is uniform.

[0066] Step S5, see Figure 5 , corresponding to the thin circuit 22 , a locking structure 30 is formed on the surface of the insulating layer 11 away from the insulating carrier 10 .

[0067] The snap-lock structure 30 may be one or more. When there is one snap-lock structure 30, a single snap-lock structure 30 may simultaneously connect to a plurality of thin circuits 22; when there are multiple snap-lock structures 30, each snap-lock structure 30 is correspondingly connected to one thin circuit 22. The width W2 of one end of the snap-lock structure 30 connected to the thin circuit 22 is greater than the width W1 of the thin circuit 22. The snap-lock structure 30 may be, but is not limited to, a rectangular, triangular, or other special-shaped shapes.

[0068] Specifically, a photosensitive dry film may be attached to the surface of the copper layer 201, and the locking structure 30 may be formed through steps such as exposure, development, and electroplating, and then the copper layer 201 may be removed through film stripping and rapid etching.

[0069] Step S6, see Figure 6 , a portion of the insulating layer 11 is removed along the thickness direction A, so that a gap R is formed between the insulating layer 11 and the locking structure 30 , thereby obtaining a circuit substrate 1 .

[0070] Specifically, a plasma etching process may be used to remove a portion of the insulating layer 11 on the side of the insulating layer 11 away from the insulating substrate 10 . The surface of the circuit layer 20 away from the insulating substrate 10 protrudes from the surface of the insulating layer 11 away from the insulating substrate 10 .

[0071] Step S7, see Figure 7 and Figure 8 , a circuit substrate 1, a dielectric layer 4 and another circuit substrate 1 are stacked and pressed together, and the insulating carrier 10 is removed to obtain a circuit board structure 100 with embedded fine circuits. When stacking, the locking structures 30 of the two circuit substrates 1 are facing the dielectric layer 4 and are arranged correspondingly; after pressing together, the dielectric layer 4 fills the gap R and adheres the two insulating layers 11, so that the locking structures 30 and part of the circuit layer 20 are embedded in the dielectric layer 4.

[0072] The dielectric layer 4 is also provided with a conductive body 42 therethrough. When stacked, the conductive body 42 is arranged corresponding to the pad 24 . After pressing, the conductive body 42 electrically connects the two pads 24 .

[0073] In some embodiments, the dielectric layer 4 may be a prepreg (PP) or other dielectric material layer, and the conductive body 42 may be a copper paste.

[0074] See also Figure 8An embodiment of the present application further provides a circuit board structure 100 with embedded fine circuits, the circuit board structure 100 includes at least one circuit layer 20, a locking structure 30, and an insulating layer 11 and a dielectric layer 4 stacked along a thickness direction A, the circuit layer 20 is partially embedded in the insulating layer 11, and the other part is embedded in the dielectric layer 4, the locking structure 30 is embedded in the dielectric layer 4 and connected to the circuit layer 20.

[0075] Wherein, the circuit layer 20 includes a thin circuit 22, and the snap-lock structure 30 is connected to the side of the thin circuit 22 away from the insulating layer 11. The surface of the circuit layer 20 away from the dielectric layer 4 is roughly flush with the surface of the insulating layer 11 away from the dielectric layer 4, and the width of the end of the thin circuit 22 facing the dielectric layer 4 is not less than the width of the end of the thin circuit 22 away from the dielectric layer 4. Preferably, the width W1 of the thin circuit 22 along the thickness direction A is consistent. The width W2 of the end of the snap-lock structure 30 connected to the thin circuit 22 is greater than the width W1 of the thin circuit 22, and the snap-lock structure 30 can be, but is not limited to, a rectangular, triangular or other special-shaped shapes.

[0076] In some embodiments, the snap-locking structure 30 may be one or more. When the snap-locking structure 30 is one, the single snap-locking structure 30 may simultaneously connect to a plurality of the thin circuits 22; when the snap-locking structure 30 is more than one, each snap-locking structure 30 is connected to a corresponding thin circuit 22.

[0077] In one embodiment, the circuit board structure 100 includes two circuit layers 20, two corresponding locking structures 30 and two insulating layers 11, the two insulating layers 11 are respectively arranged on opposite sides of the dielectric layer 4, the two circuit layers 20 are arranged facing each other and correspondingly, and the two locking structures 30 are arranged facing each other and correspondingly.

[0078] The circuit layer 20 further includes pads 24 spaced apart from the thin circuits 22 , and a conductive body 42 is provided through the dielectric layer 4 , and the conductive body 42 electrically connects two opposite pads 24 .

[0079] In the circuit board structure 100 of the present application, part of the circuit layer 20 is embedded in the insulating layer 11, and another part of the circuit layer 20 is embedded in the dielectric layer 4. The widths of the two ends of the thin circuit 22 are consistent, and the locking structure 30 is set to be embedded in the dielectric layer 4, which can greatly enhance the bonding force between the thin circuit 22 and the dielectric layer 4.

[0080] The above description is only an optimized specific implementation of the present application, but it cannot be limited to this implementation in the actual application process. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should all fall within the protection scope of the present application.

Claims

1. A circuit board structure with embedded thin circuits, characterized in that: The circuit board structure includes at least one circuit layer, a locking structure, and at least one insulating layer and a dielectric layer stacked along the thickness direction. The circuit layer includes fine circuits, part of the circuit layer is embedded in the insulating layer, and another part of the circuit layer is embedded in the dielectric layer. The side of the circuit layer facing away from the dielectric layer is exposed from the surface of the insulating layer facing away from the dielectric layer; the locking structure is embedded in the dielectric layer and connects the fine circuits.

2. The circuit board structure according to claim 1, characterized in that: The width of one end of the thin line facing the dielectric layer is not less than the width of one end of the thin line facing the insulating layer.

3. The circuit board structure according to claim 2, characterized in that: The width of one end of the locking structure connected to the thin line is greater than the width of the thin line.

4. The circuit board structure according to claim 1, characterized in that: The circuit board structure includes two circuit layers, two locking structures and two insulating layers. The two insulating layers are respectively arranged on opposite sides of the dielectric layer, the two locking structures are arranged facing each other and correspondingly, and the two circuit layers are arranged correspondingly.

5. The circuit board structure according to claim 4, characterized in that: Each of the circuit layers further comprises a pad, a conductive body is arranged in the dielectric layer, and the conductive body electrically connects two opposite pads.

6. The circuit board structure according to claim 1, characterized in that: A surface of the circuit layer facing away from the dielectric layer is flush with a surface of the insulating layer facing away from the dielectric layer.

7. A method for manufacturing a circuit board structure with embedded thin circuits, characterized in that: Includes steps: Providing an insulating carrier, and stacking an insulating layer on one side of the insulating carrier along the thickness direction; A plurality of openings are formed through the insulating layer; Electroplating to form a circuit layer in the opening, wherein the circuit layer includes fine circuits; A locking structure is formed on a side of the insulating layer away from the insulating carrier, wherein the locking structure is connected to the thin circuit; Removing part of the insulating layer along the thickness direction so that a gap is formed between the locking structure and the insulating layer to obtain a circuit substrate; A dielectric layer is pressed on one side of the circuit substrate, the dielectric layer fills the gap and adheres to the insulating layer, and the locking structure and part of the circuit layer are embedded in the dielectric layer; The insulating carrier is removed to obtain the circuit board structure with embedded fine circuits.

8. The manufacturing method according to claim 7, characterized in that: The step of "pressing a dielectric layer on one side of the circuit substrate" includes: A circuit substrate, a dielectric layer and another circuit substrate are stacked and pressed together, wherein, during stacking, the two thin circuits are facing each other and arranged correspondingly; after pressing together, an insulating layer is respectively bonded to opposite sides of the dielectric layer.

9. The manufacturing method according to claim 8, characterized in that: A conductive body is provided in the dielectric layer, and the circuit layer further comprises a pad spaced apart from the thin circuit; The step of "stacking and laminating one circuit substrate, one dielectric layer and another circuit substrate" includes: During stacking, the two ends of the conductive body are respectively arranged corresponding to one of the pads; after pressing, the conductive body connects the two pads.

10. The manufacturing method according to claim 7, characterized in that: The step of "opening a plurality of openings through the insulating layer" includes: The insulating layer is exposed and developed to form a plurality of the openings, wherein the width of the openings on a side away from the insulating carrier is not less than the width of the openings on a side facing the insulating carrier.

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