Ferroelectric memory and manufacturing method thereof
By forming sacrificial layers and back-etching technology in ferroelectric memory manufacturing, the high cost and leakage of traditional processes are solved, and performance improvement and integration improvement are achieved.
Patent Information
- Application Number
- CN202411441021.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-10
AI Technical Summary
Traditional ferroelectric memory manufacturing process is costly and difficult to achieve high integration, and leakage problems between adjacent memory cells are prone to affect performance.
By forming a sacrificial layer covering at least the memory hole and removing the storage structure using a back etching process, the manufacturing process is simplified, the use of the photocoat is avoided, the cost is reduced, and sufficient separation and isolation of the memory cells are achieved.
The performance improvement of ferroelectric memory is achieved, manufacturing costs are reduced, manufacturing processes are simplified, leakage problems between adjacent memory cells are avoided, and integration is improved.
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Figure CN119300357A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a ferroelectric memory and a manufacturing method thereof. Background Art
[0002] Ferroelectric RAM (FeRAM) is a device that integrates memory cells in the back-end of line (BEOL), which is a structure in which the memory cell is inserted between two adjacent metal layers. The memory cell is generally composed of an upper and lower electrode layer and a ferroelectric memory layer in the middle. The storage performance of the ferroelectric memory is proportional to the effective area of the ferroelectric memory layer and the electrode layer in the memory cell. The material of the ferroelectric memory layer in the memory cell of the traditional ferroelectric memory is usually phase change material or ferroelectric material, and the traditional memory cell is a three-dimensional structure.
[0003] In the manufacturing process of the traditional ferroelectric memory, after depositing the lower electrode layer, storage layer, upper electrode layer and contact structure in the capacitor hole in the dielectric layer, it is necessary to form a mask layer above the dielectric layer and pattern the mask layer to remove the lower electrode layer, storage layer and upper electrode layer covering the top surface of the dielectric layer to separate adjacent memory cells. However, the above-mentioned steps of separating adjacent memory cells are not only costly, but also prone to leakage problems between adjacent memory cells due to incomplete separation, which is not conducive to the improvement and enhancement of the performance of the ferroelectric memory. In addition, the above-mentioned process of separating adjacent memory cells requires a large spacing between adjacent memory cells so that there are sufficient lithography windows, which is not conducive to further improvement of the integration of the ferroelectric memory.
[0004] Therefore, how to simplify the manufacturing process of ferroelectric memory, reduce the manufacturing cost of ferroelectric memory, improve the integration of ferroelectric memory, and improve the performance of ferroelectric memory is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The ferroelectric memory and the manufacturing method thereof provided by the present invention are used to simplify the manufacturing process of the ferroelectric memory, reduce the manufacturing cost of the ferroelectric memory, and at the same time improve the integration of the ferroelectric memory and improve the performance of the ferroelectric memory.
[0006] According to some embodiments, the present invention provides a method for manufacturing a ferroelectric memory, comprising the following steps:
[0007] forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly;
[0008] forming a sacrificial layer at least covering the storage structure in the storage hole;
[0009] Etching back to remove the storage structure on the top surface of the first dielectric layer, and remove the sacrificial layer;
[0010] forming a second dielectric layer covering the substrate;
[0011] A first lead-out structure is formed which penetrates the second dielectric layer and is electrically connected to the storage structure.
[0012] In some embodiments, the specific steps of forming the substrate include:
[0013] forming a first dielectric layer;
[0014] Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction;
[0015] forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer;
[0016] forming a storage layer covering the lower electrode layer;
[0017] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.
[0018] In some embodiments, the specific step of forming a sacrificial layer covering at least the storage structure in the storage hole comprises:
[0019] An insulating material is deposited on the substrate to form the sacrificial layer that continuously covers the upper electrode layer in the storage hole and the upper electrode layer on the top surface of the first dielectric layer.
[0020] In some embodiments, the specific step of etching back to remove the storage structure on the top surface of the first dielectric layer includes:
[0021] The storage structure is etched back to completely remove the storage structure on the top surface of the first dielectric layer and to remove a portion of the storage structure in the storage hole, wherein the top surface of the remaining storage structure in the storage hole is lower than the top surface of the first dielectric layer.
[0022] In some embodiments, the specific steps of forming the second dielectric layer covering the substrate include:
[0023] A second dielectric layer is formed to fill the storage hole and cover the top surface of the first dielectric layer.
[0024] In some embodiments, the specific steps of forming a first lead-out structure that penetrates the second dielectric layer and is electrically connected to the storage structure include:
[0025] forming a first lead-out hole penetrating through the second dielectric layer along the first direction and exposing the upper electrode layer at the bottom of the storage hole, and the remaining second dielectric layer is distributed at least around the periphery of the first lead-out hole;
[0026] A conductive material is filled into the first lead-out hole to form the first lead-out structure electrically connected to the upper electrode layer.
[0027] In some embodiments, the specific steps of forming the substrate include:
[0028] forming a first dielectric layer;
[0029] Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction;
[0030] forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer;
[0031] Etching back part of the lower electrode layer to completely remove the lower electrode layer on the top surface of the first dielectric layer and part of the lower electrode layer in the storage hole, wherein the top surface of the remaining lower electrode layer in the storage hole is lower than the top surface of the first dielectric layer;
[0032] forming a storage layer that continuously covers the top surface of the first dielectric layer, the inner wall of the storage hole, and the surface of the lower electrode layer;
[0033] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.
[0034] In some embodiments, the specific steps of etching back part of the lower electrode layer include:
[0035] A portion of the lower electrode layer in the storage hole is etched by multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer.
[0036] In some embodiments, before forming the second dielectric layer covering the substrate, the following steps are also included:
[0037] A conductive filling layer is formed to fill the storage hole and cover the upper electrode layer.
[0038] In some embodiments, the specific steps of forming a first lead-out structure that penetrates the second dielectric layer and is electrically connected to the storage structure include:
[0039] forming a first lead-out hole penetrating through the second dielectric layer along the first direction and exposing the conductive filling layer;
[0040] Filling the first lead-out hole with a conductive material to form the first lead-out structure electrically connected to the conductive filling layer.
[0041] According to some other embodiments, the present invention further provides a ferroelectric memory, comprising:
[0042] A substrate, the substrate comprising a first dielectric layer and a storage hole penetrating the first dielectric layer along a first direction, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the first dielectric layer;
[0043] A storage structure, covering the inner wall of the storage hole, wherein the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer;
[0044] A second dielectric layer covering the substrate;
[0045] The first lead-out structure penetrates the second dielectric layer along the first direction and is electrically connected to the storage structure.
[0046] In some embodiments, the storage structure includes a lower electrode layer, a storage layer covering a surface of the lower electrode layer, and an upper electrode layer covering a surface of the storage layer;
[0047] The first lead-out structure is electrically connected to the upper electrode layer.
[0048] In some embodiments, the second dielectric layer covers the top surface of the first dielectric layer and fills the storage hole, the first lead-out structure extends into the storage hole and is electrically connected to the upper electrode layer at the bottom of the storage hole, and the second dielectric layer in the storage hole is distributed around the periphery of the first lead-out structure.
[0049] In some embodiments, the top surface of the lower electrode layer is lower than the top surface of the first dielectric layer, and the storage layer continuously covers the sidewall of the storage hole and the surface of the lower electrode layer away from the sidewall of the storage hole;
[0050] The ferroelectric memory further includes a conductive filling layer that fills the storage hole and covers the upper electrode layer. The first lead-out structure is located above the conductive filling layer and is electrically connected to the conductive filling layer.
[0051] The ferroelectric memory and its manufacturing method provided by the present invention, by forming a sacrificial layer that at least covers the storage structure in the storage hole, and removing the storage structure on the top surface of the first dielectric layer through a back etching process, can not only fully separate the adjacent storage structures to achieve the improvement of the electrical performance of the ferroelectric memory, but also save the manufacturing cost of the ferroelectric memory and simplify the manufacturing process of the ferroelectric memory without using a mask. At the same time, the present invention can fully isolate the lower electrode layer and the upper electrode layer in the storage structure through the subsequently deposited storage layer by back etching the deposited lower electrode layer before depositing the storage layer in the storage structure, thereby avoiding the leakage problem between the lower electrode layer and the upper electrode layer. In addition, the present invention etches part of the lower electrode layer in the storage hole through multiple lateral etching processes, reduces the inclination angle of the top surface of the lower electrode layer, can reduce the tip discharge effect of the lower electrode layer, and further improve the performance of the ferroelectric memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 is a flow chart of a method for manufacturing a ferroelectric memory in a specific embodiment of the present invention;
[0053] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;
[0054] Figure 3 is a structural schematic diagram after a storage structure is formed in a storage hole in a specific embodiment of the present invention;
[0055] Figure 4 is a schematic diagram of a structure after a sacrificial layer is formed in a specific embodiment of the present invention;
[0056] Figure 5 is a schematic diagram of a structure after the storage structure is etched back in a specific implementation manner of the present invention;
[0057] Figure 6 is a schematic diagram of a structure after forming a second dielectric layer in a specific embodiment of the present invention;
[0058] Figure 7 is a schematic diagram of a structure after a mask layer is formed in a specific embodiment of the present invention;
[0059] Figure 8 is a structural schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention;
[0060] Fig. 9 is another structural schematic diagram after a lower electrode layer is formed in a storage hole in a specific embodiment of the present invention;
[0061] Fig.10is another structural schematic diagram after the lower electrode layer is etched back in a specific embodiment of the present invention;
[0062] Fig.11 is another structural schematic diagram after a storage structure is formed in a storage hole in a specific embodiment of the present invention;
[0063] Fig.12 is another structural schematic diagram after the storage structure is etched back in a specific embodiment of the present invention;
[0064] Fig.13 is another structural schematic diagram after a conductive filling layer is formed in a specific embodiment of the present invention;
[0065] Fig.14 It is another structural schematic diagram after the first lead-out structure is formed in a specific implementation manner of the present invention. DETAILED DESCRIPTION
[0066] The specific implementation manner of the ferroelectric memory and the manufacturing method thereof provided by the present invention is described in detail below with reference to the accompanying drawings.
[0067] This specific embodiment provides a method for manufacturing a ferroelectric memory. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a ferroelectric memory in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the ferroelectric memory comprises the following steps:
[0068] Step S11, forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly;
[0069] Step S12, forming a sacrificial layer covering at least the storage structure in the storage hole;
[0070] Step S13, etching back to remove the storage structure on the top surface of the first dielectric layer, and remove the sacrificial layer;
[0071] Step S14, forming a second dielectric layer covering the substrate;
[0072] Step S15, forming a first lead-out structure penetrating the second dielectric layer and electrically connected to the storage structure.
[0073] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention, Figure 3 FIG. 1 is a schematic diagram of a structure after a storage structure is formed in a storage hole in a specific embodiment of the present invention. Figure 2 and Figure 3 As shown, the specific steps of forming the substrate include:
[0074] forming a first dielectric layer 21;
[0075] Etching the first dielectric layer 21 to form the storage hole 22 penetrating the first dielectric layer 21 along the first direction D1;
[0076] forming a lower electrode layer 31 covering the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21;
[0077] forming a storage layer 32 covering the lower electrode layer 31;
[0078] An upper electrode layer 33 is formed to cover the storage layer 32 . The lower electrode layer 31 , the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.
[0079] For example, the substrate includes a substrate, an isolation layer 20 located above the substrate, and the first dielectric layer 21 covering the isolation layer 20. The substrate includes an active region, and the active region includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction D2. In one example, the isolation layer 20 has a first contact structure 23 electrically connected to the drain region and penetrating the isolation layer 20 along the first direction D1, and a second contact structure 24 electrically connected to the source region and penetrating the isolation layer 20 along the first direction D1. In another example, the substrate also includes a gate electrode located above the substrate and corresponding to the channel region, the isolation layer 20 covers the gate electrode, and the isolation layer 20 has a first contact structure 23 electrically connected to the drain region and penetrating the isolation layer 20 along the first direction D1, and a second contact structure 24 electrically connected to the gate electrode and penetrating the isolation layer 20 along the first direction D1.
[0080] The substrate further includes a third dielectric layer 25 located between the first dielectric layer 21 and the isolation layer 20. The materials of the first dielectric layer 21 and the isolation layer 20 may both be oxide materials, such as silicon dioxide; and the material of the third dielectric layer 25 may be nitride materials, such as silicon nitride. The first dielectric layer 21 is etched to form the storage hole 22 that penetrates the first dielectric layer 21 and the third dielectric layer 25 along the first direction D1 and exposes the first contact structure 23. In an example, the substrate includes at least a plurality of active regions arranged at intervals along the second direction D2 and the first contact structure 23 and the second contact structure 24 located above each active region. By etching the first dielectric layer 21, a plurality of storage holes 22 that are arranged at intervals along the second direction D2 and correspond to the plurality of first contact structures 23 are formed. A conductive material such as TiN is deposited on the substrate to form the lower electrode layer 31 that continuously covers the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21. A ferroelectric material is deposited on the substrate to form the storage layer 32 covering the lower electrode layer 31. Next, a conductive material such as TiN is deposited on the substrate to form the upper electrode layer 33 covering the storage layer 32, so that the lower electrode layer 31, the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.
[0081] Figure 4 2 is a schematic diagram of a structure after forming a sacrificial layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the sacrificial layer 40 of the storage structure at least covering the storage hole 22 include:
[0082] An insulating material is deposited on the substrate to form the sacrificial layer 40 that continuously covers the upper electrode layer 33 in the storage hole 22 and the upper electrode layer 33 on the top surface of the first dielectric layer 21 .
[0083] For example, a BARC (Bottom Anti-Reflective Coating) material is deposited on the substrate to form the sacrificial layer 40 that continuously covers the upper electrode layer 33 in the storage hole 22 and the upper electrode layer 33 on the top surface of the first dielectric layer 21. The use of the BARC material to form the sacrificial layer 40 can not only prevent the sacrificial layer 40 from chemically reacting with the upper electrode layer 33, but also facilitate the subsequent removal of the remaining sacrificial layer 40.
[0084] Figure 5 is a schematic diagram of a structure after the storage structure is etched back in a specific embodiment of the present invention. Figure 5As shown, the specific steps of etching back to remove the storage structure on the top surface of the first dielectric layer 21 include:
[0085] The storage structure is etched back to completely remove the storage structure on the top surface of the first dielectric layer 21 and to remove part of the storage structure in the storage hole 22 , and the top surface of the remaining storage structure in the storage hole 22 is lower than the top surface of the first dielectric layer 21 .
[0086] Specifically, the storage structure on the top surface of the first dielectric layer 21 is completely removed by an etch-back process, and part of the storage structure in the storage hole 22 is removed, so as to ensure that the connection between the storage structures in the adjacent storage holes 22 along the second direction D2 is completely cut off, which not only avoids the leakage problem between the adjacent storage structures, but also simplifies the manufacturing process of the ferroelectric memory and reduces the manufacturing cost of the ferroelectric memory. The top surface of the remaining storage structure in the storage hole 22 described in this specific embodiment is lower than the top surface of the first dielectric layer 21, which means that at least part of the top surface of the remaining storage structure in the storage hole 22 is lower than the top surface of the first dielectric layer 21. After the storage structure is etched back, the remaining sacrificial layer 40 can also be removed by a wet cleaning process.
[0087] Figure 6 is a schematic diagram of a structure after forming the second dielectric layer in a specific embodiment of the present invention. Figure 6 As shown, the specific steps of forming the second dielectric layer 60 covering the substrate include:
[0088] A second dielectric layer 60 is formed to fill the storage hole 22 and cover the top surface of the first dielectric layer 21 .
[0089] Figure 7 is a schematic diagram of a structure after a mask layer is formed in a specific embodiment of the present invention, Figure 8 is a schematic diagram of a structure after forming the first lead-out structure in a specific embodiment of the present invention. Figure 7 and Figure 8 As shown, the specific steps of forming the first lead-out structure 80 that penetrates the second dielectric layer 60 and is electrically connected to the storage structure include:
[0090] A first lead-out hole is formed along the first direction D1, penetrating the second dielectric layer 60 and exposing the upper electrode layer 33 at the bottom of the storage hole 22, and the remaining second dielectric layer 60 is at least distributed around the periphery of the first lead-out hole;
[0091] A conductive material is filled into the first lead-out hole to form the first lead-out structure 80 electrically connected to the upper electrode layer 33 .
[0092] For example, an insulating material such as silicon dioxide is deposited on the substrate to form the second dielectric layer 60 that fills the storage hole 22 and covers the top surface of the storage structure and the first dielectric layer 21. Afterwards, the second dielectric layer 60 can be planarized by chemical mechanical polishing or other methods. During the planarization process, the thickness of the remaining second dielectric layer 60 after polishing can be controlled by controlling the polishing time to fully protect the storage structure. Next, a mask layer 70 is formed on the second dielectric layer 60, and a patterned photoresist layer 71 is formed on the mask layer 70, wherein the photoresist layer 71 has a first etching window 72 and a second etching window 73 that expose the mask layer 70. The mask layer 70 and the second dielectric layer 60 are etched downward along the first etching window 72, and the mask layer 70, the second dielectric layer 60, the first dielectric layer 21 and the third dielectric layer 25 are etched downward along the second etching window 73 to form the first lead-out hole exposing the upper electrode layer 33 at the bottom of the storage hole 22 and the second lead-out hole exposing the second contact structure 24. At the same time, a conductive material such as metal tungsten is filled into the first lead-out hole and the second lead-out hole to form the first lead-out structure 80 electrically connected to the upper electrode layer 33 and the second lead-out structure 81 electrically connected to the second contact structure 24. After the first lead-out hole is formed by the etching process, the remaining second dielectric layer 60 is at least distributed around the periphery of the first lead-out hole, thereby avoiding the problem of short circuit between the upper electrode layer 33 and the lower electrode layer 31 when depositing the conductive material such as metal tungsten, and helping to further reduce the distance between the adjacent storage structures, thereby further increasing the number of the storage structures in the ferroelectric memory and achieving further improvement of the integration of the ferroelectric memory.
[0093] Fig. 9 is another structural schematic diagram after a lower electrode layer is formed in a storage hole in a specific embodiment of the present invention, Fig.10 is another structural schematic diagram after the lower electrode layer is etched back in a specific embodiment of the present invention, Fig.11 FIG. 1 is another schematic diagram of a structure after a storage structure is formed in a storage hole in a specific embodiment of the present invention. Fig. 9 , Fig.10 and Fig.11 As shown, the specific steps of forming the substrate include:
[0094] forming a first dielectric layer 21;
[0095] Etching the first dielectric layer 21 to form the storage hole 22 penetrating the first dielectric layer 21 along the first direction D1;
[0096] forming a lower electrode layer 31 covering the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21;
[0097] Etch back part of the lower electrode layer 31, completely remove the lower electrode layer 31 on the top surface of the first dielectric layer 21 and part of the lower electrode layer 31 in the storage hole 22, and the top surface of the remaining lower electrode layer 31 in the storage hole 22 is lower than the top surface of the first dielectric layer 21;
[0098] forming a storage layer 32 that continuously covers the top surface of the first dielectric layer 21, the inner wall of the storage hole 22, and the surface of the lower electrode layer 31;
[0099] An upper electrode layer 33 is formed to cover the storage layer 32 . The lower electrode layer 31 , the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.
[0100] Specifically, by etching back the lower electrode layer 31 after depositing the lower electrode layer 31 and before depositing the storage layer 32, not only can the connection between the lower electrode layers 31 in adjacent storage structures be fully cut off, but the lower electrode layer 31 and the upper electrode layer 33 in the same storage structure can also be isolated through the subsequently deposited storage layer 32, thereby fully avoiding the leakage problem between the lower electrode layer 31 and the upper electrode layer 33 in the same storage structure.
[0101] In some other embodiments, the specific steps of etching back part of the lower electrode layer 31 include:
[0102] The portion of the lower electrode layer 31 in the storage hole 22 is etched through multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer 31 .
[0103] Specifically, by etching the portion of the lower electrode layer 31 in the storage hole 22 through multiple lateral etching processes, the inclination angle of the top surface of the lower electrode layer 31 is reduced, which can reduce the tip discharge effect of the lower electrode layer 31, thereby further improving the performance of the ferroelectric memory. The multiple times mentioned in this specific embodiment refers to more than twice.
[0104] Fig.122 is another structural schematic diagram after the storage structure is etched back in a specific embodiment of the present invention. In one example, after the storage structure is formed, a BARC (Bottom Anti-Reflective Coating) material is deposited on the substrate to form a sacrificial layer 40 that continuously covers the upper electrode layer 33 in the storage hole 22 and the upper electrode layer 33 on the top surface of the first dielectric layer 21. Then, the upper electrode layer 33 and the storage layer 32 on the top surface of the first dielectric layer 21 are etched back to remove, and the sacrificial layer 40 is removed to obtain the following. Fig.12 Through the back etching process, the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21, which not only simplifies the manufacturing process of the ferroelectric memory, but also fully avoids the leakage problem between adjacent storage structures.
[0105] Fig.13 is another structural schematic diagram after forming a conductive filling layer in a specific embodiment of the present invention. Fig.13 As shown, before forming the second dielectric layer 60 covering the substrate, the following steps are also included:
[0106] A conductive filling layer 130 is formed to fill the storage hole 22 and cover the upper electrode layer 33 .
[0107] Fig.14 8 is another structural schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention. In other embodiments, the specific steps of forming the first lead-out structure 80 that penetrates the second dielectric layer 60 and is electrically connected to the storage structure include:
[0108] forming a first lead-out hole penetrating through the second dielectric layer 60 along the first direction D1 and exposing the conductive filling layer 130;
[0109] A conductive material is filled into the first lead-out hole to form the first lead-out structure 80 electrically connected to the conductive filling layer 130 .
[0110] Specifically, since the lower electrode layer 31 and the upper electrode layer 33 in the same storage structure are isolated by the storage layer 32, the formation of the conductive filling layer 130 that fills the storage hole 22 and covers the upper electrode layer 33 will not cause a short circuit between the upper electrode layer 33 and the lower electrode layer 31. By forming the conductive filling layer 130, not only the process window for forming the first lead-out structure 80 can be increased, but also the electrical connection stability between the upper electrode layer 33 and the first lead-out structure 80 can be improved.
[0111] This specific embodiment also provides a ferroelectric memory. The ferroelectric memory provided in this specific embodiment can be used as follows Figure 1-Figure 14 The ferroelectric memory is formed by the manufacturing method shown in FIG. Figure 8 and Fig.14 .like Figure 1-Figure 14 As shown, the ferroelectric memory comprises:
[0112] A substrate, the substrate comprising a first dielectric layer 21 and a storage hole 22 penetrating the first dielectric layer 21 along a first direction D1, the first dielectric layer 21 comprising a top surface and a bottom surface that are relatively distributed, and the first direction D1 intersects the top surface of the first dielectric layer 21 perpendicularly;
[0113] A storage structure, covering the inner wall of the storage hole 22, and the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21;
[0114] A second dielectric layer 60, covering the substrate;
[0115] The first lead-out structure 80 penetrates the second dielectric layer 60 along the first direction D1 and is electrically connected to the storage structure.
[0116] Specifically, by making the top surface of the storage structure lower than or flush with the top surface of the first dielectric layer 21, the adjacent storage structures can be fully isolated, thereby improving the electrical performance of the ferroelectric memory. In this specific embodiment, the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21, which means that at least part of the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21.
[0117] In some embodiments, the storage structure includes a lower electrode layer 31, a storage layer 32 covering a surface of the lower electrode layer 31, and an upper electrode layer 33 covering a surface of the storage layer 32;
[0118] The first lead-out structure 80 is electrically connected to the upper electrode layer 33 .
[0119] In some embodiments, the second dielectric layer 60 covers the top surface of the first dielectric layer 21 and fills the storage hole 22, the first lead structure 80 extends into the storage hole 22 and contacts and electrically connects with the upper electrode layer 33 at the bottom of the storage hole 22, and the second dielectric layer 60 in the storage hole 22 is distributed around the periphery of the first lead structure 80. With the above structure, not only can the lower electrode layer 31 and the upper electrode layer 33 in the storage structure be fully isolated by the second dielectric layer 60, but also the distance between adjacent storage structures can be further reduced, thereby further increasing the number of storage structures in the ferroelectric memory and further improving the integration of the ferroelectric memory.
[0120] In some embodiments, the top surface of the lower electrode layer 31 is lower than the top surface of the first dielectric layer 21, and the storage layer 32 continuously covers the side wall of the storage hole 22 and the surface of the lower electrode layer 31 away from the side wall of the storage hole 22;
[0121] The ferroelectric memory further includes a conductive filling layer 130 that fills the storage hole 22 and covers the upper electrode layer 33, and the first lead-out structure 81 is located above the conductive filling layer 130 and is electrically connected to the conductive filling layer 130. By forming the conductive filling layer 130, not only the process window for forming the first lead-out structure 80 can be increased, but also the electrical connection stability between the upper electrode layer 33 and the first lead-out structure 80 can be improved.
[0122] The ferroelectric memory and its manufacturing method provided in this specific embodiment, by forming a sacrificial layer that at least covers the storage structure in the storage hole, and removing the storage structure on the top surface of the first dielectric layer through a back etching process, can not only fully separate the adjacent storage structures to achieve the improvement of the electrical performance of the ferroelectric memory, but also save the manufacturing cost of the ferroelectric memory and simplify the manufacturing process of the ferroelectric memory without using a mask. At the same time, this specific embodiment, by back etching the deposited lower electrode layer before depositing the storage layer in the storage structure, can fully isolate the lower electrode layer and the upper electrode layer in the storage structure through the subsequently deposited storage layer, thereby avoiding the leakage problem between the lower electrode layer and the upper electrode layer. In addition, this specific embodiment etches part of the lower electrode layer in the storage hole through multiple lateral etching processes, reduces the inclination angle of the top surface of the lower electrode layer, can reduce the tip discharge effect of the lower electrode layer, and further improve the performance of the ferroelectric memory.
[0123] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing a ferroelectric memory, characterized in that: The steps include: forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly; forming a sacrificial layer at least covering the storage structure in the storage hole; Etching back to remove the storage structure on the top surface of the first dielectric layer, and remove the sacrificial layer; forming a second dielectric layer covering the substrate; A first lead-out structure is formed which penetrates the second dielectric layer and is electrically connected to the storage structure.
2. The method for manufacturing a ferroelectric memory according to claim 1, characterized in that: The specific steps of forming the substrate include: forming a first dielectric layer; Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction; forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer; forming a storage layer covering the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.
3. The method for manufacturing a ferroelectric memory according to claim 2, wherein: The specific steps of forming a sacrificial layer at least covering the storage structure in the storage hole include: An insulating material is deposited on the substrate to form the sacrificial layer that continuously covers the upper electrode layer in the storage hole and the upper electrode layer on the top surface of the first dielectric layer.
4. The method for manufacturing a ferroelectric memory according to claim 1, wherein: The specific steps of etching back to remove the storage structure on the top surface of the first dielectric layer include: The storage structure is etched back to completely remove the storage structure on the top surface of the first dielectric layer and to remove a portion of the storage structure in the storage hole, wherein the top surface of the remaining storage structure in the storage hole is lower than the top surface of the first dielectric layer.
5. The method for manufacturing a ferroelectric memory according to claim 2, wherein: The specific steps of forming the second dielectric layer covering the substrate include: A second dielectric layer is formed to fill the storage hole and cover the top surface of the first dielectric layer.
6. The method for manufacturing a ferroelectric memory according to claim 5, characterized in that: The specific steps of forming a first lead-out structure penetrating the second dielectric layer and electrically connected to the storage structure include: forming a first lead-out hole penetrating the second dielectric layer along the first direction and exposing the upper electrode layer at the bottom of the storage hole, and the remaining second dielectric layer is distributed at least around the periphery of the first lead-out hole; A conductive material is filled into the first lead-out hole to form the first lead-out structure electrically connected to the upper electrode layer.
7. The method for manufacturing a ferroelectric memory according to claim 1, characterized in that: The specific steps of forming the substrate include: forming a first dielectric layer; Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction; forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer; Etching back part of the lower electrode layer to completely remove the lower electrode layer on the top surface of the first dielectric layer and part of the lower electrode layer in the storage hole, wherein the top surface of the remaining lower electrode layer in the storage hole is lower than the top surface of the first dielectric layer; forming a storage layer that continuously covers the top surface of the first dielectric layer, the inner wall of the storage hole, and the surface of the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.
8. The method for manufacturing a ferroelectric memory according to claim 7, characterized in that: The specific steps of etching back part of the lower electrode layer include: A portion of the lower electrode layer in the storage hole is etched by multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer.
9. The method for manufacturing a ferroelectric memory according to claim 7, characterized in that: Before forming the second dielectric layer covering the substrate, the method further includes the following steps: A conductive filling layer is formed to fill the storage hole and cover the upper electrode layer.
10. The method for manufacturing a ferroelectric memory according to claim 9, characterized in that: The specific steps of forming a first lead-out structure penetrating the second dielectric layer and electrically connected to the storage structure include: forming a first lead-out hole penetrating the second dielectric layer along the first direction and exposing the conductive filling layer; Filling the first lead-out hole with a conductive material to form the first lead-out structure electrically connected to the conductive filling layer.
11. A ferroelectric memory, characterized in that: include: The substrate comprises a first dielectric layer and a storage hole penetrating the first dielectric layer along a first direction, the first dielectric layer comprises a top surface and a bottom surface that are relatively distributed, and the first direction is parallel to the first dielectric layer. The top surface of the first dielectric layer intersects vertically; A storage structure, covering the inner wall of the storage hole, wherein the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer; A second dielectric layer covering the substrate; The first lead-out structure penetrates the second dielectric layer along the first direction and is electrically connected to the storage structure.
12. The ferroelectric memory according to claim 11, characterized in that: The storage structure includes a lower electrode layer, a storage layer covering a surface of the lower electrode layer, and an upper electrode layer covering a surface of the storage layer; The first lead-out structure is electrically connected to the upper electrode layer.
13. The ferroelectric memory according to claim 12, characterized in that: The second dielectric layer covers the top surface of the first dielectric layer and fills the storage hole, the first lead-out structure extends into the storage hole and is in contact and electrically connected with the upper electrode layer at the bottom of the storage hole, and the second dielectric layer in the storage hole is distributed around the periphery of the first lead-out structure.
14. The ferroelectric memory according to claim 12, wherein: The top surface of the lower electrode layer is lower than the top surface of the first dielectric layer, and the storage layer continuously covers the side wall of the storage hole and the surface of the lower electrode layer away from the side wall of the storage hole; The ferroelectric memory further includes a conductive filling layer that fills the storage hole and covers the upper electrode layer. The first lead-out structure is located above the conductive filling layer and is electrically connected to the conductive filling layer.