Small surface-mounted diode array packaging method and packaging structure thereof

Abstract

The invention discloses a small surface-mounted diode array packaging method and a small surface-mounted diode array packaging structure, and belongs to the technical field of microelectronic device packaging. The packaging structure is packaged by adopting a multi-layer co-fired ceramic base and a metal cover plate or a ceramic cover plate. The electric signal transmission line is arranged in each layer of ceramic, the bonding area is arranged in the same area, the chip area is arranged in the other area, and the bonding area and the chip area are in a step type. And metallization layers are respectively manufactured on the ceramic bottom planes of the bonding area and the chip area. Bottom surface areas of two ends of the ceramic pedestal are external electrode pad layout areas, and a diode array is respectively provided with a positive electrode pad array and a negative electrode pad array which are used for external connection. And the bonding region and the chip region are connected with the corresponding electrode bonding pads on the bottom surface through metal via holes. The problems that an existing surface-mounted multi-array diode discrete device is low in packaging integration level, large in size, low in heat dissipation efficiency, low in product power integration density, large in parasitic impedance and low in reliability are solved. The method is widely applied to the technical field of miniaturized high-reliability packaging of component arrays.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic device packaging, and further relates to the technical field of SMD multi-array discrete device integrated packaging, and specifically, to a small SMD diode array packaging method and a packaging structure thereof. Background Art

[0002] Semiconductor products are gradually developing towards miniaturization and lightness. The integration of discrete devices can optimize the circuit structure, reduce the board area, and increase the power density. The requirements for the integration, miniaturization, airtightness, reliability and other performance of packaged products are becoming increasingly higher.

[0003] Compared with organic plastic packaging, ceramic packaging has higher mechanical strength, lower expansion coefficient, and higher thermal conductivity. These characteristics can meet the needs of high airtightness and high heat dissipation packaging of chips. Ceramic packaging technology can provide higher heat resistance, moisture resistance, corrosion resistance, and electromagnetic interference resistance. It can maintain stable performance in high temperature environment and will not cause performance degradation due to temperature increase.

[0004] Ceramic packaging has the following characteristics: 1. High moisture resistance: It has good waterproof and moisture-proof properties and is suitable for environments with high humidity; 2. High corrosion resistance: It has good corrosion resistance to chemicals such as acids, alkalis, salts and organic solvents; 3. High resistance to electromagnetic interference: It has good electromagnetic shielding ability and can be used at high frequencies without being affected by electromagnetic interference; 4. Excellent electrical properties: Ceramic materials have low resistivity and high insulation performance, which can effectively suppress electromagnetic interference and signal crosstalk; 5. Excellent mechanical properties and stability: Ceramic materials have high hardness and impact resistance, which can effectively protect the chip from external physical impact and damage; 6. Good airtightness: Ceramic packaging is an airtight packaging that can prevent moisture from entering the interior and contaminating the chip; 7. Small thermal expansion coefficient: The thermal expansion coefficient of ceramic materials is small, which is similar to the thermal expansion coefficient of chip materials, which is beneficial to improving the reliability of packaging.

[0005] Due to these remarkable characteristics, ceramic packages are widely used in various electronic fields with high performance requirements, including aerospace, military equipment, medical equipment, high-end communication equipment and functional electronics. For example, electronic equipment working in extreme temperature and radiation environments, communication and navigation systems that require high reliability and long-term stability.

[0006] The packaging structure currently using planar integration technology has low integration, large volume, low heat dissipation efficiency, low product power density, and large parasitic impedance. It cannot meet the requirements of multi-array discrete devices for high integration and miniaturized packaging.

[0007] In view of this, the present invention is proposed. Summary of the invention

[0008] The technical problem to be solved by the present invention is to solve the problems of low integration, large volume, low heat dissipation efficiency, low product power integration density, large parasitic impedance and low reliability of existing surface-mount multi-array diode discrete device packaging.

[0009] To this end, the present invention provides a small-scale surface mount diode array packaging method, including the following method: The packaging structure is packaged in a ceramic shell (a combination of a multi-layer co-fired ceramic base and a metal cover). The ceramic base and the metal cover are precisely calculated and designed to put the entire product in an optimal state.

[0010] In the packaging cavity of the ceramic shell, the electrical signal transmission lines are arranged in each layer of ceramic, the electrical signal transmission lines and the lead bonding area (collectively referred to as the bonding area) on the bottom of the cavity are arranged in the same area, and the chip welding area (referred to as the chip area) is arranged in another area. The bonding area and the chip area are stepped, and the chip area is lower than the bonding area. The bonding area and the chip area are seamlessly isolated by staggered steps, which not only ensures the isolation between the bonding area and the chip area and reduces parasitic effects, but also greatly improves the heat dissipation capacity and integration.

[0011] Metallization layers are made on the ceramic bottom planes of the bonding area and the chip area respectively. The metallization layer in the bonding area is used for electrode wiring and wire bonding of the front electrode of the diode chip, and the metallization layer in the chip area is used for diode chip mounting welding and electrode wiring of the back electrode.

[0012] The bottom surface areas at both ends of the ceramic base are external electrode pad layout areas, where diode arrays are respectively laid out as a positive electrode pad array and a negative electrode pad array for external connection.

[0013] A through hole penetrating the ceramic base body is made below the electrode wiring layer on the front side of the diode chip in the metallization layer of the bonding area, and metal electrode materials are filled in the through hole to connect with the corresponding electrode pad on the bottom of the ceramic base; a through hole penetrating the ceramic base body is made below the electrode wiring layer on the back side of the diode chip in the metallization layer of the chip area, and metal electrode materials are filled in the through hole to connect with the corresponding electrode pad on the bottom of the ceramic base. This realizes internal and external electrical connection, greatly reduces the parasitic impedance and inductive reactance of the product, and at the same time maximizes the heat dissipation efficiency of the product and increases the power density of the product. Improve product reliability.

[0014] The packaging structure of the small-sized SMD diode array packaging method is as follows: Figure 1-4 As shown. Includes: Ceramic base body 1, side cavity 2, sealing ring 3, cover plate 4, cover plate welding ring 5, inner cavity 6, bonding area bottom surface 7, chip area bottom surface 8, bonding area metallization layer 9, chip area metallization layer 10, bonding area electrode through hole 11, chip area electrode through hole 12, back electrode pad 13, chip 14, bonding wire 15.

[0015] The ceramic base body 1 is a multi-layer co-fired ceramic, and the electrode wiring between each ceramic layer is connected through metal vias provided in the corresponding ceramic layer.

[0016] The side cavity 2, inner cavity 6, bonding area bottom surface 7, chip area bottom surface 8, bonding area electrode through hole 11, and chip area electrode through hole 12 are integrated into the ceramic base body 1. The bonding area bottom surface 7 is located in the upper area of ​​the bottom of the inner cavity of the ceramic base, and the chip area bottom surface 8 is located in the lower area of ​​the bottom of the inner cavity of the ceramic base. The bonding area bottom surface 7 is higher than the chip area bottom surface 8.

[0017] The bonding area metallization layer 9 is made on the bonding area bottom surface 7, and the chip area metallization layer 10 is made on the chip area bottom surface 8. The bonding area metallization layer 9 is used for the bonding area, the diode front electrode routing and the connection with the external electrode, and the chip area metallization layer 10 is used for the chip assembly area, the diode back electrode routing and the connection with the external electrode.

[0018] The chip area metallization layer 10 is lower than the bonding area metallization layer 9, and the chip area electrode through hole 12 is shorter than the bonding area electrode through hole 11, which greatly shortens the chip heat dissipation channel, reduces the chip heat dissipation thermal resistance, and facilitates rapid heat dissipation.

[0019] The bonding area electrode through hole 11 is located below the bonding area metallization layer 9, and the chip area electrode through hole 12 is located below the chip area metallization layer 10, penetrating the ceramic base body, and connected to the corresponding back electrode pads 13 after being filled with via metal.

[0020] The chip 14 is welded on the chip area metallization layer 10 , and the chip front electrode is bonded to the bonding area metallization layer 9 via a bonding wire 15 .

[0021] The cover plate 4 is a ceramic cover plate or a metal cover plate, and a cover plate welding ring 5 is made around the cover plate 4 . The shape and size of the cover plate welding ring 5 are consistent with the sealing ring 3 .

[0022] The upper surface of the side cavity 2 is a sealing ring 3, and the cover plate 4 is sealedly connected to the sealing ring 3 by high-temperature welding. Beneficial Effects

[0023] The product of the present invention has the advantages of high packaging integration, small size, high heat dissipation efficiency, high product power integration density, small parasitic impedance, high mechanical strength, stable chemical properties, high insulation, good high-frequency shielding, high reliability, etc.

[0024] The invention can be widely used in the field of miniaturized high-reliability packaging technology for component arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the structure of the ceramic packaging shell of the diode array unit channel.

[0026] Figure 2 This is a schematic diagram of the internal cavity layout structure of the ceramic base package for the three-channel diode array.

[0027] Figure 3 This is a schematic diagram of the pin pad layout structure on the bottom surface of the ceramic base of the three-channel diode array package.

[0028] Figure 4 Schematic diagram of the planar structure of the three-channel diode array package ceramic base chip assembly.

[0029] In the figure: 1 is the ceramic base body, 2 is the side cavity, 3 is the sealing ring, 4 is the cover plate, 5 is the cover plate welding ring, 6 is the inner cavity, 7 is the bottom surface of the bonding area, 8 is the bottom surface of the chip area, 9 is the metallization layer of the bonding area, 10 is the metallization layer of the chip area, 11 is the electrode through hole of the bonding area, 12 is the electrode through hole of the chip area, 13 is the back electrode pad, 14 is the chip, and 15 is the bonding wire.

[0030] A, B, C, D, E, and F are the serial numbers of the metallization layers distributed on the inner surface, and a, b, c, d, e, and f are the serial numbers of the electrode pads on the back side. DETAILED DESCRIPTION

[0031] like Figure 1-4 As shown, taking a three-channel diode array ceramic metal package as an example, the small-sized SMD diode array packaging method and its packaging structure are specifically implemented as follows: Example 1: Packaging structure The base of the package shell is a square ceramic base. The ceramic body material is more than 95% Al2O3 ceramic (aluminum oxide) or AlN ceramic (aluminum nitride). The outer dimensions of the shell are: length 2.0mm±0.12mm, width 2.2mm±0.12mm, height 1.0mm±0.1mm, inner cavity size is length 1.4mm, width 1.2mm, bonding area bottom plane height is 0.4mm±0.06mm, chip area bottom plane height is 0.6mm±0.06mm, and frame width is 0.4mm.

[0032] The package shell cover is a square metal cover with a composition of 4J42. The cover dimensions are: length 1.85mm±0.1mm, width 2.05mm±0.1mm, height 0.2mm±0.05mm, welding ring width 0.45mm, and the welding ring material of the cover is gold-tin alloy.

[0033] The sealing ring material is 4J42 / 4J29.

[0034] The layout of the base area is: bonding area, chip area, external electrode pad area, such as Figure 2 , Figure 3 shown.

[0035] A surface metallization layer is formed in the bonding area, the chip area, and the electrode pad area.

[0036] The bonding area metallization layer 9 is distributed as: D, E, F, and is located in the middle and upper part of the bottom plane of the inner cavity. Preferably, the size of the D, E, and F pads is 0.5 mm×0.3 mm. Figure 2 shown.

[0037] The chip area metallization layer 10 is distributed as: A, B, C, and is located in the middle and lower part of the bottom plane of the inner cavity. Preferably, the size of the A, B, C pads is 0.85mm×0.3mm. Figure 2 shown.

[0038] The electrode pad area metallization layer 13 is located on the back of the ceramic base and is distributed as follows: a, b, c, d, e, f. The pads a, b, c are located below A, B, C in sequence, and the pads d, e, f are located below D, E, F in sequence. Preferably, the pads a, b, c, d, e, f have a size of 0.4 mm × 0.6 mm and a spacing of 0.25 mm. Figure 3 shown.

[0039] The bonding area metallization layer 9 and the chip area metallization layer 10 are both composed of multiple layers of metal materials, the surface layer material is gold, the second layer material is metal nickel, and the third layer material is metal tungsten. The surface layer and the second layer material are plated by electroplating, and the third layer material is first printed on the ceramic with metal tungsten slurry and then solidified. Preferably, the surface gold layer has a thickness of 1.3 to 5.7 um, the second nickel layer has a thickness of 4.0 to 11.3 um, and the third tungsten layer has a thickness of 5 to 30 um.

[0040] The structure of the electrode pad area metallization layer 13 is to first print a metal tungsten layer in an outer set area, and then weld a metal block on the metal tungsten layer.

[0041] The bonding connections are: A is connected to F, B is connected to E, and C is connected to D.

[0042] The internal and external connection relationships are: A is connected to a, B is connected to b, C is connected to c, D is connected to d, E is connected to e, and F is connected to f.

[0043] The shell sealing ring and the cover plate are connected by fusion sealing, such as Figure 1 shown.

[0044] Embodiment 2: Packaging method The following steps are involved: (1) Alumina and an organic binder are mixed and ground into a slurry, and then tape-cast, sliced, and sintered to form alumina green ceramic sheets of a set size; (2) Using laser drilling or mechanical punching to process multiple through holes on the ceramic green sheet according to the setting; (3) Inject metallized tungsten paste into the through hole through a mechanical mask to form a metal via to achieve conductive interconnection in the vertical direction, and then use a screen printer to print the bonding area, chip area, and intermediate layer electrical connection lines on the corresponding ceramic layer; (4) stacking the plurality of raw porcelain sheets processed as above, with the through holes of all the raw porcelain sheets corresponding to each other and compacted, to form a raw porcelain assembly with interconnected layers; (5) Processing the internal cavity on the green-ceramic combination by laser cutting or mechanical punching; (6) using a dicing machine to cut the stacked green-ceramic combination into individual ceramic bodies for high-temperature sintering; (7) Making a metal sealing frame (sealing ring) and an electrode pad electrode sheet according to the set size. The metal sealing frame material is 4J29 Kovar material, and the electrode sheet material is Mo70Cu30 material; (8) Electroplating a nickel layer and a gold layer on the pad metal layer, the bonding area metal layer, the chip area metal layer and the sealing ring of the ceramic base respectively; (9) Alloy solder is used to simultaneously perform airtight welding of the cover plate and the base, and welding of the pad electrode sheet and the pad metal layer.

[0045] Finally, it should be noted that the above embodiments are merely examples for the purpose of clear explanation. The present invention includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods exhaustively. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. All implementation methods that meet the requirements of the present invention belong to the protection scope of the present invention.

Claims

1. A small-scale surface-mount diode array packaging method, characterized in that: The following methods are included: The packaging structure is packaged using a multi-layer co-fired ceramic base and a metal cover or a ceramic cover; In the packaging cavity of the ceramic shell, the electric signal transmission line is arranged in each layer of ceramic, the electric signal transmission line and the lead bonding area (collectively referred to as the bonding area) on the bottom of the cavity are arranged in the same area, and the chip welding area (referred to as the chip area) is arranged in another area. The bonding area and the chip area are stepped, the chip area is lower than the bonding area, and the bonding area and the chip area are seamlessly isolated by staggered steps; Metallization layers are respectively made on the ceramic bottom planes of the bonding area and the chip area, the bonding area metallization layer includes the electrode wiring metallization layer of the front electrode of the diode chip and the lead bonding area metallization layer, and the chip area metallization layer includes the diode chip mounting welding area metallization layer and the back electrode wiring metallization layer; The bottom surface areas at both ends of the ceramic base are external electrode pad layout areas, where a diode array is respectively laid out for a positive electrode pad array and a negative electrode pad array for external connection; A through hole penetrating the ceramic base body is made below the front electrode wiring layer of the diode chip in the metallization layer of the bonding area, and the through hole is filled with metal electrode material to connect with the corresponding electrode pad on the bottom surface of the ceramic base; a through hole penetrating the ceramic base body is made below the back electrode wiring layer of the diode chip in the metallization layer of the chip area, and the through hole is filled with metal electrode material to connect with the corresponding electrode pad on the bottom surface of the ceramic base.

2. A small-scale SMD diode array packaging method as claimed in claim 1, characterized in that: The specific method is as follows: (1) Alumina and an organic binder are mixed and ground into a slurry, and then tape-cast, sliced, and sintered to form alumina green ceramic sheets of a set size; (2) Using laser drilling or mechanical punching to process multiple through holes on the ceramic green sheet according to the setting; (3) Inject metallized tungsten paste into the through hole through a mechanical mask to form a metal via to achieve conductive interconnection in the vertical direction, and then use a screen printer to print the bonding area, chip area, and intermediate layer electrical connection lines on the corresponding ceramic layer; (4) stacking the plurality of raw porcelain sheets processed as above, with the through holes of all the raw porcelain sheets corresponding to each other and compacted, to form a raw porcelain assembly with interconnected layers; (5) Processing the internal cavity on the green-ceramic combination by laser cutting or mechanical punching; (6) using a dicing machine to cut the stacked green-ceramic combination into individual ceramic bodies for high-temperature sintering; (7) Making sealing rings and electrode pads according to set dimensions; (8) Electroplating a nickel layer and a gold layer on the pad metal layer, the bonding area metal layer, the chip area metal layer and the sealing ring of the ceramic base respectively; (9) Using alloy solder to simultaneously perform airtight welding of the cover plate and the base, and welding of the pad electrode sheet and the pad metal layer; The electrode sheet material is Mo70Cu30.

3. The packaging structure of a small-sized SMD diode array packaging method according to claim 1, characterized in that: It comprises a ceramic base body (1), a side cavity (2), a sealing ring (3), a cover plate (4), a cover plate welding ring (5), an inner cavity (6), a bonding area bottom surface (7), a chip area bottom surface (8), a bonding area metallization layer (9), a chip area metallization layer (10), a bonding area electrode through hole (11), a chip area electrode through hole (12), a back electrode pad (13), a chip (14) and a bonding wire (15); The ceramic base body (1) is a multi-layer co-fired ceramic, and the electrode wiring between each ceramic layer is connected through metal vias provided in the corresponding ceramic layer; The side cavity (2), the inner cavity (6), the bonding area bottom surface (7), the chip area bottom surface (8), the bonding area electrode through hole (11), and the chip area electrode through hole (12) are integrally manufactured in the ceramic base body (1); the bonding area bottom surface (7) is located in the upper area of ​​the bottom of the inner cavity of the ceramic base; the chip area bottom surface (8) is located in the lower area of ​​the bottom of the inner cavity of the ceramic base; and the bonding area bottom surface (7) is higher than the chip area bottom surface (8); The bonding area metallization layer (9) is manufactured on the bonding area bottom surface (7), and the chip area metallization layer (10) is manufactured on the chip area bottom surface (8); the bonding area metallization layer (9) is used for the bonding area, the diode front electrode routing and the connection with the external electrode, and the chip area metallization layer (10) is used for the chip assembly area, the diode back electrode routing and the connection with the external electrode; The chip region metallization layer (10) is lower than the bonding region metallization layer (9), and the chip region electrode through hole (12) is shorter than the bonding region electrode through hole (11); The bonding area electrode through hole (11) is located below the bonding area metallization layer (9), and the chip area electrode through hole (12) is located below the chip area metallization layer (10), penetrates the ceramic base body, and is respectively connected to the corresponding back electrode pads (13) after being filled with via metal; The chip (14) is welded on the chip area metallization layer (10), and the chip front electrode is bonded to the bonding area metallization layer (9) via a bonding wire (15); The cover plate (4) is a ceramic cover plate or a metal cover plate, and a cover plate welding ring (5) is formed around the cover plate (4), and the shape and size of the cover plate welding ring (5) are consistent with the sealing ring (3); The upper surface of the side cavity (2) is a sealing ring (3), and the cover plate (4) is sealedly connected to the sealing ring (3) by high-temperature welding.

4. The packaging structure of a small-sized SMD diode array packaging method as claimed in claim 3, characterized in that: The layout of the base area is: bonding area, chip area, and external electrode pad area; A surface metallization layer (9, 10, 13) is formed in the bonding area, the chip area, and the electrode pad area; The bonding area metallization layer (9) is distributed as follows: D, E, and F, and is located in the middle and upper part of the bottom plane of the inner cavity; The chip area metallization layer (10) is distributed as follows: A, B, C, and is located in the middle and lower part of the bottom plane of the inner cavity; The electrode pad area metallization layer 13 is located on the back of the ceramic base and is distributed as: a, b, c, d, e, f. Pads a, b, c are located below A, B, C respectively, and pads d, e, f are located below D, E, F respectively.

5. The packaging structure of a small-sized SMD diode array packaging method as claimed in claim 4, characterized in that: The size of the D, E, and F pads is 0.5 mm × 0.3 mm; The size of the A, B, and C pads is 0.85 mm × 0.3 mm; The pad sizes of a, b, c, d, e, and f are all 0.4 mm×0.6 mm, with a spacing of 0.25 mm.

6. The packaging structure of a small-sized SMD diode array packaging method according to claim 3, characterized in that: The bonding area metallization layer (9) and the chip area metallization layer (10) are both composed of multiple layers of metal materials, the surface layer material is gold, the second layer material is metal nickel, and the third layer material is metal tungsten. The surface layer and the second layer material are plated by electroplating, and the third layer material is a metal tungsten slurry that is first printed on the ceramic and then solidified. The thickness of the surface gold layer is 1.3-5.7um, the thickness of the second nickel layer is 4.0-11.3um, and the thickness of the third tungsten layer is 5-30um.

7. The packaging structure of a small-sized SMD diode array packaging method according to claim 3, characterized in that: The structure of the electrode pad area metallization layer 13 is to first print a metal tungsten layer in an outer set area, and then weld a metal block on the metal tungsten layer.

8. The packaging structure of a small-sized SMD diode array packaging method as claimed in claim 3, characterized in that: The shell sealing ring and the cover plate are airtightly melt-welded by alloy solder, and the pad electrode sheet and the pad metal layer are melt-welded by alloy solder.

9. The packaging structure of a small-sized SMD diode array packaging method as claimed in claim 3, characterized in that: The bonding connections are: A is connected to F, B is connected to E, and C is connected to D; The internal and external connection relationships are: A is connected to a, B is connected to b, C is connected to c, D is connected to d, E is connected to e, and F is connected to f.

10. The packaging structure of a small-sized SMD diode array packaging method according to claim 3, characterized in that: The package shell base is a square ceramic base, and the material of the ceramic base is more than 95% Al2O3 ceramic or AlN ceramic; The outer dimensions of the shell are: length 2.0 mm ± 0.12 mm, width 2.2 mm ± 0.12 mm, height 1.0 mm ± 0.1 mm, the inner cavity dimensions are length 1.4 mm, width 1.2 mm, the bottom plane height of the bonding area is 0.4 mm ± 0.06 mm, the bottom plane height of the chip area is 0.6 mm ± 0.06 mm, and the frame width is 0.4 mm; The package shell cover is a square metal cover, and the material of the metal cover is 4J42; The dimensions of the cover plate are: length 1.85 mm ± 0.1 mm, width 2.05 mm ± 0.1 mm, height 0.2 mm ± 0.05 mm, the width of the welding ring is 0.45 mm, and the welding ring material of the cover plate is gold-tin alloy; The sealing ring is made of 4J42 or 4J29.

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