Vertical type super junction device with gear-shaped p column and preparation method of vertical type super junction device

Abstract

The invention relates to a vertical super junction device with a gear-shaped p column and a preparation method thereof, and belongs to the technical field of semiconductor devices, the vertical super junction device comprises a drain electrode and a substrate from bottom to top, the p column and an n column are arranged on the substrate, the p column and the n column both comprise tooth-shaped structures which are vertically and periodically arranged, the tooth-shaped structure of the p column and the tooth-shaped structure of the n column are meshed with each other, and the p column and the n column are arranged on the drain electrode. The top end of the p column is flush with the top end of the n column, a p-GaN layer and an n +-GaN layer are sequentially arranged above the p column and the n column, one end of the n +-GaN layer is provided with a source electrode, the other end of the n +-GaN layer is provided with a groove, the groove is etched to the n column, SiO2 masks are arranged above the n +-GaN layer and on the surface of the groove, and gate metal is arranged above the SiO2 masks at the position of the groove. On one hand, more uniform electric field distribution can be improved, and on the other hand, the grid electrode can be better protected from invasion of a high electric field, and the breakdown voltage of the device is increased, so that the breakdown voltage of the device is further improved.

Description

Technical Field

[0001] The invention relates to a vertical super junction device with a gear-shaped p-column and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Power semiconductor transistors are considered to be the core of power electronic systems and are widely used in many fields such as consumer electronics, rail transportation, photovoltaic power generation and industrial control. They undertake functions such as frequency conversion, rectification, voltage conversion, power amplification and power management. Compared with silicon (Si), gallium nitride (GaN) has attracted much attention due to its advantages such as larger bandgap width, larger critical breakdown field strength and high saturation drift speed. Therefore, GaN-based power transistors can meet the needs of the next generation of power electronic systems. Thanks to the high-mobility two-dimensional electron gas (2DEG) at the AlGaN / GaN interface, GaN-based lateral high electron mobility transistors (HEMTs) have been commercialized at medium power (650V) levels. However, for applications at high voltage levels, a larger source-drain spacing is required, which increases the size of the chip and the cost of the required rated current. At the same time, the parasitic elements and pins of the HEMT are proportional to the spacing from the gate to the drain. The device with high withstand voltage achieved by increasing the source-drain spacing will increase the parasitic effect and limit the switching speed of the device. In addition, the 2DEG channel of a HEMT is located at the point where it contacts the device surface, making it particularly susceptible to surface states that cause current collapse.

[0003] Compared with GaN-based HEMTs, GaN vertical power transistors can provide higher breakdown voltages by increasing the thickness of the epitaxial region without increasing the chip package size. In addition, vertical GaN power transistors also exhibit avalanche capability, which can protect the device from breakdown and affect the stability of the system when the bias voltage is too high in a short period of time and exceeds the breakdown voltage. At present, there are many GaN vertical structures, such as fin power field effect transistors (FinFETs), current hole vertical electron transistors (CAVETs), junction FETs (JFETs) and trench MOSFETs (T-MOSFETs). Superjunction (SJ-superjunction) technology can deplete the drift region electrons well by introducing p-type columns in the drift region of vertical devices, perform electric field modulation and thus improve the overall performance of the device. However, in the reverse recovery process of superjunction devices, holes and electrons will form a large reverse recovery current during the extraction process. In circuits with large inductance loads, this may cause large current and voltage overshoots, which is not conducive to the stable operation of the circuit.

[0004] Superjunction devices (MOSFET, FinFET, CAVET, SBD, PiN diode, etc.) can modulate the triangular electric field distribution of traditional vertical devices into a rectangular shape by modulating the electric field distribution, which greatly improves the breakdown voltage of the device and reduces the specific on-resistance. They are widely used in high-power power electronic applications. Taking superjunction MOSFET as an example, in addition to the specific on-resistance and breakdown voltage, the reverse recovery characteristics of the body diode are also very important when it is used in power inverters. When the PiN diode works in the forward conduction state, due to the concentration gradient between the P+ anode region and the N+ cathode region and the base region, the anode and cathode will inject a large amount of unbalanced carriers into the base region to form stored charges. The injection of unbalanced carriers will cause the base region to be in a large injection state, thereby producing a conductivity modulation effect, which reduces the on-state voltage drop of the diode. When a reverse voltage is applied to the diode, the large amount of unbalanced carriers stored in the base region when the diode is turned on makes the diode still in the on state. In order to make the diode in the blocking state, these unbalanced carriers must be completely removed. This process takes a period of time. This process is called the reverse recovery process, and the time it takes for this process to occur is called the reverse recovery time. From the time point when the current crosses the zero line and becomes a negative current to the time when the current reaches the maximum reverse current I RR The time point when the value reaches 25% is called the reverse recovery time t rr Another important parameter is the stored charge Q in the device. rr , which is equivalent to the current area below the horizontal zero line. From the moment the reverse current returns to zero to the moment the reverse current reaches its maximum value I RR The time elapsed when a , from the reverse current reaches the maximum value I RR Start to decay to 0.25I RR The time elapsed when b The "softness factor" s is defined as: The larger the softness factor s is, the softer the reverse recovery characteristic is. In order to increase the softness factor, the fall time t b Greater than storage time t a In power circuits, the larger the softness factor of a diode, the better the reverse recovery characteristics of the device, which can effectively avoid voltage overshoot and oscillation caused by hard recovery and improve the stability and reliability of the device. However, superjunction devices usually exhibit fast reverse recovery, which can easily trigger voltage oscillations through stray inductance and lead to poor EMI performance or even device failure. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a vertical super junction device with a gear-shaped p-column and a preparation method thereof.

[0006] The technical solution of the present invention is as follows:

[0007] A vertical superjunction device with a gear-shaped p-column includes a drain and a substrate from bottom to top. A p-column and an n-column are arranged on the substrate. The p-column and the n-column both include tooth structures arranged vertically and periodically. The tooth structures of the p-column and the n-column are meshed with each other. The top of the p-column is flush with the top of the n-column. A p-GaN layer, an n-column and a p-GaN layer are arranged above the p-column and the n-column in sequence. + -GaN layer, n + -GaN layer has a source at one end, n + -A groove is provided at the other end of the GaN layer, and the groove is etched to the n column. + A dielectric layer is provided above the GaN layer and on the surface of the groove, and a gate metal is provided above the dielectric layer in the groove.

[0008] Preferably, the dielectric layer is SiO 2 or Al 2 O 3 .

[0009] Preferably, the thickness of a single tooth of the p-column tooth-shaped structure is 1-6 μm, the spacing between the teeth is the same as the thickness of a single tooth, and the doping concentration of the p-column and the n-column is 1e16 cm -3 -1e17cm -3 , more preferably 5e16cm -3 .

[0010] Further preferably, the thickness of a single tooth of the p-column tooth-like structure is 2 μm, and the spacing between the teeth is 2 μm.

[0011] Preferably, the substrate thickness is 1 μm; the p-GaN layer thickness is 0.5-1 μm, and the doping concentration is 1e18-3e18 cm -3 ;n + -GaN layer thickness is 0.1μm-0.5μm, doping concentration is 4e18-8e18 cm -3 ;SiO 2 The mask thickness is 50nm-100nm.

[0012] Further preferably, the p-GaN layer has a thickness of 0.7 μm and a doping concentration of 2e18 cm -3 ;n + -GaN layer thickness is 0.2 μm and doping concentration is 6e18 cm -3 ;SiO 2 The thickness of the dielectric layer is 80 nm.

[0013] Preferably, the gate trench width is 1 μm-3 μm, and the trench depth is 1 μm-2 μm.

[0014] Further preferably, the gate trench width is 2 μm and the trench depth is 1.4 μm.

[0015] Preferably, the gate metal is Ni or Ni / Au, and the source / drain metal is Ti / Al / Ni / Au or Pd / Al.

[0016] The p-column of the device proposed in the present application is completely connected and grounded. The segmented p-column will cause some p-columns to not be clamped to 0 potential when the device is under voltage, which is not conducive to the reverse voltage resistance performance of MOSFET; the superjunction p-column and n-column of the present application have the same doping concentration and the same area mainly for charge balance, giving full play to the advantages of the superjunction. The different areas of n-type and p-type may cause the device to fail to achieve charge balance. The p-column of the present application is generally in the shape of periodically arranged gears, which is a structural innovation based on the vertical trench superjunction MOSFET.

[0017] A method for preparing a vertical superjunction device having a gear-shaped p-column comprises the following steps:

[0018] (a) Growth of iN epitaxial structure, i represents drift region, N represents drain n-doped region substrate, substrate thickness is 1 μm, a layer of Si-doped n-type semiconductor is grown on the substrate surface, thickness is 2 μm, one side of the surface is shielded with photoresist, ion implantation is performed, and a wide p-column is formed by Mg ion implantation, and the doping concentration of both n-column and p-column is 5e16 cm -3 ;

[0019] (b) removing the surface photoresist, growing a layer of Si-doped n-type semiconductor with a thickness of 2 μm, shielding one side of the surface with the photoresist, the shielding length being greater than the shielding length in step (a), and performing ion implantation to form a narrow p-column by Mg ion implantation, the thickness of the narrow p-column being 2 μm;

[0020] (c) Repeat steps (a) and (b) three times to grow three layers of gear-shaped p-pillar and n-pillar regions;

[0021] (d) Further epitaxial growth of p-GaN and n+-GaN layers with thicknesses of 0.7 μm and 0.2 μm, respectively, and doping concentrations of 2e18 cm -3 and 6e18 cm -3 ;

[0022] (e) Using a mask to perform trench etching, MOS gate region trenches and source contact trenches are etched. The gate trench etching width is 2 μm and the etching depth is 1.4 μm. The source trench etching width is 0.5 μm and the etching depth is 0.2 μm. PECVD is used to deposit a layer of 80 nm thick SiO2 on the bottom and sidewalls of the gate trench. 2 film;

[0023] (f) Electron beam evaporation is used to form a gate metal, and electron beam evaporation is used to form a source and drain metal to form an ohmic contact source and drain.

[0024] In the reverse recovery process, holes are extracted through the anode (source of MOSFET) and electrons are extracted through the cathode. The mobility of holes is low. By reducing the hole extraction rate, the reverse recovery time can be increased and the softness factor can be increased. The structure proposed in this application changes the shape of the p-piller from the original rectangle to a ladder structure without changing the area of ​​the entire p-piller. On the one hand, it can maintain charge balance, and on the other hand, it can suppress the hole extraction rate. In the reverse recovery current falling stage, there are still more holes retained until the end of the shutdown period before recombining with electrons, making the reverse recovery current tail longer, resulting in the reverse recovery characteristics of the device becoming softer.

[0025] The beneficial effects of the present invention are:

[0026] The mature multi-layer ion implantation process is adopted, and the shape and number of layers of the p-column are adjusted by changing the size of the mask. Compared with the traditional SJ-MOSFET, no complicated process flow is required. The gear-shaped p-column effectively suppresses the extraction of holes during the reverse recovery period. In the reverse recovery current falling stage, there are still more holes that remain until the end of the shutdown period before recombining with electrons, which makes the reverse recovery current tail longer, resulting in the reverse recovery characteristics of the device becoming softer, reducing the maximum reverse recovery current, and significantly improving the reverse recovery voltage. In addition, the gear-shaped p-column extends a part of the p-GaN, which can improve the uniformity of the electric field distribution on the one hand, and better protect the gate from the invasion of high electric fields on the other hand, increase the breakdown voltage of the device, and further improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the process flow for preparing gear-shaped p-pillar GaN SJ-MOSFET, (a)-(f) correspond to steps (a)-(f);

[0028] Wherein: 1. drain; 2. substrate; 3. n column; 4. dielectric layer; 5. gate metal; 6. source; 7. p-GaN; 8. p column; 9. n + -GaN; arrows represent Mg ion implantation;

[0029] Figure 2 The breakdown voltage BV increases with the number of p-column periodicity and the width of the narrow p-column (W p ) changes, the horizontal coordinate is the width of the narrow p column (W p ), the vertical coordinate is the breakdown voltage;

[0030] Figure 3The forward resistance increases with the number of p-column periodicity and the width of the narrow p-column (W p ) changes, the horizontal coordinate is the width of the narrow p column (W p ), the vertical coordinate is the forward on-resistance;

[0031] Figure 4 The reverse recovery current increases with the narrow p-column width (W p ), the horizontal coordinate is the reverse recovery time, the vertical coordinate is the reverse recovery current, and the thickness of a single tooth of the p-column is 2μm;

[0032] Figure 5 The reverse recovery voltage increases with the width of the narrow p column (W p ), the horizontal axis is the reverse recovery time, the vertical axis is the reverse recovery voltage, and the thickness of a single tooth of the p-column is 2μm. DETAILED DESCRIPTION

[0033] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0034] Embodiment 1:

[0035] A vertical super junction device with a gear-shaped p-column, which is a MOSFET device in this embodiment, comprises, from bottom to top, a drain 1 and a substrate 2, on which a p-column 8 and an n-column 3 are arranged, wherein both the p-column and the n-column comprise a toothed structure arranged vertically and periodically, wherein the toothed structure of the p-column meshes with the toothed structure of the n-column, wherein the top of the p-column is flush with the top of the n-column, and a p-GaN layer 7, an n-column 3 are arranged in sequence above the p-column and the n-column. + -GaN layer 9,n + -GaN layer has a source electrode 6 at one end, n + -A groove is provided at the other end of the GaN layer, and the groove is etched to the n column. + -SiO is placed on the GaN layer and on the surface of the groove 2 Dielectric layer 4, SiO in the groove 2 A gate metal 5 is disposed above the dielectric layer.

[0036] The thickness of a single tooth of the p-column tooth structure is 2 μm, and the spacing between the teeth is the same as the thickness of a single tooth, that is, the spacing between the teeth is 2 μm. The doping concentration of the p-column and n-column is 5e16 cm -3 .

[0037] The substrate thickness is 1 μm; the p-GaN layer thickness is 0.7 μm, and the doping concentration is 2e18 cm -3 ;n + -GaN layer thickness is 0.2 μm and doping concentration is 6e18 cm -3 ;SiO 2The mask thickness is 80nm. The trench width is 2μm and the trench depth is 1.4μm. The gate metal is Ni and the source and drain metals are Ti / Al / Ni / Au.

[0038] Depend on Figure 2 It can be seen that the increase in the number of p-column layers increases the breakdown voltage of the device. When the number of layers is less than 3, the breakdown voltage increases with W. p When the number of layers is greater than or equal to 3, the breakdown voltage increases with W p decreases with the increase of .

[0039] Figure 3 It can be seen that the increase in the number of layers and W p An increase in will lead to an increase in resistance.

[0040] Figure 4 It can be seen that the reverse recovery overshoot current increases with the width of the narrow p column (W p ) increases and decreases.

[0041] Figure 5 It can be seen that the reverse recovery overshoot voltage increases with the width of the narrow p column (W p ) increases and decreases.

[0042] Embodiment 2:

[0043] A vertical superjunction device with a gear-shaped p-column, the structure of which is as described in Example 1, except that the thickness of a single tooth of the p-column tooth structure is 1 μm, the thickness of the p-GaN layer is 0.5 μm, and the doping concentration is 1e18 cm -3 ;n + -GaN layer thickness is 0.1 μm and doping concentration is 4e18 cm -3 ;SiO 2 The mask thickness is 50 nm.

[0044] The trench width is 1 μm, the trench depth is 1 μm, the gate metal is Ni / Au double-layer metal, and the source and drain metal is Pd / Al double-layer metal.

[0045] Embodiment 3:

[0046] A vertical superjunction device with a gear-shaped p-column, the structure of which is as described in Example 1, except that the thickness of a single tooth of the p-column tooth-shaped structure is 6 μm, the thickness of the p-GaN layer is 1 μm, and the doping concentration is 3e18 cm -3 ;n + -GaN layer thickness is 0.5 μm and doping concentration is 8e18 cm -3 ;SiO 2 The mask thickness is 100 nm.

[0047] The groove width is 3 μm and the groove depth is 2 μm.

[0048] Embodiment 4:

[0049] A method for preparing the vertical superjunction gallium nitride device having a gear-shaped p-column as described in Example 1 comprises the following steps:

[0050] (a) Growth of iN epitaxial structure, i represents drift region, N represents drain n-doped region substrate, substrate thickness is 1 μm, a layer of Si-doped n-type semiconductor is grown on the substrate surface, thickness is 2 μm, one side of the surface is shielded with photoresist, ion implantation is performed, and a wide p-column is formed by Mg ion implantation. The doping concentration of both p-column and n-column is 5e16 cm -3 ;

[0051] (b) removing the surface photoresist, growing a layer of Si-doped n-type semiconductor with a thickness of 2 μm, shielding one side of the surface with the photoresist, the shielding length being greater than the shielding length in step (a), and performing ion implantation to form a narrow p-column by Mg ion implantation, the thickness of the narrow p-column being 2 μm;

[0052] (c) Repeat steps (a) and (b) three times to grow three layers of gear-shaped p-pillar and n-pillar regions;

[0053] (d) Further epitaxial growth of p-GaN layer and n + -GaN layers with thickness of 0.7 μm and 0.2 μm and doping concentration of 2e18 cm -3 and 6e18 cm -3 ;

[0054] (e) Using SiO 2 A hard mask was used for ICP (Cl2 / BCl3 / Ar) trench etching to etch the MOS gate region trench with an etching width of 2 μm and an etching depth of 1.4 μm. A 80 nm thick SiO2 layer was deposited on the bottom and sidewalls of the trench using PECVD. 2 film;

[0055] (f) Electron beam evaporation is used to form a gate metal, and electron beam evaporation is used to form a source and drain metal to form an ohmic contact source and drain.

Claims

1. A vertical superjunction device having a gear-shaped p-column, characterized in that: From bottom to top, it includes a drain electrode and a substrate. A p-column and an n-column are arranged on the substrate. Both the p-column and the n-column include a tooth-like structure arranged vertically and periodically. The tooth-like structure of the p-column meshes with the tooth-like structure of the n-column. The top of the p-column is flush with the top of the n-column. A p-GaN layer, an n-column and a p-GaN layer are arranged above the p-column and the n-column in sequence. + -GaN layer, n + -GaN layer has a source at one end, n + -A groove is provided at the other end of the GaN layer, and the groove is etched to the n column. + A dielectric layer is provided above the GaN layer and on the surface of the groove, and a gate metal is provided above the dielectric layer in the groove.

2. The vertical superjunction device with gear-shaped p-columns according to claim 1, characterized in that: The thickness of a single tooth of the p-column tooth-like structure is 1-6 μm, and the spacing between the teeth is the same as the thickness of a single tooth. The doping concentration of the p-column and n-column is 1e16 cm -3 -1e17cm -3 , and more preferably 5e16cm -3 .

3. The vertical superjunction device with gear-shaped p-columns according to claim 2, characterized in that: The thickness of a single tooth of the p-column tooth-like structure is 2 μm, and the spacing between the teeth is 2 μm.

4. The vertical superjunction device with gear-shaped p-columns according to claim 1, characterized in that: The substrate thickness is 1 μm; the p-GaN layer thickness is 0.5-1 μm, and the doping concentration is 1e18-3e18 cm -3 ;n + -GaN layer thickness is 0.1μm-0.5μm, doping concentration is 4e18-8e18 cm -3 ; The thickness of the dielectric layer is 50nm-100nm.

5. The vertical superjunction device with gear-shaped p-columns according to claim 4, characterized in that: The p-GaN layer thickness is 0.7 μm and the doping concentration is 2e18 cm -3 ;n + -GaN layer thickness is 0.2 μm and doping concentration is 6e18 cm -3 ; The thickness of the dielectric layer is 80nm.

6. The vertical superjunction device with gear-shaped p-columns according to claim 1, characterized in that: The groove width is 1 μm-3 μm, and the groove depth is 1 μm-2 μm.

7. The vertical super junction device with gear-shaped p-columns according to claim 6, characterized in that: The groove width is 2 μm and the groove depth is 1.4 μm.

8. The vertical super junction device with gear-shaped p-columns according to claim 1, characterized in that: The gate metal is Ni or Ni / Au, and the source and drain metals are Ti / Al / Ni / Au or Pd / Al.

9. The vertical superjunction device with gear-shaped p-columns according to claim 1, characterized in that: The dielectric layer is SiO2 or Al2O3.

10. A method for preparing a vertical superjunction gallium nitride device having a gear-shaped p-column, characterized in that: The steps include: (a) Growth of iN epitaxial structure, substrate thickness is 1 μm, a layer of Si-doped n-type semiconductor is grown on the substrate surface, thickness is 2 μm, one side of the surface is shielded with photoresist, ion implantation is performed, and a wide p-column is formed by Mg ion implantation. The doping concentrations of Si and Mg are both 5e16 cm -3 ; (b) removing the surface photoresist, growing a layer of Si-doped n-type semiconductor with a thickness of 2 μm, shielding one side of the surface with the photoresist, the shielding length being greater than the shielding length in step (a), and performing ion implantation to form a narrow p-column by Mg ion implantation, the thickness of the narrow p-column being 2 μm; (c) Repeat steps (a) and (b) three times to grow three layers of gear-shaped p-pillar and n-pillar regions; (d) Further epitaxial growth of p-GaN layer and n + -GaN layers with thickness of 0.7 μm and 0.2 μm and doping concentration of 2e18 cm -3 and 6e18 cm -3 ; (e) performing trench etching using a mask to etch a MOS gate region trench and a source contact trench, wherein the gate trench etching width is 2 μm and the etching depth is 1.4 μm; The source trench etching width is 0.5 μm and the etching depth is 0.2 μm; A 80nm thick SiO2 film is deposited on the bottom and sidewalls of the gate trench using PECVD; (f) Electron beam evaporation is used to form a gate metal, and electron beam evaporation is used to form a source and drain metal to form an ohmic contact source and drain.

Images