Heterogeneous crystalline silicon battery and grid line preparation method thereof
By forming a metal conductive layer on the doped amorphous silicon layer of heterocrystalline silicon battery and opening holes, the problems of cumbersome gate wire preparation process and poor pulling force are solved, and better conductivity and improved battery performance are achieved. Produce.
Patent Information
- Application Number
- CN202411417779.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-14
AI Technical Summary
The existing heterocrystalline silicon batteries need to prepare seed layers during gate line preparation. The process is cumbersome and costly. When the seed layer is not prepared, the gate line pulling force is poor, which is easy to corrode, making it difficult to ensure current collection and protection of the gate line.
By adopting a method that does not require the preparation of a seed layer, by forming a metal conductive layer on the doped amorphous silicon layer and opening holes on the conductive layer, the top of the gate line is exposed, and the depth of the conductive layer opening is greater than or equal to the gate line height. The metal conductive layer covers and protects the gate lines, and the conductive materials are deposited by chemical vapor deposition, physical vapor deposition or solution processes.
It achieves simple process, good gate wire pull-off force, and conductive material protects the gate wire to prevent corrosion, while improving current collection efficiency and overall battery performance.
Smart Images
Figure CN119317188A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of solar cells, and in particular to a heterogeneous crystalline silicon cell and a method for preparing a grid line thereof. Background Art
[0002] With the development of photovoltaic technology, the photoelectric conversion efficiency of batteries has gradually increased and the cost has gradually decreased. However, due to the high price of silver paste used in the screen printing process, the cost of silver paste accounts for about 40% of the non-silicon cost of the battery, making the cost of the battery high. Especially for heterojunction batteries, due to their special battery structure, they can only be printed with special low-temperature pastes, and the cost of low-temperature pastes is much higher than that of ordinary pastes. Therefore, through electroplating, chemical plating and other technologies, the silver in the metallization process is replaced with cheap metals such as copper, making electroplating and chemical plating technologies a new way to solve the problem of reducing costs.
[0003] Heterojunction cells are generally composed of a single crystal silicon layer, an intrinsic layer, a doped amorphous silicon layer, a surface conductive layer and a gate line. Since doped amorphous silicon has poor conductivity, the preparation of the gate line is mostly carried out on the surface conductive layer. However, due to the presence of the conductive layer, the formation of the gate line by electroplating requires shielding of the non-gate line area, or the preparation of a seed layer with better conductivity on the conductive layer. In the subsequent electroplating process, the metal is preferentially deposited on the seed layer, otherwise the electroplating process will cause metal to be deposited on the entire surface.
[0004] In the prior art, if a seed layer is not prepared, a mask material is prepared on the conductive material, and then the mask material is patterned to expose the conductive material on the surface of the gate line area, and then metal is deposited in the gate line area by electroplating.
[0005] If a seed layer is prepared, a seed layer is first deposited on the surface conductive material, and then the seed layer in the gate line area is protected by a mask. The seed layer in the non-gate line area is then etched away by processing, leaving only the seed layer in the gate line area, and then the gate line is grown on the seed layer in the gate line area by subsequent electroplating.
[0006] However, in the method for preparing the gate line without preparing the seed layer, the mask area needs to be removed after the gate line is formed to expose the gate line, which will cause the prepared gate line to have a poor pull-off force, and the conductive material on the surface is easily damaged during the mask removal process.
[0007] The method of preparing the seed layer is relatively complicated and will cause waste of resources. When the preparation process of the seed layer is poor, the pull-off force will also be poor.
[0008] Therefore, it is urgent to propose a method that does not require the preparation of a seed layer while ensuring that the process is relatively simple; and the prepared battery structure can have good pull-off force while ensuring the collection of current, and the conductive material can protect the gate line and prevent corrosion of the gate line. Summary of the invention
[0009] The object of the present invention is to provide a heterogeneous crystalline silicon cell and a method for preparing a gate line thereof. The process is relatively simple, and the prepared cell structure has good pull-off force, and the conductive material can better protect the gate line.
[0010] In order to achieve the above-mentioned object of the invention, the present invention provides a heterogeneous crystalline silicon cell, comprising:
[0011] Single crystal silicon layer;
[0012] The front and back sides of the single crystal silicon layer are sequentially provided with an intrinsic layer and a doped amorphous silicon layer;
[0013] A gate line and a metal conductive layer are arranged on the doped amorphous silicon layer, and the gate line passes through the metal conductive layer and is connected to the doped amorphous silicon layer;
[0014] The gate lines include front gate lines and back gate lines, the metal conductive layer has conductive layer openings avoiding the gate lines so that the tops of the gate lines are exposed, and the depth of the conductive layer openings is greater than or equal to the height of the gate lines.
[0015] Optionally, the intrinsic layer is a polysilicon layer.
[0016] Optionally, one of the doped amorphous silicon layers disposed on the front side and the back side of the single crystal silicon layer is N-type doped, and the other doped amorphous silicon layer is P-type doped.
[0017] Optionally, the conductive material used in the metal conductive layer includes a metal element or an oxide complex of the metal element; the metal element is one of indium, antimony, zinc, tin or cadmium, and the oxide complex is an oxide of two of the metal elements among indium, antimony, zinc, tin or cadmium.
[0018] The present invention also provides a method for preparing a heterogeneous crystalline silicon battery grid line, comprising:
[0019] forming a gate line on the front-end structure;
[0020] Obtaining a metal conductive layer, wherein the metal conductive layer covers the gate line;
[0021] forming a first mask layer on the metal conductive layer;
[0022] Performing patterning on the first mask layer to obtain a first opening, wherein the first opening corresponds to a position of the gate line;
[0023] removing the conductive material of the metal conductive layer by using the first mask layer as a mask; and
[0024] The first mask layer is removed.
[0025] Optionally, the process of forming a gate line on the front-end structure includes:
[0026] forming a second mask layer on the doped amorphous silicon layer;
[0027] Performing patterning on the second mask layer to obtain a second opening, wherein the second opening corresponds to a gate line position and exposes the bottom amorphous silicon layer;
[0028] Grid lines are formed on both the front and back surfaces.
[0029] Optionally, after the process of forming the gate line on the front-end structure and before the process of obtaining the metal conductive layer, the method further includes: removing the second mask layer.
[0030] Optionally, the method of removing the first mask layer and removing the second mask layer includes chemical etching, mechanical stripping or laser stripping.
[0031] Optionally, in the process of obtaining the metal conductive layer, the conductive material is deposited by chemical vapor deposition, physical vapor deposition or solution process.
[0032] Optionally, the removing of the conductive material of the metal conductive layer by using the first mask layer as a mask adopts a method including wet processing, dry etching, laser lift-off, chemical mechanical polishing, ion milling or electrochemical polishing.
[0033] The present invention provides a method for preparing a heterogeneous crystalline silicon cell and a gate line thereof. The electroplating treatment is not performed in the manner of preparing a seed layer, and the process is relatively simple. At the same time, the gate line of the heterogeneous crystalline silicon cell prepared by the present invention is mostly surrounded by a metal conductive material, and can have a good pull-off force while ensuring the collection of current. At the same time, the metal conductive layer can also well protect the gate line and prevent the corrosion of the gate line. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 It is a block diagram of a method for preparing a heterogeneous crystalline silicon battery grid line in an embodiment of the present invention;
[0035] Figure 2 Schematic diagram of the structure of a heterogeneous crystalline silicon cell after forming a second mask layer in an embodiment of the present invention;
[0036] Figure 3 It is a schematic diagram of the structure of a heterogeneous crystalline silicon cell after patterning on the second mask layer in an embodiment of the present invention;
[0037] Figure 4 Schematic diagram of the structure of a heterogeneous crystalline silicon cell after forming gate lines in an embodiment of the present invention;
[0038] Figure 5 This is a schematic diagram of the structure of a heterogeneous crystalline silicon cell after the second mask layer is removed in an embodiment of the present invention;
[0039] Figure 6 Schematic diagram of the structure of a heterogeneous crystalline silicon cell after obtaining a metal conductive layer in an embodiment of the present invention;
[0040] Figure 7 It is a schematic diagram of the structure of a heterogeneous crystalline silicon cell after a first mask layer is prepared on a metal conductive layer in an embodiment of the present invention;
[0041] Figure 8 It is a schematic diagram of the structure of a heterogeneous crystalline silicon cell after patterning on the first mask layer in an embodiment of the present invention;
[0042] Fig. 9 This is a schematic diagram of the structure of a heterogeneous crystalline silicon cell after the first mask layer is removed in an embodiment of the present invention;
[0043] Fig.10 Schematic diagram of the depth of the opening of the conductive layer in an embodiment of the present invention.
[0044] In the figure, 1, single crystal silicon layer; 2, intrinsic layer; 3, doped amorphous silicon layer; 4, second mask layer; 41, second opening; 5, gate line; 6, metal conductive layer; 61, conductive layer opening; 7, first mask layer; 71, first opening. DETAILED DESCRIPTION
[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0046] The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.
[0047] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0048] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.
[0049] Embodiment 1
[0050] Please refer to Figure 1 - Fig. 9 This embodiment provides a method for preparing a heterogeneous crystalline silicon battery grid line, comprising the steps of:
[0051] S1, forming a gate line 5 on the front end structure;
[0052] S2, obtaining a metal conductive layer 6, wherein the metal conductive layer 6 covers the gate line 5;
[0053] S3, forming a first mask layer 7 on the metal conductive layer 6;
[0054] S4, performing patterning on the first mask layer 7 to obtain a first opening 71, wherein the first opening 71 corresponds to a position of the gate line 5;
[0055] S5, using the first mask layer 7 as a mask to remove the conductive material of the metal conductive layer 6; and
[0056] S6. Remove the first mask layer 7.
[0057] The preparation method provided in the embodiment of the present invention does not use the electroplating treatment in the manner of preparing a seed layer, and the process is relatively simple; since the gate line is mostly surrounded by metal conductive material, it can have good pull-off force while ensuring the collection current, and the metal conductive layer can also protect the gate line well and prevent corrosion of the gate line.
[0058] In this embodiment, please continue to refer to Figure 2 In step S1, the front-end structure specifically includes: a single crystal silicon layer 1, and an intrinsic layer 2 and a doped amorphous silicon layer 3 sequentially arranged on the front and back sides of the single crystal silicon layer 1.
[0059] The front-end structure can be obtained in the following manner:
[0060] S101, silicon wafer pretreatment: cleaning and surface treatment of the silicon wafer to make the surface of the silicon wafer clean, free of impurities, and have an appropriate roughness (the roughness can be set according to actual needs).
[0061] In one example, after pre-processing, the silicon wafer becomes the single crystal silicon layer 1 required subsequently.
[0062] The silicon wafer is pre-treated to facilitate the deposition of subsequent layers and the attachment of gate lines.
[0063] S102 , depositing an intrinsic layer 2 and a doped amorphous silicon layer 3 on both the front and back surfaces of the single crystal silicon layer 1 .
[0064] Among them, the doped amorphous silicon layer 3 as the bottom layer of the conductive material will help to improve the efficiency and stability of the battery.
[0065] S103 , depositing a layer of mask material on a side of the doped amorphous silicon layer 3 away from the intrinsic layer 2 by physical or chemical vapor deposition (such as PECVD) to form a second mask layer 4 .
[0066] The second mask layer 4 will protect the doped amorphous silicon layer 3 from being damaged during subsequent processing.
[0067] S104 , coating photoresist on the second mask layer 4 , and then forming a pattern corresponding to the gate line pattern through exposure and development.
[0068] S105, using the photoresist as a mask, removing the mask layer corresponding to the gate line regions on the front and back sides by etching or other removal methods, forming a plurality of second openings 41, exposing the doped amorphous silicon layer 3, such as Figure 3 shown.
[0069] Removing the mask layer in the gate line region in step S105 is to prepare for the deposition of the gate line.
[0070] S106, placing the silicon wafer processed in the above steps into an electroplating tank, and depositing gate lines 5 on the exposed doped amorphous silicon layer 3 on both the front and back surfaces through electrochemical reaction, such as Figure 4 shown.
[0071] During the electroplating process, metal ions are reduced under the action of electric current and deposited on the surface of the silicon wafer to form a desired gate line pattern.
[0072] The gate line 5 is prepared by, for example, an electroplating method such as rack plating or horizontal plating.
[0073] like Figure 4 As shown, it can be seen that the gate line 5 is formed in the second opening 41 , one end of which is in contact with the doped amorphous silicon layer 3 , and the other end of which is exposed above the second mask layer 4 .
[0074] Furthermore, the method further includes: S107, after the electroplating is completed, cleaning and drying the silicon wafer to remove residual electrolyte and unreacted substances.
[0075] In another specific example, other post-processing steps are also included, such as heat treatment, which is performed to improve the adhesion and fill factor of the gate lines.
[0076] In step S2, specifically including: please refer to Figure 5 , step S201, removing the second mask layer 4.
[0077] In step S201 , the second mask layer 4 is removed by chemical etching, mechanical stripping or laser stripping.
[0078] When removing the mask layers on the front and back sides, the mask in the gate line area should be removed as completely as possible without causing damage to the gate line and the silicon wafer.
[0079] S202 , after removing the second mask layer 4 , thoroughly cleaning the surface of the silicon wafer.
[0080] In step S22, all residues and etchants are removed to ensure that the surface is clean and free of impurities to facilitate the subsequent deposition of conductive materials.
[0081] S203, depositing a layer of conductive material on the cleaned silicon wafer surface by chemical vapor deposition (CVD), physical vapor deposition (PVD) or solution process (such as coating, spraying, dripping, etc.) to obtain a metal conductive layer 6.
[0082] The conductive material includes aluminum zinc oxide (AZO), aluminum-doped tin oxide (ATO), or other transparent conductive oxides (TCO).
[0083] In step S203 , the metal conductive layer 6 covers the gate line 5 .
[0084] The metal conductive layer 6 not only enhances the adhesion between the gate line 5 and the silicon wafer, but also provides good electrical conductivity to ensure effective conduction of current.
[0085] In another specific example, after step S203, the method further includes:
[0086] S204, performing heat treatment or mechanical compaction on the metal conductive layer 6.
[0087] In order to further improve the contact quality and adhesion strength between the conductive material and the gate line 5 , the deposited conductive material may be subjected to post-processing steps such as heat treatment or mechanical compaction.
[0088] Furthermore, it also includes: S205, cleaning and inspection: cleaning and drying the silicon wafer to remove residual substances that may affect the battery performance.
[0089] Please refer to Figure 8 In step S4, patterning is performed on the first mask layer 7 to obtain a first opening 71, wherein the first opening 71 corresponds to the position of the gate line 5 and exposes the position of the gate line 5 to be exposed.
[0090] Furthermore, step S5 specifically includes the following steps:
[0091] S501 , selectively removing the conductive material in the exposed area by means of the first mask layer 7 .
[0092] After the conductive material is selectively removed, the top of the gate line 5 is exposed.
[0093] It can be understood that in the preparation method of this embodiment, when the metal conductive layer 6 is obtained, the metal conductive layer 6 covers the gate line 5, and the conductive material in the exposed area is selectively removed after masking, exposing only the top of the gate line 5, and the rest of the gate line 5 is still surrounded by the conductive material.
[0094] The process of removing the conductive material from the exposed areas may include wet processing, dry etching, laser lift-off, chemical mechanical polishing, ion milling or electrochemical polishing.
[0095] S502, cleaning and drying: The wafer is cleaned thoroughly to remove residual chemical solution and loose substances, and then the wafer is dried.
[0096] S503, inspection and repair: Use a high-magnification microscope or other tool to inspect the exposed gate line 5 to ensure that there are no defects and residues.
[0097] For further information, please continue to refer to Fig. 9 , further comprising S6, removing the first mask layer 7.
[0098] According to the above method, this embodiment directly forms a gate line on the doped amorphous silicon layer of the heterojunction battery. After the gate line is prepared, the surface conductive material is prepared. At the same time, the gate line whose top needs to be exposed is masked to remove the conductive material on the top of the gate line, thereby obtaining a gate line with better conductive performance and better pull-off force; the top of the gate line thus prepared is exposed, and its bottom is arranged on the doped amorphous silicon layer, while the remaining part is surrounded by the conductive material, which can have a good pull-off force while ensuring the collection current, and the conductive material can well protect the gate line and prevent the corrosion of the gate line; in addition, during the preparation process, the non-gate line area does not contact the plating solution during electroplating to prevent virtual plating or damage to the battery by the plating solution.
[0099] Embodiment 2
[0100] The second embodiment of the present invention provides a heterogeneous crystalline silicon cell, wherein the heterogeneous crystalline silicon cell can be realized according to the above-mentioned first embodiment, or obtained based on other methods. Fig. 9 , the heterogeneous crystalline silicon cell comprises:
[0101] Single crystal silicon layer 1;
[0102] The front and back sides of the single crystal silicon layer 1 are sequentially provided with an intrinsic layer 2 and a doped amorphous silicon layer 3 ; a gate line 5 and a metal conductive layer 6 are provided on the doped amorphous silicon layer 3 , and the gate line 5 passes through the metal conductive layer 6 and is connected to the doped amorphous silicon layer 3 .
[0103] The gate lines 5 include front gate lines and back gate lines. The front gate lines are connected to the front doped amorphous silicon layer 3, and correspondingly, the back gate lines are connected to the back doped amorphous silicon layer 3.
[0104] The metal conductive layer 6 has a conductive layer opening 61 that avoids the gate line 5 so that the top of the gate line 5 is exposed.
[0105] In this embodiment, please continue to refer to Fig. 9 A plurality of conductive layer openings 61 are opened on the metal conductive layer 6 , and positions of the plurality of conductive layer openings 61 correspond one-to-one to a plurality of gate lines 5 , respectively, so that the tops of the gate lines 5 are exposed through the conductive layer openings 61 .
[0106] Please refer to Fig.10The depth H of the conductive layer opening 61 is greater than or equal to the height h of the gate line 5 . It can be understood that the width of the conductive layer opening 61 is greater than the width of the gate line 5 .
[0107] The conductive layer opening 61 is configured to allow only the top of the gate line 5 to be exposed. The gate line 5 is located in the conductive layer opening 61. The bottom of the gate line 5 is connected to the doped amorphous silicon layer 3, and the top is exposed through the conductive layer opening 61. The rest of the gate line 5 is surrounded by the conductive material of the metal conductive layer 6, which can have a good pull-off force while ensuring that the gate line 5 collects current. At the same time, the conductive material can protect the gate line 5 well and prevent the gate line 5 from being corroded.
[0108] Furthermore, the single crystal silicon layer 1 is an N-type single crystal silicon layer.
[0109] Furthermore, the intrinsic layer 2 includes amorphous silicon, microcrystalline silicon and / or nanocrystalline silicon.
[0110] Furthermore, one of the doped amorphous silicon layers 3 disposed on the front and back sides of the single crystal silicon layer 1 is N-type doped, and the other doped amorphous silicon layer 3 is P-type doped.
[0111] Furthermore, the conductive material used in the metal conductive layer 6 includes a metal element or an oxide complex of the metal element, the metal element is one of indium, antimony, zinc, tin or cadmium, and the oxide complex is an oxide of two of the metal elements among indium, antimony, zinc, tin or cadmium.
[0112] Specifically, the oxide composite includes: indium tin oxide (ITO, Indium Tin Oxide), zinc tin oxide (ZTO, Zinc Tin Oxide), cadmium tin oxide (CTO, Cadmium Tin Oxide) or indium antimony oxide (ATO, Antimony Tin Oxide).
[0113] In other examples, the material of the metal conductive layer 6 can be selected according to specific applications and cost requirements to optimize the performance and cost of the battery.
[0114] Therefore, the heterogeneous crystalline silicon cell provided in this embodiment has a high current collection efficiency. Since most of the gate line is surrounded by the conductive material, it helps to improve the current collection efficiency, and the conductive material surrounding the gate line can reduce the contact resistance between the gate line and the silicon wafer, thereby reducing the series resistance and improving the overall efficiency of the cell; the conductive material provides additional mechanical stability, enhances the adhesion between the gate line and the silicon wafer, and helps prevent the gate line from falling off under long-term use or external factors; the conductive material layer can protect the gate line from corrosion by environmental factors (such as moisture, oxygen, etc.), thereby extending the service life of the battery; the intrinsic layer in the heterogeneous crystalline silicon cell is a polycrystalline silicon layer, which can absorb light of different wavelengths, broadens the response range of the cell to the solar spectrum, and thus improves the photoelectric conversion efficiency.
[0115] The heterogeneous crystalline silicon cell provided in the embodiments of the present invention has significant advantages in improving current collection efficiency, enhancing mechanical stability, providing corrosion protection, optimizing optical and electrical properties, etc.
[0116] In summary, the present invention proposes a heterogeneous crystalline silicon cell and a method for preparing a gate line thereof, wherein a gate line is directly formed on a doped amorphous silicon layer of a heterojunction cell, thereby obtaining a gate line with better conductivity and better pull-off force; since most of the gate line is surrounded by a conductive material, it helps to improve the current collection efficiency, and the surrounding conductive material can reduce the contact resistance between the gate line and the silicon wafer, thereby reducing the series resistance and improving the overall efficiency of the cell; therefore, the present invention provides an efficient and reliable solar cell structure, which has significant advantages in improving current collection efficiency, enhancing mechanical stability, providing corrosion protection, optimizing optical and electrical properties, etc., and the preparation process is simple, and there is no need to prepare a seed layer. The process is simple, the effect is significant, and it is suitable for mass production.
[0117] Obviously, the above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A heterogeneous crystalline silicon cell, characterized in that: include: Single crystal silicon layer; The front and back sides of the single crystal silicon layer are sequentially provided with an intrinsic layer and a doped amorphous silicon layer; A gate line and a metal conductive layer are arranged on the doped amorphous silicon layer, and the gate line passes through the metal conductive layer and is connected to the doped amorphous silicon layer; The gate lines include front gate lines and back gate lines, the metal conductive layer has conductive layer openings avoiding the gate lines so that the tops of the gate lines are exposed, and the depth of the conductive layer openings is greater than or equal to the height of the gate lines.
2. The heterogeneous crystalline silicon cell according to claim 1, characterized in that: The intrinsic layer is a polysilicon layer.
3. The heterogeneous crystalline silicon cell according to claim 1, characterized in that: One of the doped amorphous silicon layers arranged on the front and back sides of the single crystal silicon layer is N-type doped, and the other doped amorphous silicon layer is P-type doped.
4. The heterogeneous crystalline silicon cell according to claim 1, characterized in that: The conductive material used in the metal conductive layer includes a metal element or an oxide complex of the metal element; the metal element is one of indium, antimony, zinc, tin or cadmium, and the oxide complex is an oxide of two of the metal elements among indium, antimony, zinc, tin or cadmium.
5. A method for preparing a heterogeneous crystalline silicon battery grid line, characterized in that: include: forming a gate line on the front-end structure; Obtaining a metal conductive layer, wherein the metal conductive layer covers the gate line; forming a first mask layer on the metal conductive layer; Performing patterning on the first mask layer to obtain a first opening, wherein the first opening corresponds to a position of the gate line; Using the first mask layer as a mask, removing the conductive material of the metal conductive layer; as well as The first mask layer is removed.
6. The method for preparing a heterogeneous crystalline silicon battery grid line according to claim 5, characterized in that: The process of forming a gate line on the front-end structure includes: forming a second mask layer on the doped amorphous silicon layer; Performing patterning on the second mask layer to obtain a second opening, wherein the second opening corresponds to a gate line position and exposes the bottom amorphous silicon layer; Grid lines are formed on both the front and back surfaces.
7. The method for preparing a heterogeneous crystalline silicon battery grid line according to claim 6, characterized in that: After the process of forming the gate line on the front-end structure and before the process of obtaining the metal conductive layer, the method further includes: removing the second mask layer.
8. The method for preparing a heterogeneous crystalline silicon battery grid line according to claim 7, characterized in that: The method of removing the first mask layer and the method of removing the second mask layer include chemical etching, mechanical stripping or laser stripping.
9. The method for preparing a heterogeneous crystalline silicon battery grid line according to claim 5, characterized in that: In the process of obtaining the metal conductive layer, the conductive material is deposited by chemical vapor deposition, physical vapor deposition or solution process.
10. The method for preparing a heterogeneous crystalline silicon battery grid line according to claim 5, characterized in that: The method of removing the conductive material of the metal conductive layer by using the first mask layer as a mask includes wet processing, dry etching, laser stripping, chemical mechanical polishing, ion milling or electrochemical polishing.