Preparation method of TBC battery

Abstract

The invention relates to a preparation method of a TBC battery. The preparation method comprises the following steps: 1) surface treatment of monocrystalline silicon; 2) forming a tunneling oxide layer; 3) forming an interdigital passivation contact layer; 4) forming a passivation layer and an anti-reflection film layer; and 5) forming a metal electrode. On one hand, the N + poly and P + poly interdigital areas of a TBC battery core can be prepared and completed in one procedure by adopting a deposition technology in combination with a patterned mask plate and superposition in-situ doping, and meanwhile, the interdigital passivation contact layer can be formed only by one-time annealing process through boron-phosphorus co-annealing, so that the number of preparation procedures of the TBC battery is greatly reduced, and the production cost of the TBC battery is reduced; and on the other hand, the N + poly layers and the P + poly layers which are alternately distributed at intervals are formed in the adjacent plate-type cavities of the same equipment, so that forming interference between the N + poly layers and the P + poly layers is avoided, the preparation efficiency of the TBC battery is also improved, meanwhile, compounding of metallization areas of the metal grid lines is effectively reduced, and the battery efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a TBC cell. Background Art

[0002] TBC cells are a type of solar cell technology that combines passivation contact structure technology (Topcon structure) with back contact cell technology. This type of cell technology can effectively reduce the recombination of the metallized area of ​​the metal grid and avoid the shading effect of the metal grid on the front of the cell. Therefore, the conversion efficiency of TBC cells will be significantly improved compared to the current mainstream cells (TOPcon and Prec structure cells). However, the TBC cell itself has a complex structure and a cumbersome preparation process, which seriously limits the current industrialization process of TBC cells.

[0003] At present, the mainstream TBC battery technology generally uses the method of mask plus laser film opening to prepare n+ and p+ passivation contact areas. It is necessary to prepare poly layers of different types of doping areas separately and dope each area separately. Therefore, it has the following technical defects:

[0004] 1) The preparation of the TBC battery interdigital passivation contact structure requires the use of mask technology, laser grooving, etching technology, etc., which makes the preparation process of the TBC battery interdigital structure very complicated;

[0005] 2) Two annealing steps are required during the preparation process, i.e., preparation of P+poly → annealing → preparation of N+poly → annealing, which is not only inefficient but also costly. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide an improved method for preparing a TBC battery.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0008] A method for preparing a TBC battery comprises the following steps: 1) selecting a single crystal silicon as a substrate and performing surface treatment so that a velvet surface is formed on the front side and a flat surface is formed on the back side;

[0009] 2) Formation of a tunnel oxide layer on the back side;

[0010] 3) forming an interdigitated passivation contact layer of an N+poly layer and a P+poly layer on the back side of the tunnel oxide layer;

[0011] 4) Forming a passivation layer and an anti-reflection film layer on the front and back sides in sequence;

[0012] 5) forming a metal electrode, in particular, in step 3), first, a patterned mask is used in a designated area on the back side of the tunnel oxide layer, and an alternating and spaced N+poly layer and a P+poly layer are formed in adjacent plate-type cavities of the same device; secondly, the silicon wafer after the deposition of the N+poly layer and the P+poly layer is placed in an annealing furnace to complete boron-phosphorus co-annealing, so that the in-situ doped N+poly layer and the P+poly layer are crystallized, and the doping sources of the N+poly layer and the P+poly layer are activated to form an interdigitated passivation contact layer.

[0013] Preferably, a Gap region is formed between the patterned N+poly layer and the P+poly layer prepared in step 3), wherein the width of the N+poly layer is 30-300um; the width of the P+poly layer is 500-1500um; and the width of the Gap region is 30-100um.

[0014] In some specific embodiments, the N+poly layer is a Poly layer in-situ doped with phosphorus atoms, and the phosphorus doping concentration is 1e 20 -1e 21 / cm -3 ; and / or, the P+poly layer is a poly layer in-situ doped with B atoms, and the boron doping concentration is 5e 19 -5e 20 .

[0015] Preferably, the N+poly layer and the P+poly layer are formed to a thickness of 30-200 nm.

[0016] According to a specific implementation and preferred aspect of the present invention, step 2) and step 3) are performed in the same device, and the device has three plate-type chambers connected in series, which is not only convenient for processing, but also helps in the subsequent boron-phosphorus co-annealing (i.e., primary annealing).

[0017] Preferably, the cavity is divided into a first cavity, a second cavity and a third cavity. The first cavity uses a thermal oxidation method to prepare a tunneling oxide layer on the back of the substrate; the second cavity and the third cavity both use a PVD method in conjunction with a patterned mask plate, and the mask plate is located between the PVD sputtering source and the silicon wafer, so that the PVD sputtering area is patterned, and combined with the in-situ doping process, a patterned N+poly layer and a P+poly layer are deposited in a specific area.

[0018] Specifically, the PVD technology is preferably magnetron sputtering technology, and a patterned mask plate is placed between the sputtering source and the silicon wafer. Since the particles are sputtered in a straight line, the particles can be blocked by the mask area of ​​the imaged mask plate, and the PVD sputtering in the non-mask area can deposit the film layer normally, thereby forming a patterned deposited film layer on the surface of the silicon wafer.

[0019] In some specific embodiments, the process temperature used in the thermal oxidation method is 500°C-650°C, and O2 is introduced for oxidation during the process, the pressure in the first chamber is between 1-10mBar, and / or the thickness of the prepared tunneling oxide layer is 1.4-2.0nm.

[0020] Preferably, the annealing temperature is controlled between 895°C and 935°C, and the annealing time is 20-50 minutes. Preferably, the annealing temperature required for the P+poly layer is the same as the annealing temperature required for the N+poly layer, and the annealing of the two POLY layers is completed at one time. In short, the annealing of the P+poly layer and the N+poly layer is boron-phosphorus co-annealing, which is carried out simultaneously in one furnace tube using the same annealing conditions.

[0021] Preferably, the annealing process is carried out in a high-temperature furnace tube, and N2 is introduced as a protective gas during the annealing process; and / or, after annealing, the square resistance of the P+poly region is controlled at 120-300Ω / sq, and the square resistance of the N+poly region is controlled at 30-60Ω / sq.

[0022] In short, under normal conditions, the annealing temperature required for the P+poly layer is higher than that required for the N+poly layer. The principle is that the solid solubility of boron is lower. In order to achieve sufficient doping, P+poly needs a higher temperature to increase the solid solubility of B atoms in silicon, but high temperature will destroy the tunneling oxide layer, so the temperature needs to match the thickness of the tunneling oxide layer. The phosphorus atom itself has a high solid solubility and does not require high temperature to achieve sufficient doping. It uses a thinner tunneling oxide layer with low temperature to achieve a better passivation contact effect. The key to achieving boron-phosphorus co-annealing (addition: annealing P+poly and N+POLY in one process, replacing the previous step-by-step annealing method, reducing the process flow.) is to provide a suitable annealing temperature and annealing time interval combined with the thickness of the tunneling oxide layer. Through one annealing, both boron and phosphorus can obtain excellent activation amounts, and both can achieve higher concentrations of doping, and the tunneling oxide layer will not be damaged by high temperature.

[0023] In some specific embodiments, the silicon wafer is cleaned with a mixed solution of HF / HCL after annealing to remove the natural oxide layer on the surface of the silicon wafer and the tunnel oxide layer in the gap region.

[0024] Preferably, the volume ratio of HF:HCL:H2O is 1:1:4-4:1:4, and the cleaning time is 2-5 min.

[0025] In some specific embodiments, the substrate is an N-type silicon wafer; and / or the thickness of the silicon wafer is 100-200 um; and / or the resistivity of the silicon wafer is 0.5-7 Ω·cm.

[0026] According to another specific implementation and preferred aspect of the present invention, the surface treatment in step 1) includes the following steps: a) performing double-sided texturing on the silicon wafer to form a double-sided texturing silicon wafer; b) forming a mask layer on the front side of the silicon wafer after texturing; c) acid washing and alkaline polishing are used on the back side of the silicon wafer to form a flat surface.

[0027] Preferably, the Mask layer is a SiNx layer or a SiO2 layer prepared by PECVD; and / or, the thickness of the Mask layer is 30-150 nm.

[0028] Furthermore, the Mask layer is a SiO2 layer, and the thickness of the Mask layer is 40-80 nm.

[0029] Preferably, in step b), a mask layer is formed on opposite sides of the back side of the silicon wafer by wrap-around plating; in step c), the back side is cleaned with HF, wherein an HF solution with a volume fraction exceeding 20% ​​is used for cleaning to remove the wrap-around plating on the back side.

[0030] In some specific embodiments, the passivation layer is an aluminum oxide film layer; and / or the thickness of the passivation layer is 2-10 nm. In short, double-sided aluminum oxide is deposited on the surface of the silicon wafer using ALD to achieve comprehensive passivation of the FSF / BSF / Emitter and Gap regions of the TBC cell.

[0031] In some specific embodiments, the anti-reflection film layer is a SiNx anti-reflection film, and the thickness of the front anti-reflection film is 75-85nm, the refractive index is 2.02-2.10, and the thickness of the back anti-reflection film is 70-80nm, the refractive index is 2.02-2.10. Specifically, the SiNx anti-reflection film is prepared on the front and back of the cell using the PECVD method.

[0032] In addition, the metal electrode uses a screen printing method to print metal grid lines on the metal area, and the metal grid lines correspond to the interdigitated passivation contact layer.

[0033] Preferably, the widths of the N+poly layer and the P+poly layer of the interdigitated passivation contact layer are both greater than or equal to the width of the metal gate line.

[0034] Furthermore, the metal grid lines corresponding to the N+poly layer form silver electrodes or aluminum electrodes; and the metal grid lines corresponding to the P+poly layer form silver electrodes.

[0035] Due to the implementation of the above technical solution, the present invention has the following advantages compared with the prior art:

[0036] The existing TBC battery preparation requires the use of mask technology, laser grooving, etching technology, etc., which makes the preparation process of the TBC battery interdigital structure very complicated; at the same time, two annealings are required during the preparation process, that is, preparation of P+poly→annealing→preparation of N+poly→annealing. Therefore, it is not only inefficient but also costly, etc. The present invention cleverly solves the various existing deficiencies by overall designing the preparation method of the TBC battery. After adopting the preparation method of the TBC battery, first, single crystal silicon is selected as the substrate and surface treatment is performed to form a velvet surface on the front side and a flat surface on the back side; then, a tunneling oxide layer is formed on the back side; then, a patterned mask is used in a designated area on the back side of the tunneling oxide layer, and an alternating and spaced N+poly layer and a P+poly layer are formed in adjacent plate-type cavities of the same device, and then the silicon wafer after the N+poly layer and the P+poly layer are deposited is put into an annealing furnace to complete boron-phosphorus co-annealing, so that the in-situ doped N+poly layer and the P+poly layer are crystallized, and the doping sources of the N+poly layer and the P+poly layer are activated to form the interdigitated passivation contact layer, and then the passivation layer is formed on the front side and the back side in sequence. and anti-reflection film layer; finally, the metal electrode. Therefore, on the one hand, the present invention adopts deposition technology combined with a graphic mask plate and superimposed in-situ doping, which can realize the preparation of the N+poly and P+poly finger regions of the core of the TBC battery in one process, and at the same time cooperates with the boron-phosphorus co-annealing technology, and only one annealing process is required to form the finger passivation contact layer, thereby greatly reducing the number of preparation steps of the TBC battery and reducing the production cost of the TBC battery; on the other hand, alternating and spaced N+poly layers and P+poly layers are formed in adjacent plate cavities of the same device to avoid molding interference between the two, thereby improving the preparation efficiency of the TBC battery, and effectively reducing the recombination of the metallized area of ​​the metal grid line, thereby improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the process of preparing the TBC battery of this embodiment;

[0038] Figure 2 This is a schematic diagram of step a) in step 1) of this embodiment;

[0039] Figure 3 This is a schematic diagram of step b) in step 1) of this embodiment;

[0040] Figure 4 This is a schematic diagram of the decomposition of step c) in step 1) of this embodiment;

[0041] Figure 5 This is a schematic diagram of step 2 in step 1) of c) of this embodiment;

[0042] Figure 6 This is a schematic diagram of step c) in step 1) of this embodiment;

[0043] Figure 7 This is a schematic diagram for decomposing step 2) and step 3) of this embodiment;

[0044] Figure 8 This is a schematic diagram of the decomposition of step 2) and step 3) of this embodiment;

[0045] Fig. 9 This is a schematic diagram of the decomposition of step 4) of this embodiment;

[0046] Fig.10 This is a schematic diagram of the decomposition of step 4) of this embodiment;

[0047] Fig.11 This is a schematic diagram of step 5) of this embodiment;

[0048] Among them: 1. substrate; 2. tunneling oxide layer; 3. N+poly layer; 4. P+poly layer; 5. interdigitated passivation contact layer; 6. passivation layer; 7. anti-reflection film layer; 8. metal electrode. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0050] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0052] In the present invention, unless otherwise clearly defined and specified, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In the invention, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0054] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0055] like Figures 1 to 11 As shown, the preparation method of the TBC battery involved in this embodiment includes the following steps: 1) selecting single crystal silicon as the substrate 1, and performing surface treatment so that the front side forms a velvet surface and the back side is a flat surface;

[0056] 2) forming a tunnel oxide layer 2 on the back side;

[0057] 3) forming an interdigitated passivation contact layer 5 of an N+poly layer 3 and a P+poly layer 4 on the back side of the tunnel oxide layer 2;

[0058] 4) forming a passivation layer 6 and an anti-reflection film layer 7 on the front and back sides in sequence;

[0059] 5) Metal electrodes 8 are formed.

[0060] The following is a specific implementation method to describe the steps as follows (combined with Figures 2 to 11 ):

[0061] 1) Select an N-type silicon wafer as substrate 1, and the thickness of the silicon wafer is 135um, and the resistivity is 1Ω·cm. First, perform a double-sided texturing process, and the texturing is thinned to 0.4g. At the same time, the front side is texturized by using PECVD to prepare an 80nm SiO2mask mask, and then use a 20% volume fraction HF solution to clean the side where the mask is not deposited (using a single-sided HF cleaning machine) to remove the SiO2mask plating, and then use an alkaline polishing method (trough machine) to polish the back of the silicon wafer, and finally use a 20% volume fraction HF solution to wash off the SiO2mask mask on the front to prepare a silicon wafer with a polished back and a texturized front, completing the decomposition steps a), b) and c);

[0062] 2) Using a three-chamber PVD device, the first chamber is used to thermally oxidize and grow a 1.5 nm tunneling oxide layer 2 on the polished surface, wherein the process temperature used in the thermal oxidation method is 500° C.-650° C., and O2 is introduced during the process for oxidation. The pressure in the first chamber is between 1-10 mBar, completing step 2);

[0063] 3) In the second cavity of the three-cavity PVD equipment, an in-situ doping PVD technology is used to superimpose a patterned mask plate, and a strip P+poly layer 4 is prepared in a local area on the back of the tunnel oxide layer 2. The third cavity uses an in-situ doping PVD technology to superimpose a patterned mask plate, and a strip N+poly layer 3 is prepared locally on the back of the tunnel oxide layer 2, wherein the P+poly layer 4 and the N+poly layer 3 are staggered, without an overlapping area, and there is a certain interval area between the two poly layers as a Gap area. Specifically, the P+poly layer 4 is a Poly layer in-situ doped with B atoms, the poly layer thickness is 100nm, and the doping amount is 1.5e 20 cm -3 , width 700um; N+poly layer 3 is a poly layer in-situ doped with phosphorus atoms, the poly layer thickness is 100nm, and the doping amount is 5e 20 cm -3 , the width is 250um; the width of the Gap area is 50um, and then the silicon wafer after the deposition of the N+poly layer 3 and the P+poly layer 4 is put into the annealing furnace to complete the boron-phosphorus co-annealing, the annealing temperature is 915±5℃, the annealing time is 40±10min, and the annealing is performed at normal pressure. During the annealing process, 15slm nitrogen is introduced as a protective gas to crystallize the in-situ doped N+poly layer 3 and the P+poly layer 4. After annealing, the square resistance of the N+poly layer 3 is 45Ω / sq, and the square resistance of the P+poly layer 4 is 220Ω / sq, and the doping sources of the N+poly layer 3 and the P+poly layer 4 are activated to form an interdigitated passivation contact layer 5. Finally, a HF solution with a volume fraction of 10% is used for cleaning, and the cleaning time is 3min to remove the natural oxide layer on the surface of the silicon wafer and the tunnel oxide layer in the gap area, and complete step 3);

[0064] 4) ALD is used to deposit an AL2O3 passivation layer 6 on the front and back sides, the process is carried out for 32 cycles, the film thickness is 3.5nm, and the step is completed; then a SiNx anti-reflection film 7 is deposited on the front and back sides by PECVD, the front anti-reflection film thickness is 80nm, the refractive index is 2.05, and the back anti-reflection film thickness is 75nm, the refractive index is 2.05, and step 4 is completed;

[0065] 5) Use screen printing technology to print metallized grid lines on the battery to form metal electrodes 8, wherein the metal electrodes 8 use the screen printing method to print metal grid lines in the metal area, and the metal grid lines correspond to the interdigitated passivation contact layers, and the widths of the N+poly layer 3 and the P+poly layer 4 of the interdigitated passivation contact 5 layers are both greater than the width of the metal grid lines, and the metal grid lines corresponding to the N+poly layer 3 form silver electrodes or aluminum electrodes; the metal grid lines corresponding to the P+poly layer 4 form silver electrodes, and step 5) is completed, and the TBC battery preparation is completed.

[0066] Performance test: The battery obtained in the above embodiment was subjected to the following performance test, and the test method was: using an IV tester to test the battery photoelectric conversion efficiency and related electrical performance parameters under standard light power under simulated solar light source (and the electrical performance data is the average value data of 100Pcs batteries of various samples). Specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor; Rs: series resistance).

[0067] Table 1

[0068]

[0069] As can be seen from Table 1, the passivation contact structure of the TBC battery will passivate all the metal contact areas of the battery, so this type of battery has a lower recombination and can effectively increase its open circuit voltage (Voc). And because there is no grid line blocking the front of the TBC battery, a higher short-circuit current density (Jsc) can be obtained.

[0070] In summary, after adopting the preparation method of the TBC battery, first, single crystal silicon is selected as the substrate, and the surface is treated so that the front side forms a velvet surface and the back side is a plane; then, a tunneling oxide layer is formed on the back side; then, a patterned mask is used in the designated area on the back side of the tunneling oxide layer, and an alternating and spaced N+poly layer and a P+poly layer are formed in adjacent plate-type cavities of the same device, and then the silicon wafer after the deposition of the N+poly layer and the P+poly layer is put into an annealing furnace to complete boron-phosphorus co-annealing, so that the in-situ doped N+poly layer and the P+poly layer are crystallized, and the doping sources of the N+poly layer and the P+poly layer are activated to form the interdigitated passivation contact layer, and then the passivation layer and the anti-reflection film layer are formed on the front and back sides in sequence; finally, a metal electrode is formed. Therefore, the present invention is a On the one hand, the deposition technology combined with the graphic mask plate and superimposed in-situ doping can realize the preparation of the N+poly and P+poly finger areas of the core of the TBC battery in one process. At the same time, with the boron-phosphorus co-annealing technology, only one annealing process is needed to form the finger passivation contact layer, which greatly reduces the number of preparation steps of the TBC battery and reduces the production cost of the TBC battery. On the other hand, alternating and spaced N+poly layers and P+poly layers are formed in adjacent plate cavities of the same equipment to avoid molding interference between the two, thereby improving the preparation efficiency of the TBC battery and effectively reducing the recombination of the metallized area of ​​the metal grid line, thereby improving the battery efficiency. Thirdly, the front side of the TBC battery itself is unobstructed, which can effectively increase the light-receiving area of ​​the battery, increase the battery Jsc, and improve the battery conversion rate.

[0071] The above detailed description of the present invention is intended to enable persons familiar with the art to understand the contents of the present invention and implement them. It does not limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a TBC battery, comprising the following steps: 1) Selecting single crystal silicon as the substrate and performing surface treatment so that the front side forms a velvet surface and the back side is a flat surface; 2) Formation of a tunnel oxide layer on the back side; 3) forming an interdigitated passivation contact layer of an N+poly layer and a P+poly layer on the back side of the tunnel oxide layer; 4) Forming a passivation layer and an anti-reflection film layer on the front and back sides in sequence; 5) Forming a metal electrode, characterized in that: In step 3), first, a patterned mask plate is used in the designated area on the back side of the tunnel oxide layer, and alternating and spaced N+poly layers and P+poly layers are formed in adjacent plate-type cavities of the same device; secondly, the silicon wafer after the deposition of the N+poly layer and the P+poly layer is placed in an annealing furnace to complete boron-phosphorus co-annealing, so that the in-situ doped N+poly layer and the P+poly layer are crystallized, and the doping sources of the N+poly layer and the P+poly layer are activated to form the interdigitated passivation contact layer.

2. The method for preparing a TBC battery according to claim 1, characterized in that: Step 2) and step 3) are performed in the same device, and the device has three plate-type chambers connected in series.

3. The method for preparing a TBC battery according to claim 2, characterized in that: The cavity is divided into a first cavity, a second cavity and a third cavity. The first cavity uses a thermal oxidation method to prepare a tunneling oxide layer on the back of a substrate; the second cavity and the third cavity both use a PVD method in conjunction with a patterned mask plate, and the mask plate is located between a PVD sputtering source and a silicon wafer, so that the PVD sputtering area is presented in a patterned manner, and combined with an in-situ doping process, a patterned N+poly layer and a P+poly layer are deposited in a specific area.

4. The method for preparing a TBC battery according to claim 3, characterized in that: The process temperature used in the thermal oxidation method is 500° C.-650° C., and O2 is introduced during the process for oxidation. The pressure in the first cavity is between 1-10 mBar, and / or the thickness of the prepared tunneling oxide layer is 1.4-2.0 nm.

5. The method for preparing a TBC battery according to claim 1, characterized in that: The annealing temperature is controlled between 895°C and 935°C, and the high temperature annealing time is 20-120min; and / or, the annealing temperature required for the P+poly layer is the same as the annealing temperature required for the N+poly layer, and the annealing of the two POLY layers is completed at one time.

6. The method for preparing a TBC battery according to claim 1, characterized in that: The annealing process is carried out in a high-temperature furnace tube, and N2 is introduced as a protective gas during the annealing process; and / or, after annealing, the square resistance of the P+poly region is controlled to be 120-300Ω / sq, and the square resistance of the N+poly region is controlled to be 30-60Ω / sq.

7. The method for preparing a TBC battery according to claim 1, characterized in that: After annealing, the silicon wafer is cleaned with a mixed solution of HF / HCL to remove the natural oxide layer on the surface of the silicon wafer and the tunnel oxide layer in the gap area.

8. The method for preparing a TBC battery according to claim 7, characterized in that: The volume ratio of HF:HCL:H2O is 1:1:4-4:1:4, and the cleaning time is 2-5min.

9. The method for preparing a TBC battery according to claim 1, characterized in that: The substrate is an N-type silicon wafer; and / or the thickness of the silicon wafer is 100-200 um; and / or the resistivity of the silicon wafer is 0.5-7 Ω·cm.

10. The method for preparing a TBC battery according to claim 1, characterized in that: The surface treatment in step 1) includes the following steps: a) performing double-sided texturing on the silicon wafer to form a double-sided texturing silicon wafer; b) forming a Mask layer on the front side of the silicon wafer after texturing; c) acid washing and alkaline polishing are performed on the back side of the silicon wafer to form a flat surface, wherein the Mask layer is a SiNx layer or a SiO2 layer prepared by PECVD; and / or the thickness of the Mask layer is 30-150nm.

11. The method for preparing a TBC battery according to claim 10, characterized in that: The Mask layer is a SiO2 layer, and the thickness of the Mask layer is 40-80nm; and / or, in step b), the Mask layer is formed on two opposite sides of the back side of the silicon wafer by wrap-around plating; in step c), the back side is cleaned with HF, wherein an HF solution with a volume fraction exceeding 20% ​​is used for cleaning to remove the back side wrap-around plating.

12. The method for preparing a TBC battery according to claim 1, characterized in that: The passivation layer is an aluminum oxide film layer; and / or, the thickness of the passivation layer is 2-10nm; and / or, the anti-reflection film layer is a SiNx anti-reflection film, and the thickness of the front anti-reflection film is 75-85nm, the refractive index is 2.02-2.10, and the thickness of the back anti-reflection film is 70-80nm, and the refractive index is 2.02-2.

10.

13. The method for preparing a TBC battery according to claim 1, characterized in that: The metal electrode uses a screen printing method to print metal grid lines on the metal area, and the metal grid lines correspond to and match the interdigitated passivation contact layer.

14. The method for preparing a TBC battery according to claim 13, characterized in that: The widths of the N+poly layer and the P+poly layer of the interdigitated passivation contact layer are both greater than or equal to the width of the metal gate line; and / or, the metal gate line corresponding to the N+poly layer forms a silver electrode or an aluminum electrode; the metal gate line corresponding to the P+poly layer forms a silver electrode.

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