Structure for improving DMOS resistance

Abstract

The invention provides a structure for improving DMOS resistance, which comprises a substrate, a drift region of a first conductive type is formed on the substrate, and a body region of a second conductive type is formed on the upper surface of the drift region; the substrate comprises a substrate lead-out region and a trench gate device region, deep trenches are formed in the substrate lead-out region and the trench gate device region, and gate dielectric layers are formed on the deep trenches and the substrate; a protruding metal layer higher than the substrate is formed in each deep trench; a source region formed on the body region in the trench device region; the interlayer dielectric layer covers the metal layer, the portion, above the protruding metal layer, of the interlayer dielectric layer in the substrate leading-out region is opened to serve as a first contact hole, and the portion, on the source region, of the gate dielectric layer and the interlayer dielectric layer are opened to serve as a second contact hole; the first interconnection structure is used for leading out the first contact hole; and the second interconnection structure is used for leading out the second contact hole. According to the invention, the resistance of the DMOS can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a structure for improving DMOS resistance. Background Art

[0002] DMOS process: DMOS (double diffused MOS) transistors are optimized for high current and high voltage. They are designed with a long channel structure to increase the breakdown voltage. Several units are connected in parallel to achieve high current (low on-resistance) and high energy density. The DMOS process has a thicker gate oxide layer than the logic process, which can produce a more robust device.

[0003] The DMOS device in the prior art usually uses polysilicon as the gate, and has a relatively large resistance.

[0004] In order to solve the above problems, it is necessary to propose a new structure for improving DMOS resistance. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a structure for improving DMOS resistance, so as to solve the problem of large resistance of DMOS devices in the prior art.

[0006] To achieve the above objectives and other related objectives, the present invention provides a structure for improving DMOS resistance, comprising:

[0007] A substrate, on which a drift region of a first conductivity type is formed, and on an upper surface of the drift region a body region of a second conductivity type is formed;

[0008] The substrate comprises a substrate lead-out region and a trench gate device region, deep trenches are formed on the substrate lead-out region and the trench gate device region, and a gate dielectric layer is formed on the deep trench and the substrate;

[0009] A protruding metal layer having a uniform height and a height exceeding that of the substrate is formed in each of the deep trenches;

[0010] a source region formed on the body region in the trench device region;

[0011] an interlayer dielectric layer covering the metal layer, wherein the interlayer dielectric layer above the protruding metal layer in the substrate lead-out region is opened as a first contact hole, and the gate dielectric layer and the interlayer dielectric layer on the source region are opened as a second contact hole;

[0012] A first interconnection structure for leading out the first contact hole and a second interconnection structure for leading out the second contact hole.

[0013] Preferably, the material of the gate dielectric layer is silicon dioxide.

[0014] Preferably, the material of the protruding metal layer is tungsten.

[0015] Preferably, the first and second interconnect structures include conductive components.

[0016] Preferably, a drain structure is also formed on the back side of the substrate.

[0017] As described above, the structure of improving the DMOS resistor of the present invention has the following beneficial effects:

[0018] The present invention can improve the resistance of DMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram showing the structure of the improved DMOS resistor of the present invention. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] See also Figure 1 The present invention provides a structure for improving DMOS resistance, comprising:

[0022] A substrate 301 , on which a drift region 302 of a first conductivity type is formed, and on an upper surface of the drift region 302 , a body region 303 of a second conductivity type is formed;

[0023] In some embodiments, substrate 301 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0024] The substrate 301 includes a substrate lead-out region and a trench gate device region, deep trenches are formed on the substrate lead-out region and the trench gate device region, and a gate dielectric layer 304 is formed on the deep trench and the substrate 301;

[0025] In some embodiments, the material of the gate dielectric layer 304 is silicon dioxide.

[0026] A protruding metal layer 305 with a uniform height and a height exceeding the substrate 301 is formed in each deep trench. The height of the protruding metal layer 305 exceeds the substrate, which can eliminate the difference in device threshold voltage caused by the difference in gate height between different trenches and the difference in parasitic capacitance between the gate and the source, thereby improving the uniformity of the device threshold voltage and the gate-source parasitic capacitance in the chip and the uniformity in the entire silicon wafer;

[0027] In some embodiments, the material of the protruding metal layer 305 is tungsten. In other embodiments, the protruding metal layer 305 can also be replaced with other metal materials that can improve resistance.

[0028] A source region 306 formed on the body region 303 in the trench device region;

[0029] An interlayer dielectric layer 307 covering the metal layer 305, wherein the interlayer dielectric layer 307 above the protruding metal layer 305 in the lead-out region of the substrate 301 is opened as a first contact hole, and the gate dielectric layer and the interlayer dielectric layer 307 on the source region 306 are opened as a second contact hole;

[0030] A first interconnect structure 308 for leading out a first contact hole and a second interconnect structure 309 for leading out a second contact hole.

[0031] In some embodiments, the first and second interconnect structures include conductive components. The interconnect structure also includes other interlayer dielectric (ILD) layers to separate and isolate various conductive components. For example, the interconnect structure includes contacts for leading out the first and second contact holes; metal lines; and through holes. The metal lines are distributed in multiple metal layers. The contacts provide vertical electrical wiring from the semiconductor substrate 301 to the metal lines. The through holes provide vertical electrical wiring between adjacent metal layers. Various conductive components are formed by one or more conductive materials such as metals, metal alloys or silicides. For example, the metal lines may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The through holes may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The contacts may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some instances, the various conductive components may further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride.

[0032] The ILD layer includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The ILD layer includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials or combinations thereof. In some instances, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the ILD layer includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques or combinations thereof.

[0033] In some embodiments, a drain structure is further formed on the back side of the substrate 301 , which includes ion implantation on the back side of the substrate 301 and a metal drain formed on the back side of the substrate 301 .

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] In summary, the present invention can improve the resistance of DMOS. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A structure for improving DMOS resistance, characterized in that: include: A substrate, on which a drift region of a first conductivity type is formed, and on an upper surface of the drift region a body region of a second conductivity type is formed; The substrate comprises a substrate lead-out region and a trench gate device region, deep trenches are formed on the substrate lead-out region and the trench gate device region, and a gate dielectric layer is formed on the deep trench and the substrate; A protruding metal layer having a uniform height and a height exceeding that of the substrate is formed in each of the deep trenches; a source region formed on the body region in the trench device region; an interlayer dielectric layer covering the metal layer, wherein the interlayer dielectric layer above the protruding metal layer in the substrate lead-out region is opened as a first contact hole, and the gate dielectric layer and the interlayer dielectric layer on the source region are opened as a second contact hole; A first interconnection structure for leading out the first contact hole and a second interconnection structure for leading out the second contact hole.

2. The structure for improving DMOS resistance according to claim 1, characterized in that: The material of the gate dielectric layer is silicon dioxide.

3. The structure for improving DMOS resistance according to claim 1, characterized in that: The material of the protruding metal layer is tungsten.

4. The structure for improving DMOS resistance according to claim 1, characterized in that: The first and second interconnect structures include conductive components.

5. The structure for improving DMOS resistance according to claim 1, characterized in that: A drain structure is also formed on the back side of the substrate.

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