Semiconductor structure, semiconductor chip, packaging structure and corresponding forming methods

Abstract

A semiconductor structure, a semiconductor chip, a package structure and respective corresponding forming methods wherein the semiconductor structure comprises: a substrate having a first surface, the substrate comprising a plurality of chip regions, each chip region having a groove recessed relative to the first surface; the first chip is located in the groove, and the first surface exposes a functional surface of the first chip; the rewiring layer is located on the surface of the first surface and the surface of the functional surface of the first chip, and a conductive structure is arranged in the rewiring layer; the second chips are located on the surfaces of the rewiring layers on the chip areas, the second chips are electrically connected with the first chips through conductive structures, and the projections, facing the surface of the substrate, of the first chips partially coincide with the projections, facing the surface of the substrate, of the second chips; and the conductive columns are located on the surfaces of the rewiring layers on the chip areas and are electrically connected with the first chips through conductive structures, so that the performance of the finally formed packaging structure can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure, a semiconductor chip, a packaging structure and corresponding forming methods. Background Art

[0002] With the continuous development of integrated circuit technology, electronic products are increasingly moving towards miniaturization, intelligence, high performance and high reliability. Integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules and even the entire machine, but also restricts the miniaturization, low cost and reliability of the entire electronic system. As the size of integrated circuit lenses gradually decreases and the integration level continues to increase, the electronics industry has put forward higher and higher requirements for integrated circuit packaging technology.

[0003] The first is the most common wire-bonding package in traditional packaging, that is, the chip is fixed on the substrate with the front side facing up, and then the metal pins of the chip (die) are connected to the pads of the substrate by bonding wires (usually very thin gold wires), and finally the package is sealed. Obviously, the size of this package will be much larger than the original die size, and the cost is not low, which can no longer meet the needs of increasingly smaller smart devices.

[0004] However, the existing packaging performance still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure, a semiconductor chip, a packaging structure and corresponding formation methods, which can effectively improve the performance of the finally formed packaging structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate, the substrate having a first surface, the substrate including a plurality of chip areas, each chip area having a groove recessed relative to the first surface; a first chip located in the groove, and the first surface exposes the functional surface of the first chip; a redistribution layer located on the surface of the first surface and the surface of the functional surface of the first chip, the redistribution layer having a conductive structure; a second chip located on the surface of the redistribution layer on each chip area, the second chip being electrically connected to the first chip through the conductive structure, the projection of the first chip toward the substrate surface partially overlapping with the projection of the second chip toward the substrate surface; a conductive column located on the surface of the redistribution layer on each chip area, the conductive column being electrically connected to the first chip through the conductive structure.

[0007] Optionally, it further includes: a plastic packaging layer located on the surface of the redistribution layer, the second chip and the conductive pillars are located in the plastic packaging layer, and the plastic packaging layer exposes the surface of the second chip.

[0008] Optionally, the function of the first chip is different from the function of the second chip.

[0009] Optionally, the first chip includes a logic chip, and the second chip includes a memory chip.

[0010] Optionally, the redistribution layer includes an insulating layer located on the surface of the first surface and the surface of the functional surface of the first chip, and the conductive structure is located in the insulating layer.

[0011] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a first surface, and the substrate including a plurality of chip areas; etching a partial thickness of the substrate in each chip area to form a groove in the chip area that is recessed relative to the first surface; placing a first chip in the groove, and the first surface exposes the functional surface of the first chip; forming a redistribution layer on the surface of the first surface and the surface of the functional surface of the first chip, the redistribution layer having a conductive structure; connecting a second chip on the surface of the redistribution layer in each chip area, the second chip being electrically connected to the first chip through the conductive structure, and the projection of the first chip toward the substrate surface partially overlaps with the projection of the second chip toward the substrate surface; forming a conductive column on the surface of the redistribution layer on each chip area, the conductive column being electrically connected to the first chip through the conductive structure.

[0012] The present invention also provides a semiconductor chip, comprising: a substrate unit, the substrate unit having a first surface, the substrate unit having a groove recessed relative to the first surface; a first chip located in the groove, and the first surface exposes the functional surface of the first chip; a redistribution layer located on the surface of the first surface and the surface of the functional surface of the first chip, the redistribution layer having a conductive structure; a second chip located on the surface of the redistribution layer, the second chip being electrically connected to the first chip through the conductive structure, the projection of the first chip toward the substrate surface partially overlapping with the projection of the second chip toward the substrate surface; and a conductive column located on the surface of the redistribution layer on the chip area, the conductive column being electrically connected to the first chip through the conductive structure.

[0013] Optionally, the function of the first chip is different from the function of the second chip.

[0014] Optionally, the first chip includes a logic chip, and the second chip includes a memory chip.

[0015] Optionally, the redistribution layer includes an insulating layer located on the surface of the first surface and the surface of the functional surface of the first chip, and the conductive structure is located in the insulating layer.

[0016] Optionally, a plastic encapsulation layer is included on the surface of the redistribution layer, the plastic encapsulation layer encapsulates the second chip and the conductive pillars, and the plastic encapsulation layer exposes the surface of the second chip and the surface of the conductive pillars.

[0017] Correspondingly, the present invention also provides a method for forming a semiconductor chip, comprising: providing a substrate, the substrate having a first surface, and the substrate including a plurality of chip areas; etching a partial thickness of the substrate in each chip area to form a groove in the chip area that is recessed relative to the first surface; placing a first chip in the groove, and the first surface exposes the functional surface of the first chip; forming a redistribution layer on the surface of the first surface and the surface of the functional surface of the first chip, the redistribution layer having a conductive structure; connecting a second chip on the surface of the redistribution layer in each chip area, the second chip being electrically connected to the first chip through the conductive structure, and the projection of the first chip toward the substrate surface partially overlaps with the projection of the second chip toward the substrate surface; forming a conductive column on the surface of the redistribution layer on each chip area, the conductive column being electrically connected to the first chip through the conductive structure; after forming the conductive column, cutting the substrate between the chip areas to separate the chip areas from each other to form a plurality of independent semiconductor chips.

[0018] The present invention also provides a packaging method, including the above-mentioned semiconductor chip; providing a wiring substrate; aligning the semiconductor chip and the wiring substrate; welding the aligned semiconductor chip and the wiring substrate to electrically connect the semiconductor chip and the wiring substrate; performing bottom filling between the welded semiconductor chip and the wiring substrate to form an adhesive layer between the semiconductor chip and the wiring substrate.

[0019] Optionally, after forming the adhesive layer, the method further includes forming metal balls on the wiring substrate, wherein the metal balls and the semiconductor chip are located on both sides of the wiring substrate.

[0020] Correspondingly, the present invention also provides a packaging structure, comprising: the above-mentioned semiconductor chip, the semiconductor chip having a conductive protrusion connected to the conductive column; a wiring substrate; and an adhesive layer located between the semiconductor chip and the wiring substrate.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the scheme of the semiconductor structure of the present invention, the substrate includes a plurality of chip areas, each chip area has a groove recessed relative to the first surface, after the first chip is embedded in the substrate through the groove, a redistribution layer is formed on the functional surface of the first chip, the redistribution layer has a conductive structure, the second chip is located on the surface of the redistribution layer on each chip area, the second chip is electrically connected to the first chip through the conductive structure, the first chip and the second chip have a partial overlap in their projections toward the substrate, the conductive column is located on the surface of the redistribution layer, the conductive column is electrically connected to the first chip through the conductive structure, on the one hand, this semiconductor structure embeds the first chip into the chip area of ​​the substrate, and then forms a redistribution layer on the functional surface of the first chip, because the first chip is embedded in the substrate, this ensures that the surface for forming the redistribution layer is smoother, and the pitch of the redistribution layer can be achieved to less than 1 micron, which ensures that the quality of the dielectric layer that can be formed is better, thereby helping to form a redistribution layer with high quality and smaller pitch, and having a wider range of applications; on the other hand, the projections of the first chip and the second chip partially overlap, and the transmission distance between the first chip and the second chip is short, which can more easily adapt to high-frequency transmission and expand the scope of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a packaging structure;

[0024] Figures 2 to 8 is a schematic structural diagram of a formation process of a semiconductor structure in one embodiment of the present invention;

[0025] Fig. 9 is a schematic structural diagram of a semiconductor chip in one embodiment of the present invention;

[0026] Fig.10 FIG. 4 is a schematic diagram of a packaging structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As the background technology, the performance of the packaging structure in the prior art still needs to be improved.

[0028] Please refer to Figure 1A packaging structure, a wiring substrate 111 includes a first surface 111a and a second surface 111b opposite to each other; a metal ball 112 located on the second surface 111b; a conductive protrusion 113 located on the first surface 111; a first redistribution layer 101 located on the conductive protrusion 113, a filling glue 114 between the first redistribution layer 101 and the first surface 111a, and two separate bridge chips (bridge chips) located on the first redistribution layer 101 The present invention relates to a bridge chip 102, a plurality of conductive pillars 103 arranged discretely on the first redistribution layer 101, a first plastic layer 104 on the first redistribution layer 101, wherein the first plastic layer 104 plasticizes the bridge chip 102 and the conductive pillars 103 and exposes the top surface of the bridge chip 102 and the conductive pillars 103; a second redistribution layer 105 on the plastic layer 104, a bonding wire 106 (pad) on the second redistribution layer 105, a first chip 107 and a second chip 108 discretely located on the bonding wire 106, wherein the first chip 107 is connected to a bridge chip 102 through the bonding wire 106 and the second redistribution layer 105. 102 is electrically connected, and the second chip 108 is electrically connected to another bridge chip 102 through the welding wire 106 and the second redistribution layer 105; the dielectric layer 109 is located on the second redistribution layer 105, and the dielectric layer 109 is located between the first chip 107 and the second chip 108; the second plastic sealing layer 110 is located on the second redistribution layer 105, and the second plastic sealing layer 110 plastic seals the first chip 107, the second chip 108, the dielectric layer 109, the welding wire 106, etc. on the second redistribution layer 105, and the second plastic sealing layer 110 exposes the surfaces of the first chip 107, the second chip 108 and the dielectric layer 109.

[0029] The inventors have discovered that in this packaging structure, information is transmitted between the first chip 107 and the second chip 108 through the bridge chip 102. On the one hand, the transmission distance between the first chip 107 and the second chip 108 is far, which is not conducive to high-frequency transmission; on the other hand, there are slight differences in the heights of the first plastic packaging layer 104, the bridge chip 102 and the conductive column 103, resulting in poor flatness of the plane formed by the first plastic packaging layer 104, the bridge chip 102 and the conductive column 103. As a result, the pitch of the second redistribution layer 105 formed is not easy to be made small, which is not conducive to improving the accuracy and performance of the packaging structure.

[0030] On this basis, the present invention provides a semiconductor structure, a semiconductor chip, a packaging structure and corresponding formation methods. The substrate includes a plurality of chip areas, each chip area has a groove recessed relative to the first surface. After the first chip is embedded in the substrate through the groove, a redistribution layer is formed on the functional surface of the first chip. The redistribution layer has a conductive structure. The second chip is located on the surface of the redistribution layer on each chip area. The second chip is electrically connected to the first chip through the conductive structure. The first chip and the second chip partially overlap in projection toward the substrate. The conductive column is located on the surface of the redistribution layer. The conductive column is electrically connected to the first chip through the conductive structure. On the one hand, this semiconductor structure embeds the first chip into the chip area of ​​the substrate and then forms a redistribution layer on the functional surface of the first chip. Since the first chip is embedded in the substrate, the surface for forming the redistribution layer is more flat, and the pitch of the redistribution layer can be achieved to less than 1 micron, which ensures that the quality of the dielectric layer that can be formed is better, thereby helping to form a redistribution layer with high quality and smaller pitch, and having a wider range of applications; on the other hand, the projections of the first chip and the second chip partially overlap, and the transmission distance between the first chip and the second chip is short, which can more easily adapt to high-frequency transmission and expand the scope of use.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 2 to 8 is a schematic structural diagram of a formation process of a semiconductor structure in one embodiment of the present invention; Fig. 9 is a schematic structural diagram of a semiconductor chip in one embodiment of the present invention; Fig.10 FIG. 4 is a schematic diagram of a packaging structure in an embodiment of the present invention.

[0033] First, please refer to Figure 2 , providing a substrate 200.

[0034] In this embodiment, the substrate 200 has a first surface 200 a , and the substrate 200 includes a plurality of chip regions I.

[0035] In this embodiment, only two chip regions I are shown on the substrate 200 .

[0036] In other embodiments, the number of chip regions I is designed according to actual process requirements.

[0037] In this embodiment, the material of the substrate 200 is silicon.

[0038] In other embodiments, the material of the substrate 200 may also be some semiconductor materials such as silicon germanium, germanium, etc.

[0039] In this embodiment, the material of the substrate 200 can be conventional and cheap semiconductor materials, which can improve the performance of the final semiconductor structure while reducing costs, thereby helping to expand the scope of application.

[0040] Please refer to Figure 3 , etching a portion of the thickness of the substrate 200 in each chip region I, forming a groove 201 in the chip region I that is recessed relative to the first surface 200a.

[0041] In this embodiment, the etching process for forming the groove 201 is a wet etching process.

[0042] In other embodiments, the etching process for forming the groove 201 may also be a dry etching process or the like.

[0043] In this embodiment, the purpose of forming the groove 201 is to provide space for the subsequent installation of the first chip.

[0044] Please refer to Figure 4 , a first chip 202 is placed in the groove 201 , and the first surface 200 a exposes a functional surface of the first chip 202 .

[0045] In this embodiment, after the first chip 202 is placed in the groove 201 , the first chip 202 and the groove 201 are fixed by using glue.

[0046] In this embodiment, the functional surface of the first chip 202 is flush with the first surface 200 a .

[0047] In this embodiment, the functional surface of the first chip 202 further has a plurality of conductive protrusions for subsequent connection with the conductive structure to achieve connection between the first chip 202 and the outside.

[0048] In this embodiment, the first chip 202 includes a logic chip.

[0049] Please refer to Figure 5 A redistribution layer 203 is formed on the surface of the first surface 200 a and the functional surface of the first chip 202 , and the redistribution layer 203 has a conductive structure 203 a .

[0050] In this embodiment, the redistribution layer 203 includes an insulating layer 203b located on the surface of the first surface 200a and the functional surface of the first chip 202, the conductive structure 203a is located in the insulating layer 203b, and the top surface of the insulating layer 203b exposes the top surface of the conductive structure 203a.

[0051] In this embodiment, the first chip 202 is embedded in the chip area I of the substrate 200, and then a redistribution layer 203 is formed on the functional surface of the first chip 202. Since the first chip 202 is embedded in the substrate 200, the surface for forming the redistribution layer 203 is guaranteed to be smoother, and the pitch of the redistribution layer 203 can be achieved to be less than 1 micron, which ensures that the quality of the dielectric layer that can be formed is better, thereby facilitating the formation of a high-quality and smaller-pitch redistribution layer 203, which has a wider range of applications.

[0052] Please refer to Figure 6 A second chip 204 is connected to the surface of the redistribution layer 203 of each chip area I, and the second chip 204 is electrically connected to the first chip 202 through the conductive structure 203a. The projection of the first chip 202 toward the surface of the substrate 200 partially overlaps with the projection of the second chip 204 toward the surface of the substrate 200.

[0053] In this embodiment, the function of the first chip 202 is different from the function of the second chip 204 .

[0054] In this embodiment, the second chip 204 includes a memory chip (HBM).

[0055] In this embodiment, the projections of the first chip 202 and the second chip 204 partially overlap, and the transmission distance between the first chip 202 and the second chip 204 is short, which can more easily adapt to high-frequency transmission and expand the scope of use.

[0056] Please refer to Figure 7 A conductive column 205 is formed on the surface of the redistribution layer 203 on each chip region I, and the conductive column 205 is electrically connected to the first chip 202 through the conductive structure 203a.

[0057] In this embodiment, the material of the conductive pillar 205 is copper.

[0058] In other embodiments, the conductive pillar 205 may be made of other conductive metal materials.

[0059] In this embodiment, the projection of the conductive pillars 205 on each chip region I toward the redistribution layer 203 does not overlap with the projection of the second chip 204 toward the redistribution layer 203 .

[0060] In this embodiment, the top surface of the conductive pillar 205 is flush with the top surface of the second chip 204 .

[0061] Please refer to Figure 8 A plastic encapsulation layer 206 is formed on the surface of the redistribution layer 203 , the second chip 204 and the conductive pillars 205 are located in the plastic encapsulation layer 206 , and the plastic encapsulation layer 206 exposes the surface of the second chip 204 .

[0062] In this embodiment, the step of forming the plastic encapsulation layer 206 includes forming an initial plastic encapsulation layer 206 on the surface of the redistribution layer 203 , and planarizing the initial plastic encapsulation layer 206 until the top surface of the second chip 204 and the conductive pillars 205 are exposed.

[0063] Accordingly, please refer to Figure 8 The present invention further provides a semiconductor structure, including a substrate 200, the substrate 200 having a first surface 200a, the substrate 200 including a plurality of chip areas I, each chip area I having a groove 201 recessed relative to the first surface 200a; a first chip 202 located in the groove 201, and the first surface 200a exposes the functional surface of the first chip 202; a redistribution layer 203 located on the surface of the first surface 200a and the surface of the functional surface of the first chip 202, the redistribution layer 203 having a conductive structure 203a; a second chip 204 located on the surface of the redistribution layer 203 on each chip area I, the second chip 204 being electrically connected to the first chip 202 through the conductive structure 203a, and the projection of the first chip 202 toward the surface of the substrate 200 partially overlaps with the projection of the second chip 204 toward the surface of the substrate 200; a conductive column 205 located on the surface of the redistribution layer 203 on each chip area I, the conductive column 205 being electrically connected to the first chip 202 through the conductive structure 203a.

[0064] In this embodiment, after the first chip 202 is embedded into the substrate 200 through the groove 201, a redistribution layer 203 is formed on the functional surface of the first chip 202, and the redistribution layer 203 has a conductive structure 203a. The second chip 204 is located on the surface of the redistribution layer 203 on each chip area I, and the second chip 204 is electrically connected to the first chip 202 through the conductive structure 203a. The first chip 202 and the second chip 204 partially overlap in their projections toward the substrate 200. The conductive column 205 is located on the surface of the redistribution layer 203, and the conductive column 205 is electrically connected to the first chip 202 through the conductive structure 203a. On the one hand, this semiconductor structure embeds the first chip 202 In the process of forming a redistribution layer 203 on the functional surface of the first chip 202, since the first chip is embedded in the substrate 200, the surface for forming the redistribution layer 203 is guaranteed to be smoother, and the pitch of the redistribution layer 203 can be achieved to be less than 1 micron, thereby ensuring that the quality of the dielectric layer that can be formed is better, thereby helping to form a redistribution layer 203 with high quality and smaller pitch, which has a wider range of applications; on the other hand, the projections of the first chip 202 and the second chip 204 partially overlap, and the transmission distance between the first chip 202 and the second chip 204 is short, which can more easily adapt to high-frequency transmission and expand the scope of use.

[0065] In this embodiment, the projection of the conductive pillars 205 on each chip region I toward the redistribution layer 203 does not overlap with the projection of the second chip 204 toward the redistribution layer 203 .

[0066] In this embodiment, the top surface of the conductive pillar 205 is flush with the top surface of the second chip 204 .

[0067] In this embodiment, it further includes: a plastic encapsulation layer 206 located on the surface of the redistribution layer 203 , the second chip 204 and the conductive pillars 205 are located in the plastic encapsulation layer 206 , and the plastic encapsulation layer 206 exposes the surface of the second chip 204 .

[0068] In this embodiment, the function of the first chip 202 is different from the function of the second chip 204 .

[0069] In this embodiment, the first chip 202 includes a logic chip, and the second chip 204 includes a memory chip.

[0070] In this embodiment, the redistribution layer 203 includes an insulating layer 203 b located on the surface of the first surface 200 a and the surface of the functional surface of the first chip 202 , and the conductive structure 203 a is located in the insulating layer 203 b .

[0071] Accordingly, the present invention also provides a method for forming a semiconductor chip. The process from providing a substrate 200 to forming a plastic encapsulation layer 206 is the same as the process for forming a semiconductor structure. For details, please refer to Figures 2 to 8 .

[0072] Please refer to Fig. 9 After the semiconductor structure is formed, the substrate 200 between the chip regions I is cut to separate the chip regions I from each other to form a plurality of independent semiconductor chips 300.

[0073] The semiconductor chip 300 includes a substrate unit 200, the substrate unit 200 has a first surface 200a, and the substrate unit 200 has a groove 201 that is recessed relative to the first surface 200a; a first chip 202 located in the groove 201, and the first surface 200a exposes the functional surface of the first chip 202; a redistribution layer 203 located on the surface of the first surface 200a and the surface of the functional surface of the first chip 202, and the redistribution layer 203 has a conductive structure 203a; a second chip 204 located on the surface of the redistribution layer 203, and the second chip 204 is connected to the substrate unit 200 through the substrate unit 200; The conductive structure 203a is electrically connected to the first chip 202, and the projection of the first chip 202 toward the surface of the substrate 200 partially overlaps with the projection of the second chip 204 toward the surface of the substrate 200; the conductive column 205 is located on the surface of the redistribution layer 203 on the chip area I, and the conductive column 205 is electrically connected to the first chip 202 through the conductive structure 203a; the plastic encapsulation layer 206 is located on the surface of the redistribution layer 203, and the plastic encapsulation layer 206 encapsulates the second chip 204 and the conductive column 205, and the plastic encapsulation layer 206 exposes the surface of the second chip 204 and the surface of the conductive column 205.

[0074] In this embodiment, the projection of the conductive pillars 205 on each chip region I toward the redistribution layer 203 does not overlap with the projection of the second chip 204 toward the redistribution layer 203 .

[0075] In this embodiment, the top surface of the conductive pillar 205 is flush with the top surface of the second chip 204 .

[0076] In this embodiment, the function of the first chip 202 is different from the function of the second chip 204 . The first chip 202 includes a logic chip, and the second chip 204 includes a memory chip.

[0077] Accordingly, the present invention also provides a packaging method, please refer to Fig.10 , provide a wiring substrate 400, align the semiconductor chip 300 and the wiring substrate 400, weld the aligned semiconductor chip 300 and the wiring substrate 400, and electrically connect the semiconductor chip 300 and the wiring substrate 400; perform bottom filling between the welded semiconductor chip 300 and the wiring substrate 400, and form an adhesive layer 401 between the semiconductor chip 300 and the wiring substrate 400.

[0078] Please continue to refer to Fig.10 After forming the adhesive layer 401 , the method further includes forming metal balls 402 on the wiring substrate 400 , wherein the metal balls 402 and the semiconductor chip 300 are located on both sides of the wiring substrate 400 .

[0079] Please refer to Fig.10Accordingly, the packaging structure of the present invention includes a semiconductor chip 300 having a conductive protrusion 301 connected to a conductive pillar 205; a wiring substrate 400; and an adhesive layer 401 located between the semiconductor chip 300 and the wiring substrate 400.

[0080] In this embodiment, since the first chip 202 is embedded in the substrate 200, it is ensured that the surface for forming the redistribution layer 203 is smoother, and the pitch of the redistribution layer 203 can be achieved to be less than 1 micron, thereby ensuring that the quality of the dielectric layer that can be formed is better, thereby facilitating the formation of a high-quality and smaller-pitch redistribution layer 203 with a wider range of applications; at the same time, the projections of the first chip 202 and the second chip 204 partially overlap, and the transmission distance between the first chip 202 and the second chip 204 is short, which can more easily adapt to high-frequency transmission, and the integration of the semiconductor chip 300 is improved, thereby improving the performance of the final packaging structure.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first surface, the substrate includes a plurality of chip regions, and each of the chip regions has a groove recessed relative to the first surface; a first chip located in the groove, wherein the first surface exposes a functional surface of the first chip; a redistribution layer located on the surface of the first surface and the surface of the functional surface of the first chip, wherein the redistribution layer has a conductive structure; a second chip located on the surface of the redistribution layer on each of the chip regions, the second chip being electrically connected to the first chip via the conductive structure, and a projection of the first chip toward the substrate surface partially overlapping a projection of the second chip toward the substrate surface; A conductive column is located on the surface of the redistribution layer on each chip area, and the conductive column is electrically connected to the first chip through the conductive structure.

2. The semiconductor structure according to claim 1, wherein: Also includes: A plastic encapsulation layer is located on the surface of the redistribution layer, the second chip and the conductive pillar are located in the plastic encapsulation layer, and the plastic encapsulation layer exposes the surface of the second chip.

3. The semiconductor structure according to claim 1, wherein: The function of the first chip is different from the function of the second chip.

4. The semiconductor structure according to claim 3, characterized in that The first chip includes a logic chip, and the second chip includes a memory chip.

5. The semiconductor structure according to claim 1, wherein: The redistribution layer includes an insulating layer located on a surface of the first surface and a surface of a functional surface of the first chip, and the conductive structure is located in the insulating layer.

6. A method for forming a semiconductor structure according to any one of claims 1 to 5, characterized in that: include: Providing a substrate, wherein the substrate has a first surface and includes a plurality of chip regions; Etching a portion of the thickness of the substrate in each chip region to form a groove in the chip region that is recessed relative to the first surface; Placing a first chip in the groove, with the first surface exposing a functional surface of the first chip; forming a redistribution layer on the surface of the first surface and the functional surface of the first chip, wherein the redistribution layer has a conductive structure; A second chip is connected to the surface of the redistribution layer of each chip region, the second chip is electrically connected to the first chip through the conductive structure, and a projection of the first chip toward the substrate surface partially overlaps with a projection of the second chip toward the substrate surface; Conductive pillars are formed on the surface of the redistribution layer on each of the chip regions, and the conductive pillars are electrically connected to the first chip through the conductive structure.

7. A semiconductor chip, characterized in that: include: A substrate unit, the substrate unit having a first surface, and the substrate unit having a groove recessed relative to the first surface; a first chip located in the groove, wherein the first surface exposes a functional surface of the first chip; a redistribution layer located on the surface of the first surface and the surface of the functional surface of the first chip, wherein the redistribution layer has a conductive structure; a second chip located on the surface of the redistribution layer, the second chip being electrically connected to the first chip through the conductive structure, and a projection of the first chip toward the substrate surface partially overlapping a projection of the second chip toward the substrate surface; A conductive column is located on the surface of the redistribution layer on the chip area, and the conductive column is electrically connected to the first chip through the conductive structure.

8. The semiconductor chip according to claim 7, wherein: The function of the first chip is different from the function of the second chip.

9. The semiconductor chip according to claim 7, characterized in that: The first chip includes a logic chip, and the second chip includes a memory chip.

10. The semiconductor chip according to claim 7, wherein: The redistribution layer includes an insulating layer located on a surface of the first surface and a surface of a functional surface of the first chip, and the conductive structure is located in the insulating layer.

11. The semiconductor chip according to claim 7, characterized in that: It comprises a plastic encapsulation layer located on the surface of the redistribution layer, the plastic encapsulation layer encapsulates the second chip and the conductive pillar, and the plastic encapsulation layer exposes the surface of the second chip and the surface of the conductive pillar.

12. A method for forming a semiconductor chip according to any one of claims 7 to 11, characterized in that: include: Providing a substrate, wherein the substrate has a first surface and includes a plurality of chip regions; Etching a portion of the thickness of the substrate in each chip region to form a groove in the chip region that is recessed relative to the first surface; Placing a first chip in the groove, with the first surface exposing a functional surface of the first chip; forming a redistribution layer on the surface of the first surface and the functional surface of the first chip, wherein the redistribution layer has a conductive structure; A second chip is connected to the surface of the redistribution layer of each chip region, the second chip is electrically connected to the first chip through the conductive structure, and a projection of the first chip toward the substrate surface partially overlaps with a projection of the second chip toward the substrate surface; forming a conductive column on the surface of the redistribution layer on each of the chip regions, wherein the conductive column is electrically connected to the first chip through the conductive structure; After the conductive pillars are formed, the substrate between the chip regions is cut to separate the chip regions from each other to form a plurality of independent semiconductor chips.

13. A packaging method, characterized in that: include: Providing a semiconductor chip according to any one of claims 7 to 11; providing a wiring substrate; Aligning the semiconductor chip and the wiring substrate; Soldering the aligned semiconductor chip and the wiring substrate to electrically connect the semiconductor chip and the wiring substrate; An underfill is performed between the semiconductor chip and the wiring substrate after soldering to form an adhesive layer between the semiconductor chip and the wiring substrate.

14. The packaging method according to claim 13, characterized in that: After forming the adhesive layer, the method further includes forming metal balls on the wiring substrate, wherein the metal balls and the semiconductor chip are located on both sides of the wiring substrate.

15. A packaging structure, characterized in that: include: The semiconductor chip according to any one of claims 7 to 11, wherein the semiconductor chip has a conductive protrusion connected to the conductive pillar; Wiring substrate; An adhesive layer is located between the semiconductor chip and the wiring substrate.

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