Radiator with escape groove, preparation method thereof and chip packaging method

Abstract

The invention provides a radiator with an escape groove, a preparation method of the radiator and a chip packaging method. The radiator provided by the invention comprises a cover surface and a surrounding part which extends downwards along the edge of the cover surface, wherein the lower surface of the cover surface is provided with at least one chip fixing area; each chip fixing area is used for fixing one chip; each chip fixing area is provided with an escape groove; the size of the escape groove on each chip fixing area is smaller than that of a chip to be fixed on the chip fixing area; wherein when the chips are packaged, any chip is fixed in one chip fixing area through the first soldering flux layer, the interface heat dissipation material layer and the second soldering flux layer in sequence, and the second soldering flux layer is in complete contact with the lower surface and is not in complete contact with the groove bottom of the escape groove, so that in the reflow soldering process, the first soldering flux layer and the second soldering flux layer are fixed in the chip fixing area. And enabling the liquefied or gasified second soldering flux layer to move through the escape groove so as to escape from the area between the lower surface and the chip.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a heat sink with an escape groove, a preparation method thereof, and a chip packaging method. Background Art

[0002] In recent years, with the development of artificial intelligence and graphics processors, their performance requirements have continued to grow, leading to the gradual prevalence of chip packaging structures. In the chip packaging process, flux is generally used between the heat sink and the chip to form solder joints of the interface heat dissipation material. However, when soldering the heat sink and the chip, the flux residue cannot escape between the heat sink and the chip. The flux residue will evaporate and expand in the interface heat dissipation material layer, generating voids in the interface heat dissipation material layer, affecting the heat dissipation performance of the interface heat dissipation material layer. Summary of the invention

[0003] In view of this, the present application provides a heat sink with an escape groove, a preparation method thereof, and a chip packaging method, which are used to effectively remove the flux trapped between the heat sink and the chip through the escape groove to improve the heat dissipation performance of the chip packaging structure.

[0004] Specifically, the present application is implemented through the following technical solutions: A first aspect of the present application provides a heat sink with an escape groove, the heat sink comprising a cover surface and a surrounding portion extending downward along an edge of the cover surface; The lower surface of the cover has at least one chip fixing area; each chip fixing area is used to fix a chip; each chip fixing area has an escape groove; the size of the escape groove on each chip fixing area is smaller than the size of the chip to be fixed on the chip fixing area; Among them, when the chip is packaged, any chip is fixed in a chip fixing area in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is completely in contact with the lower surface and not completely in contact with the bottom of the escape groove, so that during the reflow process, the liquefied or vaporized second flux layer moves through the escape groove to escape from the area between the lower surface and the chip.

[0005] The second aspect of the present application provides a method for preparing a heat sink with an escape groove, the method for preparing the heat sink with an escape groove provided in the first aspect of the present application, the method comprising: Prepare an initial heat sink; wherein the initial heat sink comprises a cover surface and a surrounding portion extending downward along an edge of the cover surface; the lower surface of the cover surface has at least one chip fixing area, and each chip fixing area is used to fix a chip; An escape groove is formed on each chip fixing area; wherein the size of the escape groove is smaller than the size of the chip to be fixed on the chip fixing area; when packaging the chip, any chip is fixed on one of the chip fixing areas in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is in contact with the lower surface and not in contact with the bottom of the escape groove, so that in the reflow process, the liquefied or vaporized second flux moves horizontally through the escape groove to escape from the area between the lower surface and the chip.

[0006] A third aspect of the present application provides a chip packaging method, the method comprising: soldering at least one chip to the substrate; For each chip, a first solder flux layer, an interface heat dissipation material layer and a second solder flux layer are sequentially arranged on the chip; The heat sink is placed on the second flux layer in a manner that the chip fixing area is directly opposite to the chip to form an intermediate structure; wherein the heat sink is the heat sink provided in the first aspect of the present application; after the heat sink is fixed on the second flux layer, the second flux layer is in full contact with the lower surface of the heat sink and is not in full contact with the bottom of the escape groove on the chip fixing area; The intermediate structure is processed by a reflow process so that the liquefied or vaporized second solder flux escapes from the area between the lower surface and the chip through the escape groove, and the chip is welded on the heat sink through the melted interface heat dissipation material.

[0007] The present application provides a heat sink with an escape groove, a preparation method thereof, and a chip packaging method. The heat dissipation cover provided in the present embodiment is provided with at least one chip fixing area on the lower surface of the cover surface, and an escape groove with a size smaller than the size of the chip to be fixed on the chip fixing area is provided on each chip fixing area. In this way, when the chip is packaged, any chip can be fixed in one of the chip fixing areas in sequence through the first flux layer, the interface heat dissipation material layer, and the second flux layer, and the second flux layer is completely in contact with the lower surface and not completely in contact with the bottom of the escape groove. In this way, in the reflow soldering process, a certain release space can be formed above the chip through the escape groove. When the second flux layer is liquefied or vaporized, the liquefied or vaporized second flux layer tries to diffuse to the surroundings. Due to the existence of the escape groove, there is enough space in the escape groove for the liquefied or vaporized second flux layer to flow and escape. The liquefied or vaporized second flux layer can move along the escape groove and escape from the area between the lower surface and the chip, thereby avoiding the formation of voids on the interface heat dissipation material layer due to the residue of the second flux layer, and improving the heat conduction efficiency between the chip and the radiator. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic structural diagram of a first embodiment of a heat sink with an escape groove provided in the present application; Figure 2 A diagram showing the matching relationship between a heat sink and a chip according to an exemplary embodiment of the present application; Figure 3 A schematic diagram of a chip package in which a heat sink is located according to an exemplary embodiment of the present application; Figure 4 A schematic diagram of a second embodiment of a heat dissipation cover provided in the present application; Figure 5 A schematic diagram of a chip package in which a heat sink is located according to another exemplary embodiment of the present application; Figure 6 A schematic diagram of a heat dissipation cover according to an exemplary embodiment of the present application; Figure 7 A schematic diagram showing the implementation principle of the escape of the second soldering flux after liquefaction or vaporization according to an exemplary embodiment of the present application; Figure 8 A schematic diagram of a chip package in which a heat sink is located according to another exemplary embodiment of the present application; Fig. 9 A schematic diagram of a chip package in which a heat sink is located according to another exemplary embodiment of the present application; Fig.10 This is a flow chart of Example 1 of a method for preparing a heat sink with an escape groove provided in the present application.

[0009] Description of reference numerals: 1: Cover the surface; 2: surrounding part; 3: Chip fixing area; 4: escape slot; 5: First flux layer; 6: Interface heat dissipation material layer; 7: Second flux layer. DETAILED DESCRIPTION

[0010] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0011] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0012] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0013] Specific embodiments are given below to introduce the technical solution of the present application in detail.

[0014] Figure 1 This is a schematic structural diagram of a first embodiment of a heat sink with an escape groove provided in the present application. Figure 2 This is a diagram showing the matching relationship between a heat sink and a chip according to an exemplary embodiment of the present application. Figure 3 This is a schematic diagram of a chip package where a heat sink is located according to an exemplary embodiment of the present application. Figure 1 Figure A is a three-dimensional diagram of the radiator. Figure 1 Figure B in the figure is a cross-sectional view of the radiator; Figure 2 Figure A is a three-dimensional diagram of the matching structure of the heat sink and the chip. Figure 2 Figure B is a cross-sectional view of the matching structure of the heat sink and the chip. Figure 3 Figure A is a cross-sectional view of the chip packaging structure along the length direction (the length direction is Figure 1 left and right directions as shown), Figure 3 Figure B is a cross-sectional view of the chip packaging structure along the width direction (the width direction is Figure 1 (direction perpendicular to the paper as shown).

[0015] Please also refer to Figure 1 , Figure 2 and Figure 3 The heat sink provided in this embodiment includes a cover surface 1 and a surrounding portion 2 extending downward along the edge of the cover surface 1; The lower surface of the cover surface 1 has at least one chip fixing area 3; each chip fixing area 3 is used to fix a chip; each chip fixing area 3 has an escape groove 4; the size of the escape groove 4 on each chip fixing area 3 is smaller than the size of the chip to be fixed on the chip fixing area 3; Among them, when the chip is packaged, any chip is fixed in a chip fixing area 3 in sequence through the first flux layer 5, the interface heat dissipation material layer 6 and the second flux layer 7, and the second flux layer 7 is completely in contact with the lower surface and not completely in contact with the bottom of the escape groove 4, so that during the reflow process, the liquefied or vaporized second flux layer 7 moves through the escape groove 4 to escape from the area between the lower surface and the chip.

[0016] Specifically, the heat sink includes a cover surface 1 and a surrounding portion 2 extending downward along the edge of the cover surface 1. It can be understood that the heat sink is a cover-shaped object. Further, the shape of the cover surface 1 can be a rectangular parallelepiped, and the rectangular cover surface 1 can provide a relatively large heat dissipation area. Further, the surrounding portion 2 extends downward along the edges of the cover surface 1. The surrounding portion 2 is similar to a frame. When the chip is packaged, the lower surface of the surrounding portion 2 is fixedly connected to the base, and the heat dissipation cover and the base are surrounded to form a chip packaging cavity.

[0017] It should be noted that the material of the heat sink is set according to actual needs and is not limited in this embodiment. For example, in one embodiment, the material of the heat sink may be a metal material, such as copper, aluminum, silver, etc.; for another example, in another embodiment, the material of the heat sink may be an alumina ceramic material.

[0018] Furthermore, Figure 4 Schematic diagram of the second embodiment of the heat dissipation cover provided in this application ( Figure 4 Specifically, it is a bottom view of the heat dissipation cover). Figure 5 This is a schematic diagram of a chip package in which a heat sink is located according to another exemplary embodiment of the present application. Figure 1 , Figure 4 and Figure 5 The lower surface of the cover surface 1 has at least one chip fixing area 3, for example, Figure 1 In the example shown, the lower surface of the cover surface 1 has a chip fixing area 3. Figure 4 and Figure 5 In the example shown, the lower surface of the cover surface 1 has two chip fixing areas 3. For the convenience of description, the two chip fixing areas 3 are respectively recorded as a first chip fixing area and a second chip fixing area in order from left to right.

[0019] It should be noted that the lower surface of the cover surface 1 refers to the side of the cover surface 1 facing the substrate. In addition, the chip fixing area 3 is used to fix the chip.

[0020] Please continue to refer to Figures 1 to 4 Each chip fixing area 3 has an escape groove 4. For further information, please continue to refer to Figure 2 and Figure 3, the size of the escape groove 4 on each chip fixing area 3 is smaller than the size of the chip to be fixed on the chip fixing area 3. For example, the size of the escape groove 4 on each chip fixing area 3 in the first direction is smaller than the size of the chip to be fixed on the chip fixing area 3 in the first direction, and / or, the size of the escape groove 4 on each chip fixing area 3 in the second direction is smaller than the size of the chip to be fixed on the chip fixing area 3 in the second direction; wherein the first direction is the length direction of the heat dissipation cover, and the second direction is the width direction of the heat dissipation cover. For example, Figure 2 and Figure 3 In the example shown, the dimension of the escape groove 4 in the length direction is larger than the dimension of the chip in the length direction, and the dimension of the escape groove 4 in the width direction is smaller than the dimension of the chip in the length direction.

[0021] It should be noted that the heat dissipation cover provided in this embodiment makes the size of the escape groove 4 on each chip fixing area 3 smaller than the size of the chip to be fixed on the chip fixing area 3. In this way, when the chip is packaged, the chip can partially cover the escape groove 4 to avoid the chip falling into the escape groove 4 completely, so that the second flux after liquefaction or vaporization can be used to discharge it during the reflow soldering process.

[0022] Specifically, Figure 6 This is a schematic diagram of a heat dissipation cover according to an exemplary embodiment of the present application. Figure 6 Figures A, B, C, D and E in the figure show heat sinks with escape grooves 4 in different forms.

[0023] Please refer to Figure 6 Optionally, in a possible implementation, the escape groove 4 on each chip fixing area 3 includes at least one of the following forms of escape grooves 4: a straight groove, a cross-shaped escape groove composed of multiple straight grooves, and a groove array composed of multiple grooves; wherein the multiple grooves are curved grooves, broken line grooves or straight grooves.

[0024] For example, in Figure 6 In the example shown in Figure A, the escape groove 4 is in the form of a straight-line sink groove; Figure 6 In the example shown in FIG. B, the escape groove 4 is in the form of a schematic diagram of a cross-shaped escape groove composed of a plurality of straight-shaped sink grooves; Figure 6 In the example shown in FIG. C, the escape groove 4 is in the form of a sink array consisting of a plurality of straight-line sinks; Figure 6 In the example shown in FIG. D, the escape trough 4 is in the form of a schematic diagram of a sink array consisting of a plurality of broken line sinks; Figure 6 In the example shown in Figure E in FIG. 1 , the escape trough 4 is in the form of a sink array consisting of a plurality of curved sinks.

[0025] It should be noted that when the escape trough 4 is in the form of a trough array consisting of a plurality of troughs, the number of troughs included in the trough array and the spacing between the troughs are set according to actual needs, and are not limited in this embodiment.

[0026] It should be noted that the heat dissipation cover includes a plurality of chip fixing areas 3, and the shapes of the escape grooves 4 on different chip fixing areas 3 may be the same or different, and are not limited in this embodiment. Figure 4 In the example shown, the escape groove 4 on the first chip fixing area is a straight-line groove, and the escape groove 4 on the second chip fixing area is a groove array composed of a plurality of straight-line grooves.

[0027] For further information, please refer to Figure 3 and Figure 5 When packaging the chip, any chip is fixed in a chip fixing area 3 in sequence through the first flux layer 5, the interface heat dissipation material layer 6 and the second flux layer 7. Specifically, the first flux layer 5 is arranged between the chip and the interface heat dissipation material layer 6, and is in full contact with the chip and the interface heat dissipation material layer 6, so as to enhance the adhesion between the chip and the interface heat dissipation material layer 6 and ensure good bonding between the chip and the interface heat dissipation material layer 6. Furthermore, the interface heat dissipation material layer 6 is used to achieve heat dissipation between the chip and the heat sink, and is usually made of a high thermal conductivity material to ensure that heat can be quickly transferred from the chip to the heat sink to prevent the chip from overheating. The second flux layer 7 is arranged between the interface heat dissipation material layer 6 and the heat dissipation cover, and is in full contact with the interface heat dissipation material layer 6, and is in full contact with the lower surface of the heat dissipation cover, but is not in full contact with the bottom of the escape groove 4 on the lower surface, so as to provide appropriate space for the escape groove 4 to handle gas escape.

[0028] Referring to the above description, in this way, during the reflow process, the liquefied or vaporized second solder flux can escape horizontally through the escape groove 4 without leaving voids on the interface heat dissipation material layer 6 to affect the performance and effect of the chip packaging.

[0029] Furthermore, Figure 7 This is a schematic diagram showing the implementation principle of the second soldering flux escaping after liquefaction or vaporization according to an exemplary embodiment of the present application. Figure 7In the reflow soldering process, as the temperature rises, the second flux layer 7 liquefies or vaporizes, and the second flux between the chip and the lower surface of the heat sink cover 1 changes from a solid state to a liquefied or vaporized state. The liquefied or vaporized second flux layer 7 seeks to release space in the liquid or gaseous state. In the heat sink provided by the present embodiment, the size of the escape groove 4 of each chip fixing area 3 is smaller than the chip to be fixed. In this way, when the chip is packaged, the second flux layer 7 is completely in contact with the lower surface, but not completely in contact with the bottom of the escape groove 4. In this way, the second flux layer 7 can be completely in contact with the lower surface, but not completely in contact with the bottom of the escape groove 4. A certain release space is formed above the chip. When the second flux layer 7 is liquefied or vaporized, the liquefied or vaporized second flux layer 7 tries to diffuse to the surroundings. Due to the existence of the escape groove 4, there is enough space in the escape groove 4 for the liquefied or vaporized second flux layer 7 to flow and escape. The liquefied or vaporized second flux layer 7 can move along the escape groove 4 and escape from the area between the lower surface and the chip, thereby avoiding the formation of voids on the interface heat dissipation material layer 6 due to the residue of the second flux layer 7, so as to improve the heat conduction efficiency between the chip and the heat sink.

[0030] The heat dissipation cover provided in this embodiment is provided with at least one chip fixing area on the lower surface of the cover surface, and an escape groove with a size smaller than the size of the chip to be fixed on the chip fixing area is provided on each chip fixing area. In this way, when the chip is packaged, any chip can be fixed in one of the chip fixing areas in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is made to be in full contact with the lower surface and incompletely contact with the bottom of the escape groove. In this way, in the reflow soldering process, a certain release space can be formed above the chip through the escape groove. When the second flux layer is liquefied or vaporized, the liquefied or vaporized second flux layer tries to diffuse to the surroundings. Due to the existence of the escape groove, there is enough space in the escape groove for the liquefied or vaporized second flux layer to flow and escape. The liquefied or vaporized second flux layer can move along the escape groove and escape from the area between the lower surface and the chip, thereby avoiding the formation of voids on the interface heat dissipation material layer due to the residue of the second flux layer, and improving the heat conduction efficiency between the chip and the heat sink.

[0031] Specifically, Figure 8 This is a schematic diagram of a chip package where a heat sink is located according to another exemplary embodiment of the present application. Figure 8 Figure A is a cross-sectional view of the chip package in the length direction. Figure 8 Figure B is a cross-sectional view of the chip package in the width direction.

[0032] Please also refer to Figure 3 and Figure 8Optionally, in a possible implementation, the length of the escape groove 4 on each chip fixing area 3 is equal to 50% to 150% of the length of the chip to be fixed on the chip fixing area 3 in the length direction of the escape groove 4, and the width of the escape groove 4 is smaller than the length of the chip to be fixed on the chip fixing area 3 in the width direction of the escape groove 4.

[0033] For example, in Figure 3 In the example shown, the length of the escape groove 4 on each chip fixing area 3 is greater than the length of the chip to be fixed on the chip fixing area 3 in the length direction of the escape groove 4. Figure 8 In the example shown, the length of the escape groove 4 on each chip fixing area 3 is smaller than the length of the chip to be fixed on the chip fixing area 3 in the length direction of the escape groove 4 .

[0034] Optional, please continue to refer to Figure 3 and Figure 8 The width of the escape groove 4 on each chip fixing area 3 is greater than or equal to 0.02 mm and less than or equal to 4 mm.

[0035] Please refer to Figure 6 When the escape groove 4 is a straight groove, its length direction is the length direction of the straight groove, and the width direction is the width direction of the straight groove; further, when the escape groove 4 is a cross-shaped escape groove composed of multiple straight grooves, its length direction is the length direction of the rectangular area surrounded by the cross-shaped escape groove, and the width direction is the width direction of the rectangular area; when the escape groove 4 is a groove array composed of multiple grooves, its length direction is the length direction of the rectangular area surrounded by the groove array, and the width direction is the width direction of the rectangular area.

[0036] Fig. 9 This is a schematic diagram of a chip package in which a heat sink is located according to another exemplary embodiment of the present application. Figure 3 and Fig. 9 , the bottom of the escape groove 4 is a plane; or the bottom of the escape groove 4 is a curved surface convex away from the lower surface. Figure 3 In the example shown, the bottom of the escape groove 4 is a curved surface that convexly moves away from the lower surface; Fig. 9 In the example shown, the groove bottom of the escape groove 4 is a flat surface.

[0037] Optionally, in a possible implementation, when the bottom of the escape groove 4 is a plane, the depth of the escape groove 4 ranges from 0.05 mm to 0.9 mm, and when the bottom of the escape groove 4 is a curved surface convex away from the lower surface, the depth difference between the lowest depth and the highest depth of the escape groove 4 is between 0 mm and 0.9 mm.

[0038] For details, please continue to refer to Figure 3 When the bottom of the escape groove 4 is a curved surface convex in a direction away from the lower surface, the depth difference between the lowest depth and the highest depth of the escape groove 4 is between 0 mm and 0.9 mm; please continue to refer to Fig. 9 , the bottom of the escape groove 4 is a plane, and at this time, the depth of the escape groove ranges from 0.05 mm to 0.9 mm.

[0039] Optionally, in a possible implementation, a nickel layer is plated on the lower surface, and a gold layer is plated on the nickel layer; or, The lower surface is plated with a nickel layer, and the nickel layer is plated with a gold layer on the area except the escape groove 4; or, A nickel layer is plated on the lower surface, and a gold layer is plated on the nickel layer except for the escape groove and a partial area on the escape groove.

[0040] Specifically, after the nickel layer is plated on the lower surface, the gold layer is plated, which can form a double-layer protective structure to extend the service life of the radiator. Since the function of the escape groove 4 is to allow the vaporized or liquefied solder flux to escape, only the nickel layer needs to be plated on the escape groove 4 area, which is conducive to reducing costs and ensuring that the solder flux is discharged during the reflow soldering process. In addition, after the nickel layer is plated on the lower surface, the gold layer can be plated on the area outside the escape groove 4 and part of the area on the escape groove 4. In this way, the characteristics of gold can be used to a certain extent to solve the problems that may occur in the local escape groove 4. For example, it can prevent corrosion at the edge of the escape groove 4 (because the edge of the escape groove 4 may have more contact with the external environment), and at the same time, gold is plated on most of the non-escape groove area to obtain overall good performance.

[0041] Corresponding to the aforementioned embodiment of a heat sink with an escape groove, the present application also provides an embodiment of a method for preparing a heat sink with an escape groove.

[0042] Fig.10 This is a flow chart of Example 1 of the method for preparing a heat sink with an escape groove provided in this application. Fig.10 The method provided in this embodiment is used to prepare a heat sink with an escape groove as provided in the first aspect of the present application, and the preparation method comprises: S101, preparing an initial heat sink; wherein the initial heat sink comprises a cover surface and a surrounding portion extending downward along an edge of the cover surface; the lower surface of the cover surface has at least one chip fixing area, and each chip fixing area is used to fix a chip.

[0043] S102, forming an escape groove on each chip fixing area; wherein the size of the escape groove is smaller than the size of the chip to be fixed on the chip fixing area; when packaging the chip, any chip is fixed on one of the chip fixing areas in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is in contact with the lower surface and not in contact with the bottom of the escape groove, so that during the reflow process, the liquefied or vaporized second flux moves horizontally through the escape groove to escape from the area between the lower surface and the chip.

[0044] Specifically, in a possible implementation manner, forming an escape groove on each chip fixing area includes: The escape groove is formed on each chip fixing area by any of the following processes: electrical discharge machining, stamping, numerical control machining, and chemical etching.

[0045] The method provided in this embodiment can be used to prepare any heat dissipation cover described in the first aspect of the present application to improve the heat conduction efficiency between the chip and the heat sink.

[0046] The present application also provides a chip packaging method, the method comprising: soldering at least one chip to the substrate; For each chip, a first solder flux layer, an interface heat dissipation material layer and a second solder flux layer are sequentially arranged on the chip; The heat sink is placed on the second flux layer in a manner that the chip fixing area is directly opposite to the chip to form an intermediate structure; wherein the heat sink is the heat sink provided in the first aspect of the present application; after the heat sink is fixed on the second flux layer, the second flux layer is in full contact with the lower surface of the heat sink and is not in full contact with the bottom of the escape groove on the chip fixing area; The intermediate structure is processed by a reflow process so that the liquefied or vaporized second solder flux escapes from the area between the lower surface and the chip through the escape groove, and the chip is welded on the heat sink through the melted interface heat dissipation material.

[0047] The chip packaging method provided in this embodiment can ensure that the liquefied or vaporized second flux escapes from the area between the lower surface and the chip through the escape groove, preventing residual flux from forming voids on the interface heat dissipation material, and improving the heat dissipation effect of the formed chip packaging structure.

[0048] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A heat sink with an escape groove, characterized in that: The heat sink comprises a cover surface and a surrounding portion extending downward along an edge of the cover surface; The lower surface of the cover has at least one chip fixing area; each chip fixing area is used to fix a chip; each chip fixing area has an escape groove; the size of the escape groove on each chip fixing area is smaller than the size of the chip to be fixed on the chip fixing area; Among them, when the chip is packaged, any chip is fixed in a chip fixing area in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is completely in contact with the lower surface and not completely in contact with the bottom of the escape groove, so that during the reflow process, the liquefied or vaporized second flux layer moves through the escape groove to escape from the area between the lower surface and the chip.

2. The heat sink according to claim 1, characterized in that: The escape grooves on each chip fixing area include at least one of the following forms of escape grooves: a straight groove, a cross-shaped escape groove composed of multiple straight grooves, and a groove array composed of multiple grooves; wherein the multiple grooves are curved grooves, broken line grooves or straight grooves.

3. The radiator according to claim 1 or 2, characterized in that: The bottom of the escape groove is a plane; or, The bottom of the escape groove is a curved surface convex in a direction away from the lower surface.

4. The radiator according to claim 1 or 2, characterized in that: The length of the escape groove on each chip fixing area is equal to 50% to 150% of the length of the chip to be fixed on the chip fixing area in the length direction of the escape groove, and the width of the escape groove is smaller than the length of the chip to be fixed on the chip fixing area in the width direction of the escape groove.

5. The heat sink according to claim 4, characterized in that: The width of the escape groove on each chip fixing area is greater than or equal to 0.02 mm and less than or equal to 4 mm.

6. The heat sink according to claim 3, characterized in that: When the bottom of the escape groove is a plane, the depth of the escape groove is greater than or equal to 0.05 mm and less than or equal to 0.9 mm.

7. The heat sink according to claim 3, characterized in that: When the groove bottom of the escape groove is a curved surface convex in a direction away from the lower surface, the depth difference between the lowest depth and the highest depth of the escape groove is greater than 0 mm and less than 0.9 mm.

8. The heat sink according to claim 1, characterized in that The lower surface is plated with a nickel layer, and the nickel layer is plated with a gold layer; or, The lower surface is plated with a nickel layer, and the nickel layer is plated with a gold layer on the area except the escape groove; or, A nickel layer is plated on the lower surface, and a gold layer is plated on the nickel layer except for the escape groove and a partial area on the escape groove.

9. A method for preparing a heat sink with an escape groove, characterized in that: The preparation method is used to prepare the heat sink with escape groove according to any one of claims 1 to 8, and the preparation method comprises: Prepare an initial heat sink; wherein the initial heat sink comprises a cover surface and a surrounding portion extending downward along an edge of the cover surface; the lower surface of the cover surface has at least one chip fixing area, and each chip fixing area is used to fix a chip; An escape groove is formed on each chip fixing area; wherein the size of the escape groove is smaller than the size of the chip to be fixed on the chip fixing area; when packaging the chip, any chip is fixed on one of the chip fixing areas in sequence through the first flux layer, the interface heat dissipation material layer and the second flux layer, and the second flux layer is in contact with the lower surface and not in contact with the bottom of the escape groove, so that in the reflow process, the liquefied or vaporized second flux moves horizontally through the escape groove to escape from the area between the lower surface and the chip.

10. The preparation method according to claim 9, characterized in that: The step of forming an escape groove on each chip fixing area comprises: The escape groove is formed on each chip fixing area by any of the following processes: electrical discharge machining, stamping, numerical control machining, and chemical etching.

11. A chip packaging method, characterized in that: The method comprises: soldering at least one chip to the substrate; For each chip, a first solder flux layer, an interface heat dissipation material layer and a second solder flux layer are sequentially arranged on the chip; The heat sink is placed on the second flux layer in a manner that the chip fixing area is directly opposite to the chip to form an intermediate structure; wherein the heat sink is the heat sink as described in any one of claims 1 to 8; after the heat sink is fixed on the second flux layer, the second flux layer is in full contact with the lower surface of the heat sink and is not in full contact with the bottom of the escape groove on the chip fixing area; The intermediate structure is processed by a reflow process so that the liquefied or vaporized second solder flux escapes from the area between the lower surface and the chip through the escape groove, and the chip is welded on the heat sink through the melted interface heat dissipation material.

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