Driving circuit and vertical cavity surface emitting laser system

Abstract

The invention provides a driving circuit. The output end of a bias current control sub-circuit is connected with the output end of an output driving sub-circuit and a driven element; the output driving sub-circuit comprises a differential pair module circuit, a source electrode of a PMOS transistor is connected with a power supply, and a drain electrode of the PMOS transistor is connected with a load resistor RL1 and a load resistor RL2 to form an intersection point; the end, close to a driven element, of the load resistor RL2 is the output end of the output driving sub-circuit and connected with one end of the load resistor Rf, and the end, away from the load resistor RL2, of the load resistor Rf is connected with the first input end of the first operational amplifier. The end, close to the PMOS transistor, of the load resistor RL1 is connected with one end of the load resistor Rref, and the end, away from the load resistor RL1, of the load resistor Rref is connected with the second input end of the first operational amplifier and connected with a first current source. The output end of the first operational amplifier is connected with the grid electrode of the PMOS transistor. The invention provides an optimized driving circuit which can realize higher-speed optical communication application.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a driving circuit and a vertical cavity surface emitting laser system. Background Art

[0002] In modern optical communication systems, vertical cavity surface emitting laser (VCSEL) drivers are widely used due to their excellent performance such as low power consumption, high bandwidth, small size, low cost and easy integration. Due to the limitations of cost and component structure, VCSEL drivers usually use DC-coupled VCSEL lasers with common cathodes. The optical power requirements of VCSELs are different in different application environments, so the driver bias current requirements vary greatly. In high-speed communications, due to the constraints of the driver's operating voltage and power consumption, a 4~8mA bias current is usually used, and a larger operating current means a higher operating voltage of the VCSEL, which will cause the power supply voltage margin to become smaller, so the bias circuit design is required. The existing technical solution is to raise the driving level voltage to ensure the voltage margin and circuit performance, but a new power supply will be introduced to increase the complexity of the circuit and increase the power consumption, resulting in high impedance from the output node, which is not matched with the VCSEL, and will emit signal reflections and other problems, resulting in signal quality degradation in high-speed applications, and the current source needs to flow a large current, resulting in a large transistor size, generating a large parasitic capacitance and thus affecting the high-frequency performance. There is currently no simple and effective solution to the above defects. Summary of the invention

[0003] The object of the present invention is to provide a driving circuit and a vertical cavity surface emitting laser system, which realizes higher speed optical communication applications through the optimized design of bias current control subcircuit, modulation current control subcircuit and output driving subcircuit.

[0004] To achieve the above-mentioned purpose, the present invention provides a driving circuit, comprising a bias current control subcircuit and an output driving subcircuit; the bias current control subcircuit input end is connected to a power supply, and the bias current control subcircuit output end is connected to the output end of the output driving subcircuit and the driven element; the output driving subcircuit comprises a differential pair module circuit, the differential pair module circuit comprises a load resistor RL1 and a load resistor RL2, a PMOS transistor is provided between the power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2, the source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor is connected to the load resistor RL1 and the load resistor RL2 and form an intersection; one end of the load resistor RL2 close to the driven element is the output end of the output driving sub-circuit, and one end of the load resistor RL2 close to the driven element is also connected to one end of a load resistor Rf, and one end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; one end of the load resistor RL1 close to the PMOS transistor is also connected to one end of a load resistor Rref, and one end of the load resistor Rref away from the load resistor RL1 is connected to the second input end of the first operational amplifier, and one end of the load resistor Rref away from the load resistor RL1 is connected to the first current source; the output end of the first operational amplifier is connected to the gate of the PMOS transistor.

[0005] Optionally, the bias current control subcircuit includes a current mirror module circuit.

[0006] Optionally, the current mirror module circuit includes a cascade structure circuit.

[0007] Optionally, the differential pair module circuit also includes a second current source, a transistor Q1, and a transistor Q2; one end of the second current source is grounded, and the end of the second current source away from the ground direction is connected to the emitter of the transistor Q1, and the end of the second current source away from the ground direction is connected to the emitter of the transistor Q2; the collector of the transistor Q1 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the collector of the transistor Q2 is connected to the end of the load resistor RL2 away from the PMOS transistor.

[0008] Optionally, a transistor Q3 is provided between the transistor Q1 and the load resistor RL1, and a transistor Q4 is provided between the transistor Q2 and the load resistor RL2; the collector of the transistor Q3 is connected to an end of the load resistor RL1 away from the PMOS transistor, and the emitter of the transistor Q3 is connected to the collector of the transistor Q1; the collector of the transistor Q4 is connected to an end of the load resistor RL2 away from the PMOS transistor, and the emitter of the transistor Q4 is connected to the collector of the transistor Q2.

[0009] Optionally, it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q6; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2.

[0010] Optionally, the first current source includes a second operational amplifier, a transistor QB1 and an emitter resistor RE2, and the second current source includes a third operational amplifier, a transistor QB2 and an emitter resistor RE3; one end of the emitter resistor RE2 is grounded, and the end of the emitter resistor RE2 away from the ground direction is connected to the emitter of the transistor QB1 and the reverse input terminal of the second operational amplifier; one end of the emitter resistor RE3 is grounded, and the end of the emitter resistor RE3 away from the ground direction is connected to the emitter of the transistor QB2 and the reverse input terminal of the third operational amplifier; the collector of the transistor QB1 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output terminal of the second operational amplifier; the collector of the transistor QB2 is connected to the emitter of the transistor Q1 and to the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier; the positive input terminals of the second operational amplifier and the third operational amplifier are connected to the first temperature compensation current source.

[0011] Optionally, it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2; the third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; the first current source also includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; one end of the emitter resistor RE4 The end is grounded, and the end of the emitter resistor RE4 away from the ground direction is connected to the emitter of the transistor QB2 and the inverting input terminal of the fourth operational amplifier; one end of the emitter resistor RE5 is grounded, and the end of the emitter resistor RE5 away from the ground direction is connected to the emitter of the transistor QB4 and the inverting input terminal of the fifth operational amplifier; the collector of the transistor QB3 is connected to the emitter of the transistor Q5 and to the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier; the collector of the transistor QB4 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output terminal of the fifth operational amplifier; the positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature compensation current source.

[0012] Optionally, several inductors are also included, and the inductors are used to weaken the parasitic capacitance in the circuit.

[0013] The present invention further provides a vertical cavity surface emitting laser system, comprising any one of the driving circuits described above, wherein the driven element is a vertical cavity surface emitting laser.

[0014] The vertical cavity surface emitting laser system provided by the present invention has the following beneficial effects: The present invention provides a driving circuit, comprising a bias current control subcircuit and an output driving subcircuit; the bias current control subcircuit input end is connected to a power supply, the bias current control subcircuit output end is connected to the output end of the output driving subcircuit and the driven element; the output driving subcircuit comprises a differential pair module circuit, the differential pair module circuit comprises a load resistor RL1 and a load resistor RL2, a PMOS transistor is arranged between the power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2, the source of the PMOS transistor is connected to the power supply of the differential pair module circuit, the drain of the PMOS transistor is connected to the load resistor RL1 and the load resistor RL2 to form a an intersection; the end of the load resistor RL2 close to the driven element is the output end of the output drive subcircuit, the end of the load resistor RL2 close to the driven element is also connected to one end of a load resistor Rf, and the end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; the end of the load resistor RL1 close to the PMOS transistor is also connected to one end of a load resistor Rref, the end of the load resistor Rref away from the load resistor RL1 is connected to the second input end of the first operational amplifier, and the end of the load resistor Rref away from the load resistor RL1 is connected to the first current source; the output end of the first operational amplifier is connected to the gate of the PMOS transistor. In this way, the present invention uses the resistive load and the bias current control subcircuit to modulate the drive current at the same time. The advantage of this solution is that the output impedance matching can be effectively achieved through the resistive load, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the load of the driving stage, which is conducive to improving the circuit bandwidth and achieving a larger gain bandwidth performance. The modulation current control circuit is realized by a feedback loop composed of an operational amplifier. This circuit cooperates with the output stage to form a current clamping circuit to ensure the stability of the output DC current, so that the modulation current and the bias current can be adjusted separately, and it is ensured that the bias current will not flow into the output stage, causing the bias current to be inconsistent with expectations.

[0015] A vertical cavity surface emitting laser system includes a driving circuit as described in any of the above, and the driven element is a vertical cavity surface emitting laser. Since the vertical cavity surface emitting laser system includes the driving circuit, the vertical cavity surface emitting laser system uses a resistive load and the bias current control subcircuit to modulate the driving current. The advantage of this solution is that the output impedance matching can be effectively achieved through the resistive load, and the size of the current mirror load tube of the bias current control subcircuit can be reduced, thereby reducing the load of the driving stage, which is beneficial to improving the circuit bandwidth and achieving a larger gain bandwidth performance. The modulation current control circuit implemented by the feedback loop composed of an operational amplifier, the circuit cooperates with the output stage to form a current clamping circuit to ensure the stability of the output DC current, so that the modulation current and the bias current can be adjusted separately, and it is ensured that the bias current will not flow into the output stage, causing the bias current to be inconsistent with expectations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the circuit principle of a vertical cavity surface emitting laser driver provided by an embodiment of the prior art.

[0017] Figure 2 A schematic diagram of the circuit principle of a driving circuit provided in the first embodiment of the present invention.

[0018] Figure 3 A schematic diagram of the circuit principle of a bias current control subcircuit of a driving circuit provided in a first embodiment of the present invention.

[0019] Figure 4 A schematic diagram of the circuit principle of a bias current control subcircuit of a driving circuit provided in a second embodiment of the present invention.

[0020] Figure 5 This is a schematic circuit diagram of an output drive sub-circuit of a drive circuit provided in a first embodiment of the present invention.

[0021] Figure 6 A schematic diagram of the circuit principle of an output driving sub-circuit of a driving circuit provided in a second embodiment of the present invention.

[0022] Figure 7 A schematic diagram of the circuit principle of an output driving sub-circuit of a driving circuit provided in a third embodiment of the present invention.

[0023] Figure 8 A schematic diagram of the circuit principles of a first current source and a second current source of a driving circuit provided in an embodiment of the present invention.

[0024] Fig. 9 A schematic diagram of the circuit principles of a first current source, a second current source and a third current source of a driving circuit provided in an embodiment of the present invention.

[0025] Fig.10 A schematic diagram of the circuit principle of a driving circuit provided in a second embodiment of the present invention.

[0026] The accompanying drawings are denoted as follows: 01-bias current control subcircuit; 011-bias current control subcircuit current source; 02-output drive subcircuit; 020-intersection point; 021-second current source; 03-modulation current control subcircuit; 031-first current source; driven element; 041-third current source; 051-a compensation current source unit with a temperature coefficient in the first temperature compensation current source; 052-a compensation current source unit without a temperature coefficient in the first temperature compensation current source; 061-a compensation current source unit with a temperature coefficient in the second temperature-compensated current source; 062-a compensation current source unit without a temperature coefficient in the second temperature-compensated current source; 100-Inductor. DETAILED DESCRIPTION

[0027] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0028] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or can include intermediate elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, intermediate elements or layers are not included. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in addition (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "include" is used to determine the inclusion of features, steps, operations, elements and / or parts, but does not exclude the inclusion or addition of one or more other features, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] Please refer to Figure 1 , Figure 1 A schematic diagram of a circuit principle of a vertical cavity surface emitting laser driver provided in an embodiment of the prior art. In the prior art, the voltage margin and circuit performance are guaranteed by raising the driving stage voltage, but a new power supply is introduced to increase the circuit complexity and power consumption. For example, the solution Figure 1 Using a PMOS transistor current source as a DC bias load results in high impedance seen from the output node, which is not matched with the VCSEL and will cause problems such as signal reflection, resulting in degradation of signal quality in high-speed applications. In addition, the current source needs to flow a large current, which results in a large transistor size and a large parasitic capacitance, thus affecting high-frequency performance.

[0030] The object of the present invention is to provide a driving circuit and a vertical cavity surface emitting laser system, which realizes higher speed optical communication applications through the optimized design of bias current control subcircuit, modulation current control subcircuit and output driving subcircuit.

[0031] Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the circuit principle of the driving circuit provided by the first embodiment of the present invention. Figure 2 As shown, in order to achieve the above-mentioned purpose, the present invention provides a driving circuit, including a bias current control subcircuit 01 and an output driving subcircuit 02; The input end of the bias current control subcircuit 01 is connected to the power supply VCC, and the output end of the bias current control subcircuit 01 is connected to the output end of the output drive subcircuit 02 and the driven element 10; The output driving sub-circuit 02 includes a differential pair module circuit, the differential pair module circuit includes a load resistor RL1 and a load resistor RL2, a PMOS transistor MP1 is provided between the power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2, the source of the PMOS transistor MP1 is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor MP1 is connected to the load resistor RL1 and the load resistor RL2 to form a junction 020; The end of the load resistor RL2 close to the driven element 10 is the output end of the output driving sub-circuit 02. The end of the load resistor RL2 close to the driven element 10 is also connected to one end of a load resistor Rf. The end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier OP1 (in Figure 2 In the embodiment shown, the first input terminal is a reverse input terminal); The end of the load resistor RL1 close to the PMOS transistor MP1 is also connected to one end of a load resistor Rref, and the end of the load resistor Rref away from the load resistor RL1 is connected to the second input end of the first operational amplifier OP1 (in Figure 2 In the embodiment shown, the second input terminal is a positive input terminal), one end of the load resistor Rref away from the load resistor RL1 is connected to the first current source 031; The output terminal of the first operational amplifier OP1 is connected to the gate of the PMOS transistor MP1.

[0032] It should be understood that the driving circuit should also include a capacitor Cf and a capacitor Cvdd. One end of the capacitor Cf is grounded, and the end of the capacitor Cf away from the ground direction is connected to the first input terminal of the first operational amplifier OP1 (in Figure 2In the embodiment shown, the first input terminal is a reverse input terminal) and is connected to an end of the load resistor Rf away from the load resistor RL2. One end of the capacitor Cvdd is grounded, and an end of the capacitor Cvdd away from the ground direction is connected to an end of the load resistor RL2 close to the drain of the PMOS transistor MP1, an end of the load resistor RL1 close to the drain of the PMOS transistor MP1, the drain of the PMOS transistor MP1, and an end of the load resistor Rref away from the first current source 031.

[0033] In this way, the present invention uses the resistive load and the bias current control subcircuit 01 to modulate the drive current. The advantage of this solution is that the resistive load can effectively achieve output impedance matching, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the load of the driving stage, which is beneficial to improving the circuit bandwidth and achieving a larger gain bandwidth performance. The modulation current control subcircuit 03 implemented by the feedback loop formed by the operational amplifier, the subcircuit cooperates with the output stage to form a current clamping circuit to ensure the stability of the output DC current, so that the modulation current and the bias current can be adjusted separately, and it is ensured that the bias current will not flow into the output stage to cause the bias current to be inconsistent with expectations. Specifically, the proportional relationship between the load resistor Rref and the load resistor RL2 can be set so that the voltages applied to the positive input terminal and the reverse input terminal of the first operational amplifier OP1 are consistent, thereby configuring the first operational amplifier OP1 to output the required target value level. This solution requires that both ends of the operational amplifier are low-frequency signals, so it is necessary to obtain the DC voltage of the output node through a larger RC filter. The common-mode end of the resistor as the power supply end of the driving stage requires a larger capacitor to ensure that the node is an ideal high-frequency signal ground. When the chip power supply voltage is limited, PMOS is used as a voltage-stabilized power supply power tube to make the node a high-resistance node. Therefore, attention should be paid to the zero-pole position of the loop during design to maintain the stability of the loop. Further, the first operational amplifier OP1 is used to control the PMOS transistor MP1, and finally the required target voltage is obtained at the intersection 020, so that the bias current will not flow into the output stage, causing the bias current to be inconsistent with expectations, thereby reducing the bias circuit requirements, and can reduce the size requirements of the current mirror made of PMOS in the bias circuit by about half, equivalent to reducing the parasitic capacitance by half, which can effectively expand the bandwidth, while keeping the currents of the two branches of the differential pair module circuit equal.

[0034] For example, the driven element 10 is a VCSEL, the load resistance RL1=RL2=RL, and the reference load resistance Rref=RL*K. The DC value vfb of the VCSEL anode voltage VO is obtained through Rf and Cf, and vfb=VO. Assume that the voltage at the intersection 020 is RVDD, the current of the first current source 031 is Imod_ref, the current of the second current source 021 is Imod_tail, and Imod_tail=2K*Imod_ref, and the current source 011 of the bias current control subcircuit is Ibias. In the static operating point analysis, it can be found that the voltage vref=RVDD-Rref*Imod_ref, vfb=RVDD–RL2*I(RL2) applied to the load resistance Rref, and vref=vfb is clamped by the first operational amplifier OP1, so that I(RL2)=K*imod_ref can be achieved. Since the output equivalent resistance of Q2 is much larger than the internal resistance of VCSEL, the Ibias current will mainly flow to VCSEL, so the collector terminal current of Q2 IC(Q2)=Ibias+I(RL1)–Ibias(VCSEL)≈I(RL2)=K*imod_ref. Under the condition that the base current of Q1 and Q2 is much smaller than the collector current, IC(Q1)≈Imod_tail–IC(Q2)=IC(Q2). Therefore, the output stage can be guaranteed to be in a current balance state, thereby ensuring that the high and low voltage amplification gains of the input signal are basically consistent, thereby maintaining the performance of the rising and falling edges of the output eye diagram. The RVDD voltage is determined by the set operating current value, RVDD=VO+V(RL2)=VCC–VDS(MP1), where VCC is the power supply voltage, so there needs to be enough VCC voltage to ensure that the MP1 tube can work normally in all working scenarios. Cvdd needs to be connected to the intersection 020 to ensure that this is an ideal differential signal ground node that can absorb high-frequency jitter signals. For a VCSEL with an equivalent internal resistance of Rv, this structure can realize VCSEL modulation current amplitude IMOD=RL / (RL+Rv)*Imod_tail=2*K*RL / (RL+Rv)*Imod_ref, thereby IMOD is independent of the bias current control subcircuit current source 011. Adjusting imod_ref by digital configuration can realize adjustable IMOD.

[0035] For details, please refer to Figure 3 , Figure 3 The schematic diagram of the circuit principle of the bias current control subcircuit of the driving circuit provided by the first embodiment of the present invention. Figure 3 As shown, the bias current control subcircuit 01 includes a current mirror module circuit. For further information, please refer to Figure 4 , Figure 4The schematic diagram of the circuit principle of the bias current control subcircuit of the driving circuit provided by the second embodiment of the present invention. Figure 4 As shown, the difference between the bias current control subcircuit of the driving circuit provided by the second embodiment and the bias current control subcircuit of the driving circuit provided by the first embodiment is that the current mirror module circuit includes a cascade structure circuit. Both the current mirror module circuit and the cascade structure circuit can be set with reference to the prior art and will not be described in detail here.

[0036] For further information, please refer to Figure 5 , Figure 5 The schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the first embodiment of the present invention is shown in FIG. Figure 5 As shown, the differential pair module circuit also includes a second current source 021, a transistor Q1, and a transistor Q2; one end of the second current source 021 is grounded, and the end of the second current source 021 away from the ground direction is connected to the emitter of the transistor Q1, and the end of the second current source 021 away from the ground direction is connected to the emitter of the transistor Q2; the collector of the transistor Q1 is connected to the end of the load resistor RL1 away from the PMOS transistor MP1, and the collector of the transistor Q2 is connected to the end of the load resistor RL2 away from the PMOS transistor MP1. With such a configuration, the differential pair module circuit essentially forms a CML structure (Current Mode Logic, current mode logic), which has better gain bandwidth performance and is easier to control output load matching.

[0037] There are many optimization solutions for the CML structure, for example, please refer to Figure 6 , Figure 6 The schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the second embodiment of the present invention is shown in FIG. Figure 6 As shown, the difference between the output driving subcircuit of the driving circuit provided by the second embodiment and the output driving subcircuit of the driving circuit provided by the first embodiment is that a transistor Q3 is provided between the transistor Q1 and the load resistor RL1, and a transistor Q4 is provided between the transistor Q2 and the load resistor RL2; the collector of the transistor Q3 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the emitter of the transistor Q3 is connected to the collector of the transistor Q1; the collector of the transistor Q4 is connected to the end of the load resistor RL2 away from the PMOS transistor MP1, and the emitter of the transistor Q4 is connected to the collector of the transistor Q2. Such a setting essentially adds a cascade level to the CML structure, which has advantages such as higher output impedance and output isolation.

[0038] For further information, please refer to Figure 7 , Figure 7 The schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the third embodiment of the present invention is shown in FIG. Figure 7 As shown, the output driving subcircuit of the driving circuit provided by the third embodiment is different from the output driving subcircuit of the driving circuit provided by the second embodiment and the first embodiment in that it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q6; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor MP1 and connected to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and connected to the collector of the transistor Q2. Such a setting essentially constitutes an FFE structure, and by adjusting the polarity, delay, and amplitude of the second signal, a stronger balancing function can be achieved, bandwidth expansion can be achieved, and nonlinear characteristics of driven elements such as VCSEL can be compensated, so as to ensure the performance of the VCSEL output signal.

[0039] For further information, please refer to Figure 8 , Figure 8 The schematic diagram of the circuit principle of the first current source and the second current source of the driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 8As shown, the first current source includes a second operational amplifier OP2, a transistor QB1 and an emitter resistor RE2, and the second current source includes a third operational amplifier OP3, a transistor QB2 and an emitter resistor RE3; one end of the emitter resistor RE2 is grounded, and the end of the emitter resistor RE2 away from the ground direction is connected to the emitter of the transistor QB1 and the reverse input terminal of the second operational amplifier OP2; one end of the emitter resistor RE3 is grounded, and the end of the emitter resistor RE3 away from the ground direction is connected to the emitter of the transistor QB2 and the reverse input terminal of the third operational amplifier; the collector of the transistor QB1 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output terminal of the second operational amplifier OP2; the collector of the transistor QB2 is connected to the emitter of the transistor Q1 and to the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier OP3; the second operational amplifier and the positive input terminal of the third operational amplifier OP3 are connected to the first temperature compensation current source. The first temperature-compensated current source includes a compensation current source unit 051 with a temperature coefficient and a compensation current source unit 052 without a temperature coefficient, and the temperature compensation of the entire circuit can be realized by configuring the two. The current ratio relationship between the first current source and the second current source can be realized by configuring the resistance values ​​of the emitter resistors RE1, RE2, and RE3, so as to serve the first operational amplifier OP1.

[0040] For further information, please refer to Fig. 9 , Fig. 9 The schematic diagram of the circuit principle of the first current source, the second current source and the third current source of the driving circuit provided by an embodiment of the present invention is shown in FIG. Fig. 9As shown, it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and one end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and one end of the third current source away from the ground direction is connected to the emitter of the transistor Q5; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2; the third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; the first current source also includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; one end of the emitter resistor RE4 The end of the emitter resistor RE4 is connected to the ground, and the end away from the ground direction is connected to the emitter of the transistor QB2 and the reverse input terminal of the fourth operational amplifier; one end of the emitter resistor RE5 is connected to the ground, and the end away from the ground direction is connected to the emitter of the transistor QB4 and the reverse input terminal of the fifth operational amplifier; the collector of the transistor QB3 is connected to the emitter of the transistor Q5 and the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier; the collector of the transistor QB4 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output terminal of the fifth operational amplifier; the positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature compensation current source. The second temperature compensation current source includes a compensation current source unit 061 with a temperature coefficient and a compensation current source unit 062 without a temperature coefficient. The temperature compensation of the entire circuit can be achieved by configuring the two. Fig. 9 The illustrated embodiment is particularly suitable for adapting a CML structure with a FFE structure, essentially proportionally increasing the post tap tail current.

[0041] The implementation principle of temperature compensation is Ibias=k1*(a*Iptat1+(1-a)*Iflat1), Imod_ref=k2*(a*Iptat2+(1-a)*Iflat2), where Iptat is the current that is positively correlated with temperature, and Iflat is the current that is independent of temperature. a is the proportion of the positive temperature coefficient current in the reference current. Using digital registers to control the size of a, k1, and k2 can achieve stable light emission of VCSEL at different temperatures.

[0042] For further information, please refer to Fig.10 , Fig.10 FIG. 1 is a schematic diagram of the circuit principle of a driving circuit provided by the second embodiment of the present invention. Fig.10As shown, it also includes several inductors 100, which are used to weaken the parasitic capacitance in the circuit. Fig.10 In the embodiment of the second driving circuit, the CML structure may include both a cascade structure and a FFE structure, which will not be described in detail here.

[0043] It should be noted that all the transistors described in this application may be NPN transistors or NMOS transistors.

[0044] The present invention also provides a vertical cavity surface emitting laser system, including a driving circuit as described in any of the above, and the driven element 10 is a vertical cavity surface emitting laser. Since the vertical cavity surface emitting laser system includes the driving circuit, the vertical cavity surface emitting laser system uses the resistive load and the bias current control subcircuit to modulate the driving current at the same time. The advantage of this solution is that the output impedance matching can be effectively achieved through the resistive load, and the size of the current mirror load tube of the bias current control subcircuit can be reduced, thereby reducing the load of the driving stage, which is beneficial to improving the circuit bandwidth and achieving a larger gain bandwidth performance. The modulation current control circuit implemented by the feedback loop composed of an operational amplifier, the circuit cooperates with the output stage to form a current clamping circuit to ensure the stability of the output DC current, so that the modulation current and the bias current are adjustable respectively, so that the bias current is reversed from the output end of the output driving subcircuit as a high-resistance environment, ensuring that the bias current will not flow into the output stage, causing the bias current to be inconsistent with expectations.

[0045] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0046] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0047] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A driving circuit, characterized in that: It includes a bias current control subcircuit and an output drive subcircuit; The input end of the bias current control subcircuit is connected to a power supply, and the output end of the bias current control subcircuit is connected to the output end of the output drive subcircuit and a driven element; The output driving sub-circuit includes a differential pair module circuit, the differential pair module circuit includes a load resistor RL1 and a load resistor RL2, a PMOS transistor is provided between a power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2, a source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and a drain of the PMOS transistor is connected to the load resistor RL1 and the load resistor RL2 to form a junction; One end of the load resistor RL2 close to the driven element is the output end of the output drive sub-circuit, and one end of the load resistor RL2 close to the driven element is also connected to one end of a load resistor Rf, and one end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; One end of the load resistor RL1 close to the PMOS transistor is also connected to one end of a load resistor Rref, one end of the load resistor Rref away from the load resistor RL1 is connected to the second input terminal of the first operational amplifier, and one end of the load resistor Rref away from the load resistor RL1 is connected to a first current source; The output terminal of the first operational amplifier is connected to the gate of the PMOS transistor.

2. The driving circuit according to claim 1, characterized in that: The bias current control subcircuit includes a current mirror module circuit.

3. The driving circuit according to claim 2, characterized in that: The current mirror module circuit includes a cascade structure circuit.

4. The driving circuit according to claim 1, wherein: The differential pair module circuit also includes a second current source, a transistor Q1, and a transistor Q2; One end of the second current source is grounded, and one end of the second current source away from the ground direction is connected to the emitter of the transistor Q1 and to the emitter of the transistor Q2; The collector of the transistor Q1 is connected to an end of the load resistor RL1 away from the PMOS transistor, and the collector of the transistor Q2 is connected to an end of the load resistor RL2 away from the PMOS transistor.

5. The driving circuit according to claim 4, characterized in that: A transistor Q3 is provided between the transistor Q1 and the load resistor RL1, and a transistor Q4 is provided between the transistor Q2 and the load resistor RL2; The collector of the transistor Q3 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the emitter of the transistor Q3 is connected to the collector of the transistor Q1; The collector of the transistor Q4 is connected to the end of the load resistor RL2 away from the PMOS transistor, and the emitter of the transistor Q4 is connected to the collector of the transistor Q2.

6. The driving circuit according to claim 4 or 5, characterized in that: Also includes a transistor Q5, a transistor Q6 and a third current source; One end of the third current source is grounded, and one end of the third current source away from the ground direction is connected to the emitter of the transistor Q5 and connected to the emitter of the transistor Q6; The collector of the transistor Q5 is connected to an end of the load resistor RL1 away from the PMOS transistor and is connected to the collector of the transistor Q1; The collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and is connected to the collector of the transistor Q2.

7. The driving circuit according to claim 4, characterized in that: The first current source includes a second operational amplifier, a transistor QB1 and an emitter resistor RE2, and the second current source includes a third operational amplifier, a transistor QB2 and an emitter resistor RE3; One end of the emitter resistor RE2 is grounded, and one end of the emitter resistor RE2 away from the grounding direction is connected to the emitter of the transistor QB1 and the inverting input end of the second operational amplifier; One end of the emitter resistor RE3 is grounded, and one end of the emitter resistor RE3 away from the ground direction is connected to the emitter of the transistor QB2 and the inverting input end of the third operational amplifier; The collector of the transistor QB1 is connected to an end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output end of the second operational amplifier; The collector of the transistor QB2 is connected to the emitter of the transistor Q1 and to the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier; The positive input terminals of the second operational amplifier and the third operational amplifier are connected to a first temperature compensation current source.

8. The driving circuit according to claim 7, characterized in that: Also includes a transistor Q5, a transistor Q6 and a third current source; One end of the third current source is grounded, and one end of the third current source away from the ground direction is connected to the emitter of the transistor Q5 and is connected to the emitter of the transistor Q5; The collector of the transistor Q5 is connected to an end of the load resistor RL1 away from the PMOS transistor and is connected to the collector of the transistor Q1; The collector of the transistor Q6 is connected to an end of the load resistor RL2 away from the PMOS transistor and is connected to the collector of the transistor Q2; The third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; The first current source also includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; One end of the emitter resistor RE4 is grounded, and one end of the emitter resistor RE4 away from the ground direction is connected to the emitter of the transistor QB2 and the inverting input terminal of the fourth operational amplifier; One end of the emitter resistor RE5 is grounded, and one end of the emitter resistor RE5 away from the ground direction is connected to the emitter of the transistor QB4 and the inverting input terminal of the fifth operational amplifier; The collector of the transistor QB3 is connected to the emitter of the transistor Q5 and to the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier; The collector of the transistor QB4 is connected to an end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output end of the fifth operational amplifier; The positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature compensation current source.

9. The driving circuit according to claim 1, characterized in that: Also included are several inductors, which are used to weaken the parasitic capacitance in the circuit.

10. A vertical cavity surface emitting laser system, characterized in that: The driving circuit comprises the driving circuit as claimed in any one of claims 1 to 9, wherein the driven element is a vertical cavity surface emitting laser.

Images