Method and equipment for acquiring and processing error address information

Abstract

The embodiment of the invention discloses a method and equipment for obtaining and processing error address information. In response to a data reading operation detected by the user interaction interface, reading target test data of the target test object, the target test data being error address test data corresponding to a specified address range in error address test data of the target test object; based on the target test data, displaying a first type of view in a view window of the user interaction interface, the first type of view being used for indicating test result information of different addresses in a specified address range; and in response to a view switching operation detected by the user interaction interface, displaying a second type view in a view window of the user interaction interface based on the target test data, the second type view being used for indicating position distribution information of error addresses in the specified address range on the target test object. According to the embodiment of the invention, the acquisition and analysis efficiency of the error address information of the target test object can be improved.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a method and device for obtaining and processing error address information. Background Art

[0002] With the development of electronic technology, the speed of electronic equipment replacement is getting faster and faster. At the same time, the demand for memory chips is also increasing, and higher requirements are also put forward for the storage space of memory chips. The design complexity of chips is getting higher and higher, and the requirements for memory chip testing equipment are also getting higher and higher. At present, the test of memory chips not only requires the input and output test of conventional digital chips, but also the test of the storage address of the internal space of the memory chip to detect whether there is a damaged error address bit in the storage space, so as to facilitate the later repair of the damaged storage address and analyze the cause of the failure of the chip storage address. Summary of the invention

[0003] The embodiments of the present disclosure provide a method and device for obtaining and processing error address information, which are beneficial to improving the efficiency of obtaining and analyzing error address information of a target test object.

[0004] In one aspect of an embodiment of the present disclosure, a method for obtaining and processing error address information is provided, including:

[0005] In response to the user interaction interface detecting a data read operation, reading target test data of a target test object, the target test data being error address test data corresponding to a specified address range in error address test data of the target test object;

[0006] Based on the target test data, displaying a first type of view in a view window of the user interaction interface, wherein the first type of view is used to indicate test result information of different addresses within the specified address range;

[0007] In response to the user interaction interface detecting a view switching operation, a second type of view is displayed in the view window of the user interaction interface based on the target test data, and the second type of view is used to indicate the location distribution information of the error addresses in the specified address range on the target test object.

[0008] Another aspect of the present disclosure provides an electronic device, including:

[0009] Memory for storing computer programs;

[0010] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure is implemented.

[0011] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure is implemented.

[0012] Another aspect of the embodiments of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure.

[0013] In an embodiment of the present disclosure, in response to a data reading operation being detected in a user interaction interface, target test data of a specified address range corresponding to a target test object is read, and based on the target test data, a first type of view is displayed in a view window of the user interaction interface, and a user can also switch views through the user interaction interface. In response to a view switching operation being detected in the user interaction interface, the view in the view window can be switched to a second type of view, that is, a user can select different types of views in the user interaction interface to display error address information corresponding to the target test data, and can choose to view a first type of view for indicating the test results of each address within a specified address range, and a second type of view for indicating the actual position distribution of error addresses in a specified address range on the target test object, respectively, so that the user can analyze the error address information of the target test object through different types of views. By providing different types of views, the user can intuitively view a variety of error address information, thereby improving information acquisition efficiency, and facilitating subsequent rapid positioning of the error address of the target test object and rapid analysis of the cause of the error.

[0014] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of the structure of a testing device provided for an exemplary embodiment of the present disclosure;

[0018] Figure 2 A flowchart of a method for obtaining and processing error address information provided by an exemplary embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of an interface of a first view window provided for an exemplary embodiment of the present disclosure;

[0020] Figure 4A schematic diagram of an interface of a second view window provided for an exemplary embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of an interface of a second view window provided for another exemplary embodiment of the present disclosure;

[0022] Figure 6 A flowchart of a process of displaying a first type of view provided for an exemplary embodiment of the present disclosure;

[0023] Figure 7 is a flowchart of a layer overlay process of a logic matrix bitmap provided by an exemplary embodiment of the present disclosure;

[0024] Figure 8 is a schematic diagram of an interface providing a physical matrix view according to an exemplary embodiment of the present disclosure;

[0025] Fig. 9 is a flow chart of a layer overlay process of a physical matrix bitmap provided by an exemplary embodiment of the present disclosure;

[0026] Fig.10 is a structural diagram of an apparatus for obtaining and processing error address information provided by an exemplary embodiment of the present disclosure;

[0027] Fig.11 It is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0029] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0030] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0031] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0032] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0033] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0034] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0036] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0037] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0038] The disclosed embodiments can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0039] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0040] In an embodiment of the present disclosure, a method for obtaining and processing error address information is provided, which is used to display the error address information indicated by error address test data obtained by a test device performing an error address test on the storage space of a target test object on a user interaction interface in different types of views, so that the user can quickly view and analyze the error address information of the storage space of the target test object through different types of views.

[0041] The error address information acquisition and processing method provided in the embodiment of the present disclosure can be used in the host computer of the test equipment, and specifically can be used in the error address information acquisition and processing device in the host computer. The test equipment can be used to perform semiconductor testing on the device under test (DUT), wherein the DUT may include a wafer, a chip, etc. In the present disclosure, the device under test is also referred to as a target test object. Figure 1 As shown, the test equipment includes a host computer 10 and a target slave computer 20 .

[0042] The host computer 10 runs an error address information acquisition processing device 101, which is used to read the error address test data of the target test object from the target lower computer 20, and display the error address information corresponding to the acquired error address test data in different types of views on the user interaction interface. The target lower computer 20 is used to execute the test process for the target test object, perform an error address test on the target test object, and store the error address test data obtained from the test. When the host computer 10 sends a data read request to the target lower computer 20, the target lower computer 20 can provide the corresponding error address test data to the host computer 10 according to the data read request.

[0043] Figure 2 A flowchart of a method for obtaining and processing error address information provided by an exemplary embodiment of the present disclosure, the method is used for the host computer 10 of the test device as described above, and is specifically used for the error address information obtaining and processing device 101 of the host computer 10, such as Figure 2 As shown, the method of this embodiment includes:

[0044] Step 210 , in response to the user interaction interface detecting a data read operation, read target test data of the target test object, where the target test data is error address test data corresponding to a specified address range in error address test data of the target test object.

[0045] The user interaction interface is an interface in the error address information acquisition and processing device with which the user can interact. The user interaction interface is used to display the error address information corresponding to the read error address test data.

[0046] In one possible implementation, a trigger control for triggering a data read request is provided in the user interaction interface, and the user interaction interface determines that a data read operation is detected in response to a trigger operation on the trigger control. When the data read operation is detected in the user interaction interface, the host computer reads the target test data of the target test object.

[0047] In one possible implementation, a user may configure parameters in a user interaction interface, configure parameters for reading error address test data corresponding to a specified address range, and after detecting a data read operation, a data read request may be generated based on the configured parameters, the data read request including the configured specified address range, the upper computer sends a data read request to the target lower computer, and the target lower computer provides the error address test data corresponding to the specified address range to the upper computer.

[0048] Optionally, the target lower computer may perform error address tests on multiple target test objects and store error address test data corresponding to the multiple target test objects. In one example, the target lower computer stores error address test data of a specified address range corresponding to multiple target test objects, and in response to a data read operation being detected by the user interaction interface, reads the target test data of the multiple target test objects.

[0049] Step 220: Based on the target test data, a first type of view is displayed in a view window of the user interaction interface, where the first type of view is used to indicate test result information of different addresses within a specified address range.

[0050] In one possible implementation, the first type of view is a view generated based on error address test data corresponding to the logical address of the target test object, the error address information indicated is the error address information corresponding to the logical address of the target test object, and the target lower computer stores error address test data corresponding to the logical address of the target test object.

[0051] Optionally, the first type of view includes a view for indicating test results corresponding to all logical addresses included in a specified address range, or a view including test results corresponding to local logical addresses in a specified address range.

[0052] In a possible implementation, for the above-mentioned multiple target test objects, the first type of view may include a view for displaying test results corresponding to a specified address range of the multiple target test objects.

[0053] Step 230, in response to the user interaction interface detecting a view switching operation, based on the target test data, displaying a second type of view in the view window of the user interaction interface, the second type of view being used to indicate location distribution information of error addresses in a specified address range on the target test object.

[0054] The user interaction interface also provides a view switching control for switching views. In response to detecting a trigger operation on the view switching control, the user interaction interface determines that a view switching operation is detected and can switch the first type of view displayed in the view window to a second type of view.

[0055] In a possible implementation, the second type of view is a view generated based on error address data corresponding to the physical address of the target test object, and is used to indicate the actual physical location distribution of error addresses in a specified address range of the target test object on the target test object.

[0056] In one possible implementation, after the upper computer obtains the target test data, it can convert the logical address corresponding to the target test data to obtain the error address data corresponding to the physical address. In another possible implementation, the lower computer can also convert the target test data, and the upper computer reads the error address data corresponding to the converted physical address from the lower computer, and generates the second type of view based on the error address data corresponding to the physical address.

[0057] In an embodiment of the present disclosure, in response to a data reading operation being detected in a user interaction interface, target test data in a specified address range corresponding to a target test object is read, and based on the target test data, a first type of view is displayed in a view window of the user interaction interface, and a user can also switch views through the user interaction interface. In response to the view switching operation being detected in the user interaction interface, the view in the view window can be switched to a second type of view, that is, a user can select different types of views in the user interaction interface to display error address information corresponding to the target test data, and can choose to view a first type of view for indicating test results of different addresses within a specified address range, and a second type of view for indicating the actual position distribution of each error address in the specified address range on the target test object, respectively, so that the user can analyze the error address information of the target test object through different types of views, and by providing different types of views, the user can intuitively view a variety of error address information, which is conducive to the subsequent rapid location of the error address of the target test object and the rapid analysis of the cause of the error.

[0058] Optionally, the first type of view includes at least one of a test status view, a logic matrix bitmap, and an error address list.

[0059] The test status view is used to indicate the test status information of the specified address range. The test status includes Pass / Fail status, where the Pass status indicates that the address test passed, and the Fail status indicates that the address test failed, and also indicates that the tested address is an incorrect address. The test status view can represent the test results corresponding to the specified address range as a whole. When the target test data indicates that there is no address test result in the Fail status among all the address test results in the specified address range, the test status indicated by the test status view is the Pass status. When the target test data indicates that there is an address test result in the Fail status among all the address test results in the specified address range, the test status indicated by the test status view is the Fail status.

[0060] In a possible implementation, in response to a request to view the test status view, the test status view corresponding to the target test data is displayed in a first view window of the user interaction interface.

[0061] A status view viewing control for viewing the test status view may be provided in the user interaction interface. In a possible implementation, in response to a trigger operation on the status view viewing control, it is determined that a viewing request for the test status view is received, and the test status view corresponding to the target test data is displayed in the first view window of the user interaction interface. Optionally, the test status view includes an object identifier representing the target test object, and the identifier display form may be determined according to the target test data of the target test object. When the target test data indicates that the test status of the target test object corresponding to the specified address range is the Pass state, the identifier display form of the object identifier is the first display form. When the target test data indicates that the test status of the target test object corresponding to the specified address range is the Fail state, the identifier display form of the object identifier is the second display form. The first display form is different from the second display form, and may specifically include at least one of different identifier colors, different identifier shapes, and different identifier corresponding labels.

[0062] Optionally, the target test object includes multiple digital input and output pins (DQpin), and the target test data includes test data corresponding to the specified address range of each digital input and output pin. Each digital input and output pin has the same logical address range. When reading the error address test data of the specified address range corresponding to the target test object from the lower computer, the error address test data of the specified address range of each of the multiple digital input and output pins included in the target test object can be read. When the test status view corresponding to the target test data is displayed in the first view window of the user interaction interface, the test status view for indicating the test status of each digital input and output pin can be displayed in the first view window of the user interaction interface. The test state corresponding to each digital input / output pin can be determined according to the test data of the specified address range corresponding to each digital input / output pin. In one example, when the test data of the specified address range corresponding to a digital input / output pin indicates that there is an address in the Fail state in the specified address range corresponding to the digital input / output pin, the test state of the digital input / output pin is determined to be the Fail state. When the test data of the specified address range corresponding to the digital input / output pin indicates that there is no address in the Fail state (i.e., all are Pass state) in the specified address range corresponding to the digital input / output pin, the test state of the digital input / output pin is determined to be the Pass state. When the state of all digital input / output pins included in a target test object is the Pass state, the test state of the target test object is the Pass state. When there is a pin in the Fail state among the digital input / output pins of the target test object, the test state of the target test object is the Fail state. In a possible implementation manner, the pin identifiers corresponding to each digital input / output pin are displayed in the test state view, and the display form of each pin identifier can be determined according to the test state of the corresponding digital input / output pin. In one example, when all address test results of the specified address range of the digital input / output pin are in Pass state, the display form of the pin identifier is the first display form; when all address test results of the specified address range of the digital input / output pin are in Fail state, the display form of the pin identifier is the second display form.

[0063] In a possible implementation, an object identifier for indicating the test status of the target test object and a pin identifier for indicating the test status of each digital input / output pin included in the target test object may be displayed simultaneously in the test status view.

[0064] In a possible implementation, when target test data of multiple target test objects are read, object identifiers corresponding to the multiple target test objects may be displayed in the test status view. In response to a selection operation on an object identifier, multiple pin identifiers corresponding to multiple digital input and output pins of the target test object corresponding to the object identifier may be displayed in the test status view. Figure 3 As shown, the test status view displays object identifiers corresponding to test objects 201, 202, 203 and 204, which are respectively used to indicate the test status of test objects 201, 202, 203 and 204. You can also choose to display pin identifiers of multiple digital input and output pins included in the test object 201 (including pin identifiers of DQL0-DQL7, pin identifiers of DQU0-DQU7) to respectively indicate the test status of different digital input and output pins in the test object 201.

[0065] The logic matrix bitmap is a two-dimensional matrix bitmap used to indicate the test results corresponding to different addresses within a specified address range. In a possible implementation, in response to a request to view the logic matrix bitmap, the logic matrix bitmap corresponding to the target test data is displayed in the second view window of the user interaction interface. A matrix bitmap viewing control for viewing the logic matrix bitmap may be provided in the user interaction interface. In a possible implementation, in response to a trigger operation on the matrix bitmap viewing control, it is determined that a request to view the logic matrix bitmap is received, and the logic matrix bitmap corresponding to the target test data is displayed in the second view window of the user interaction interface.

[0066] Optionally, a logic matrix bitmap corresponding to each digital input / output pin is generated according to the test data of each digital input / output pin, and the logic matrix bitmap corresponding to the target test object includes the logic matrix bitmap corresponding to each digital input / output pin. Different matrix units in the logic matrix bitmap correspond to different logic addresses, and the display state of the corresponding matrix unit can be determined according to the test result corresponding to the logic address. The display state of the matrix unit corresponding to the logic address with a test result of Pass state is different from the display state of the matrix unit corresponding to the logic address with a test result of Fail state. Exemplarily, different test results can be indicated by matrix units of different colors.

[0067] Optionally, the logic matrix bitmap includes at least one of a thumbnail logic matrix bitmap and a detailed logic matrix bitmap. A matrix unit in the thumbnail logic matrix bitmap corresponds to a logic address range, and a matrix unit in the detailed logic matrix bitmap corresponds to a logic address. In a possible implementation, the thumbnail logic matrix bitmap corresponding to each digital input / output pin can be displayed in the second view window, and / or, in response to the selection operation of the target pin, the detailed logic matrix bitmap corresponding to the target pin can be displayed in the second view window. That is, the thumbnail matrix bitmaps corresponding to all digital input / output pins can be displayed in the second view window to quickly view the test results of the specified address range of each digital input / output pin, and the detailed logic matrix bitmap of a selected digital input / output pin can also be displayed in the second view window to view the detailed test results of each logic address in the specified address range.

[0068] In a possible implementation, in response to a request to view the logic matrix view, the thumbnail logic matrix bitmap corresponding to each digital input / output pin is first displayed in the second view window, and in response to a selection operation on the thumbnail logic matrix bitmap corresponding to a digital input / output pin, the digital input / output pin corresponding to the selected thumbnail logic matrix bitmap is determined as the target pin, that is, it is determined that the selection operation on the target pin is received, and the detailed logic matrix bitmap of the target pin is displayed in the second view window. Schematically, as shown in FIG. Figure 4 As shown, the abbreviated logic matrix bitmap corresponding to each digital input and output pin of the test object 201 is displayed in the second view window. When a selection operation for DQL0 is received, as shown in FIG. Figure 5 As shown, the detailed logic matrix bitmap corresponding to the pin DQL0 of the test object 201 is displayed in the second view window.

[0069] In a possible implementation, a detailed logic matrix bitmap and a thumbnail logic matrix bitmap corresponding to the target pin may be displayed in the second view window at the same time. Optionally, the detailed logic matrix bitmap corresponding to the target pin is displayed in a first area of ​​the second view window, and the thumbnail logic matrix bitmap corresponding to the target pin is displayed in a second area of ​​the second view window, wherein the area of ​​the first area is larger than the area of ​​the second area.

[0070] In one example, the detailed logic matrix bitmap in the first area corresponds to the matrix bitmap area of ​​the thumbnail logic matrix bitmap in the second area. In response to the address range selection operation on the thumbnail logic matrix bitmap, the detailed logic matrix bitmap displayed in the first area is updated based on the selected address range. Optionally, the address range selection operation on the thumbnail logic matrix bitmap may be a box selection operation on a local matrix bitmap area in the thumbnail logic matrix bitmap, and the detailed logic matrix bitmap displayed in the first area is a logic matrix bitmap after the enlargement of the boxed local matrix bitmap area. In response to the box selection operation on the local matrix bitmap area in the thumbnail logic matrix bitmap, the corresponding selected address range is determined according to the boxed local matrix bitmap, and the detailed logic matrix bitmap displayed in the first area is updated based on the test data corresponding to the selected address range. In a possible implementation, in response to the dragging operation on the detailed logic matrix bitmap, the selected address range in the thumbnail matrix bitmap is updated based on the dragged address range. Optionally, the user can drag the detailed logic matrix bitmap displayed in the first area. When a drag operation on the detailed logic matrix bitmap is received, the detailed logic matrix bitmap displayed in the first area is updated based on the drag operation, and based on the address range corresponding to the updated detailed logic matrix bitmap, the selected local matrix bitmap area in the thumbnail logic matrix bitmap in the second area is updated.

[0071] Optionally, a horizontal drag axis and a vertical drag axis are set in the first area. In response to the drag operation of the horizontal drag axis and / or the vertical drag axis, the detailed logic matrix bitmap displayed in the first area and the local matrix bitmap area selected in the thumbnail logic matrix bitmap in the second area are updated.

[0072] In a possible implementation, the second view window further includes a third area for displaying detailed address information. An address information window is displayed in the third area of ​​the second view window, and the address information window displays address range information corresponding to the detailed logic matrix bitmap currently displayed in the first area. Specifically, the address information window may display a start address item and an end address item, wherein the start address item displays the start address of the address range corresponding to the detailed logic matrix bitmap currently displayed, and the end address item displays the end address of the address range corresponding to the detailed logic matrix bitmap currently displayed, so that the user can view specific address range information.

[0073] Optionally, in response to an update operation on the address range information in the address information window, the detailed logic matrix bitmap displayed in the first region is updated based on the updated address range. That is, the user can change the address range in the address information window, and in response to an update operation on the address range information, the updated address range can be obtained, and the detailed logic matrix bitmap displayed in the first region is updated based on the updated address range.

[0074] Optionally, in response to a drag operation on the detailed logic matrix bitmap, the address range information in the address information window is updated based on the address range information after the drag. When a drag operation on the detailed logic matrix bitmap is received, the address range information in the address information window can be updated based on the address range information after the drag, so that the user can intuitively view the updated address range.

[0075] The address range in the address information window corresponds to the address range selected in the thumbnail logic matrix bitmap in the second region, that is, the address range corresponding to the local matrix bitmap region selected by the frame in the thumbnail logic matrix bitmap. In response to the address range update operation on the thumbnail logic matrix bitmap, that is, updating the selected local matrix bitmap region, the address range information in the address information window in the third region is updated.

[0076] Indicatively, Figure 5 As shown, the first area 501 displays a detailed logic matrix bitmap of the pin DQL0 of the test object 201, which corresponds to the thumbnail logic matrix bitmap in the second area 502. The third area 503 displays an address information window, which can be used to display the address range information corresponding to the logic matrix bitmap, and can also be used to configure and select the address range information to be viewed. By updating the start address and the end address, the address range to be viewed can be updated.

[0077] The error address list is used to indicate the error addresses within the specified address range. Optionally, the error address list may include detailed logical error addresses within the specified address range.

[0078] In a possible implementation, in response to a request to view the error address list, the error address list corresponding to the target test data is displayed in a third view window of the user interaction interface.

[0079] A list viewing control for viewing an error address list may be provided in the user interaction interface. In one possible implementation, in response to a triggering operation on the list viewing control, it is determined that a request to view the error address list has been received, and the error address list corresponding to the target test data is displayed in a third view window of the user interaction interface.

[0080] The target test data includes test data of a specified address range of each digital input / output pin. In a possible implementation, a user can choose to view the error address of a target address range of a digital input / output pin belonging to the specified address range, that is, in response to the selection operation of the target pin and the target address range, the error address list corresponding to the target address range of the target pin is displayed in the third view window. After receiving the selection operation of the target pin and the target address range, the test data corresponding to the target address range of the target pin can be obtained, and an error address list is generated based on the test data of the target address range, and the error address list lists all logical error addresses (that is, logical addresses with a test result of Fail) included in the target address range of the target pin.

[0081] In combination with the above embodiment, in response to a request to view the error address list, the target pin selected by the user when the detailed logic matrix bitmap is displayed in the first area can be obtained, and the address range information in the address information window in the third area can be obtained, and the address range in the address information window in the third area is determined as the target address range, and the error address list corresponding to the target address range of the target pin is generated. That is, after the detailed logic matrix bitmap and the corresponding address range information of the target pin are displayed in the second view window, the user can trigger the display of the error address list of the target pin and the corresponding address range information in the third view window by triggering the list viewing space. Optionally, the target address range can also be updated by updating the address in the address range window, thereby triggering the update of the error address list displayed in the third view window.

[0082] In a possible implementation, the first view window, the second view window and the third view window may be parallel windows, and the user may select different view windows to view corresponding error address information.

[0083] In the disclosed embodiment, the corresponding test status view, logic matrix bitmap and error address list can be respectively displayed in the view window of the user interaction interface according to the error address test data corresponding to the acquired logical address, and different error address information can be displayed in different forms, so that the user can intuitively obtain different error address information of the target test object.

[0084] In the disclosed embodiment, a detailed logic matrix bitmap and a thumbnail logic matrix bitmap may also be displayed simultaneously, and the displayed contents of the two correspond to each other, so that users can compare and analyze the information in the detailed logic matrix bitmap and the thumbnail logic matrix bitmap, thereby improving the efficiency of obtaining error address information.

[0085] The storage control for storing the error address test data in the target lower computer includes at least one of a compressed data storage space (Compress Fail Memory, CFM) and an error address storage space (Address Fail Memory, AFM). The CFM space stores compressed test data corresponding to the error address test data, and the AFM space stores original error address test data.

[0086] In a possible implementation manner, the target test data acquired by the upper computer from the target lower computer includes at least one of compressed test data and original test data corresponding to a specified address range.

[0087] Optionally, the abbreviated logic matrix bitmap is generated based on the compressed test data. In response to the target test data being compressed test data, the abbreviated logic matrix bitmap corresponding to each digital input and output pin is displayed in the second view window. That is, when the acquired target test data is compressed test data, the abbreviated logic matrix bitmap corresponding to each digital input and output pin is generated according to the test data corresponding to each digital input and output pin contained in the compressed test data. The detailed logic matrix bitmap needs to be generated based on the original test data. In response to the target test data being the original test data and the selection operation of the target pin, the detailed logic matrix bitmap corresponding to the target pin is displayed in the second view window.

[0088] Optionally, the user interaction interface includes a parameter configuration page, which can be used to configure access parameters to the storage space. That is, the user can configure access parameters including a specified address range through the parameter configuration page, so that the host computer reads the corresponding target test data from the storage space according to the configured access parameters. In response to a trigger operation on a parameter configuration item in the user interaction interface, the parameter configuration page is displayed. The user interaction page provides a parameter configuration item, which is a trigger item for triggering the display of the parameter configuration page. The user can trigger the display of the parameter configuration page by triggering the parameter configuration item.

[0089] In response to configuration operations and data reading operations on the parameter configuration page, configured access parameters are obtained, and target test data is read based on the access parameters. In a possible implementation, in response to configuration operations and data reading operations on the parameter configuration page, configured access parameters may be obtained, and target test data may be read based on the access parameters.

[0090] Optionally, the parameter configuration page includes a capture parameter configuration page and an access parameter configuration page. The capture parameter is used to indicate the capture of the test data obtained by performing an error address test on the capture address range of the target test object. The access parameter is a parameter used to access the storage space. The user can configure the capture parameter through the capture parameter configuration page, the upper computer obtains the capture parameter configured by the user, sends the capture parameter to the target lower computer, and the lower computer of the test device executes the pre-set test vector (pattern) based on the capture parameter, obtains the test data obtained by performing an error address test on the capture address range of the target test object, and stores the test data corresponding to the capture address range in the storage space. After storing the test data corresponding to the capture address range in the storage space, the test data corresponding to the capture address range stored in the storage space can be accessed (i.e., read). Among them, the test vector, which can also be called test configuration information, includes the corresponding relationship between the input signal and the output reference signal. The test vector may include an input signal input to the object to be tested and its corresponding output reference signal, wherein the input signal may include 0 or 1. The output reference signal corresponding to the input signal can be understood as the output true value corresponding to the input signal, indicating the information that should be output for the input signal when the object to be tested meets its function. In a possible implementation, a preset test vector is stored in the target lower computer. When the capture parameters sent by the upper computer are received, the preset test vector is executed based on the capture parameters to obtain test data corresponding to the capture address range included in the capture parameters.

[0091] Optionally, the capture parameter configuration page provides an AFM space capture parameter configuration item and a CFM space capture parameter configuration item, and the capture parameters of the AFM space can be configured by the AFM space capture parameter configuration item, and the capture parameters of the CFM space can be configured by the CFM space capture parameter configuration item. In a possible implementation, in response to the configuration operation of the capture parameters of the AFM space capture parameter configuration item and the CFM space capture parameter configuration item, the capture parameters of the AFM space and the capture parameters of the CFM space are respectively sent to the target lower computer to store the corresponding error address test data in the AFM space and the CFM space. Optionally, the capture parameters of the AFM space and the CFM space can be the same, so that the error address test data of the same address range is stored in the AFM space and the CFM space, the original error address test data of the address range is stored in the AFM space, and the compressed error address test data of the address range is stored in the CFM space. The user can configure the AFM space capture parameters and CFM space capture parameters including the specified address range. The upper computer sends the AFM space capture parameters and CFM space capture parameters including the specified address range to the target lower computer. The target lower computer executes the preset test vectors based on the AFM space capture parameters and the CFM space capture parameters, respectively, and stores the original test data of the specified address range in the AFM space, and stores the compressed test data of the specified address range in the CFM space.

[0092] Optionally, the access parameter configuration page provides an AFM space access parameter configuration item and a CFM space access parameter configuration item, and the access parameters to the AFM space can be configured by the AFM space access parameter configuration item, and the access parameters to the CFM space can be configured by the CFM space access parameter configuration item. In a possible implementation, the address range included in the AFM space access parameter needs to be no larger than the address range included in the capture parameter in the AFM space, and the address range included in the CFM space access parameter needs to be no larger than the address range included in the capture parameter in the CFM space.

[0093] In a possible implementation, in response to the configuration parameters of the AFM space access parameter configuration item, the configured AFM space access parameters are obtained, and based on the specified address range included in the AFM space access parameters, the target test data in the specified address range is read from the AFM space. In response to the configuration parameters of the CFM space access parameter configuration item, the configured CFM space access parameters are obtained, and based on the specified address range included in the CFM space access parameters, the target test data in the specified address range is read from the CFM space.

[0094] Optionally, the user can configure access parameters to the storage space through the access parameter configuration items, or the corresponding access parameters can be automatically generated according to the capture parameters of the storage space configured by the user, that is, the AFM space access parameters are automatically generated according to the AFM space capture parameters, and the CFM space access parameters are automatically generated according to the CFM space capture parameters.

[0095] In one possible implementation, before configuring the capture parameters for the AFM space, it is also necessary to first configure the capture rule parameters for the AFM space. The capture parameter configuration items can also be used to configure the capture rule parameters. The capture rule parameters are used to indicate the capture rules for capturing error address test data and storing it in the storage space (including AFM space and CFM space).

[0096] The capture parameter configuration item includes a rule parameter configuration item, which is used to configure the capture rule parameters. Optionally, the capture rule parameters include the storage space that can store test data after capturing the test data, the maximum address range that can be captured, the minimum address range, whether the redundant mode is turned on, the functional mode used, the address arrangement rules for storing the test data corresponding to each address, and the writing rules for writing test data into the storage space (such as the correspondence between the bit of the storage space and each digital input and output pin (DQpin), the data type that can be written into the storage space), etc. The rule parameter configuration item may include a CFM space capture rule parameter configuration item and an AFM space capture rule parameter configuration item.

[0097] Taking the configuration of capture rule parameters for the AFM space as an example, when the upper computer receives the configuration operation of the AFM space capture rule parameter configuration item, it obtains the configured capture rule parameters, and then sends the configured capture rule parameters to the target lower computer, so that the target lower computer configures the AFM space according to the capture rule parameters for the AFM space, so that the AFM space captures the error address test data based on the configured capture rule parameters.

[0098] Optionally, the access parameter configuration item includes a rule parameter configuration item for configuring access rule parameters. Optionally, the access rule parameters include the address space accessible in the storage space, the maximum accessible address range, the minimum accessible address range, whether the redundant mode is turned on, etc. The rule parameter configuration item may include a CFM space access rule parameter configuration item and an AFM space access rule parameter configuration item.

[0099] Taking the configuration of access rule parameters to the AFM space as an example, when the upper computer receives the configuration operation of the AFM space access rule parameter configuration item, it obtains the configured access rule parameters, and then sends the configured access rule parameters to the target lower computer, so that the target lower computer configures the AFM space according to the access rule parameters to the AFM space.

[0100] In a possible implementation, Figure 6 As shown, it shows a flowchart of displaying the first type of view provided by an exemplary embodiment. The acquisition and display device of the error address information is set to work in the online mode, the working conditions of the AFM and / or CFM are configured (i.e., the configuration of the capture rule parameters and the access rule parameters), and then the process of reading data is executed. During the data reading process, if the reconfigured capture parameters are stored, the AFM space and the CFM space need to be initialized, the test vector is executed, and the test data of the capture address range indicated by the capture parameters is stored in the AFM space and the CFM space, and then the AFM data (original test data) and / or CFM data (compressed test data) are read based on the access parameters; if there are no reconfigured capture parameters, the AFM data and / or CFM data can be directly read based on the access parameters.

[0101] After reading the CFM data, at least one of a thumbnail logic matrix bitmap and a test status view may be displayed based on the CFM data. After reading the AFM data, at least one of a detailed logic matrix bitmap and an error address list may be displayed based on the AFM data. Afterwards, it is determined whether to reconfigure the working conditions, that is, to reconfigure the capture rule parameters and access rule parameters for the AFM space and / or the CFM space. If reconfigured, the process of reading data is re-executed.

[0102] The target test object includes multiple digital input and output pins, and the target test data includes test data corresponding to the specified address range of each digital input and output pin. Different logic matrix bitmaps correspond to test data corresponding to the specified address range of different digital input and output pins. In a possible implementation, the logic matrix bitmaps corresponding to different pins can be layered to compare the error address test results corresponding to multiple pins. The process includes the following steps:

[0103] Step 310 , in response to the layer overlay operation on at least two logic matrix bitmaps, a logic operation is performed on at least two logic matrix bitmaps to obtain a logic overlay layer.

[0104] Optionally, in the second view window for displaying the logic matrix bitmap, a layer overlay control for triggering layer overlay is provided. The second view window also includes a pin selection item and an address range configuration item. The pin selection item is used to select the digital input and output pins to be overlaid, and the address range configuration item is used to configure the specific overlay address range. Optionally, the address range configuration item may be the address range window displayed in the third area mentioned above, and the address range window may be used to select the address range.

[0105] In one possible implementation, in response to a selection operation of at least two digital input / output pins, an address range, and a logic operation mode, at least two logic matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins are obtained, and based on the selected logic operation mode, a logic operation is performed on the at least two logic matrix bitmaps to obtain a logic overlay layer, wherein the logic operation mode includes at least one of an AND operation, an OR operation, and an XOR operation.

[0106] Optionally, in response to a selection operation on a pin selection item, at least two selected digital input and output pins are obtained, and in response to a selection operation on an address range and a logical operation mode, a selected address range and a selected logical operation mode are obtained.

[0107] Based on the selected address range, test data of the selected address range of at least two selected digital input / output pins is obtained, a corresponding logic matrix bitmap is generated based on the test data of the selected address range of at least two digital input / output pins, and then a layer overlay operation is performed on at least two logic matrix bitmaps based on the selected logic operation method.

[0108] Optionally, the logic operation method includes at least one of an AND operation, an OR operation, and an XOR operation. The AND operation refers to filtering Fail addresses with the same address within the same address range, which is used to view and analyze the same Fail address distribution within the selected address range of different digital input and output pins. The OR operation refers to filtering all Fail addresses within the same address range, which is used to view and analyze all Fail address distributions within the selected address range of different digital input and output pins. The XOR operation is to filter Fail addresses with different addresses within the same address range, which is used to view and analyze different Fail address distributions within the selected address range.

[0109] Optionally, the layer overlay operation may be at least one of an overlay operation on a thumbnail logic matrix bitmap of at least two digital input / output pins and an overlay operation on a detailed logic matrix bitmap of at least two digital input / output pins.

[0110] Indicatively, Figure 5 As shown, at least two digital input / output pins to be overlapped can be selected in area 504 , and a logic operation method can be selected. An address range can be selected in the third area 503 .

[0111] In a possible implementation, when acquiring at least two logic matrix bitmaps corresponding to the selected address range of at least two digital input / output pins, it is necessary to acquire test data corresponding to the selected address range of at least two digital input / output pins. Optionally, in response to the selected address range belonging to the specified address range, the test data corresponding to the selected address range of at least two digital input / output pins is acquired from the target test data. When the selected address range belongs to the specified address range, the target test data of the specified address range is cached in the host computer, and the test data corresponding to the selected address range of at least two digital input / output pins can be acquired from the target test data.

[0112] In response to the selected address range not belonging to the specified address range, the test data corresponding to the selected address range is read from the storage space for storing the error address test data. When the selected address range does not belong to the specified address range, the upper computer does not cache the test data of the selected address range, and the capture parameters and access parameters including the selected address range can be sent to the lower computer, so as to read the test data corresponding to the selected address range from the storage space.

[0113] After acquiring the test data corresponding to the selected address range, at least two corresponding logic matrix bitmaps are generated.

[0114] In a possible implementation, a layer overlay operation may be performed on the detailed logic matrix bitmap of at least two digital input and output pins, and in the process of reading the test data corresponding to the selected address range from the storage space for storing the error address test data, the test data corresponding to the selected address range is read from the AFM space. Optionally, in response to the selected address range being larger than the display address range, the compressed test data corresponding to the selected address range is read; in response to the selected address range being not larger than the display address range, the original test data of the selected address range is read. The display address range is the address range corresponding to the number of data points allowed to be displayed in the user interaction interface. Specifically, when the overlaid logic overlay layer is displayed in the first area, the display address range is the address range corresponding to the number of data points allowed to be displayed in the first area. Among them, when reading the compressed test data corresponding to the selected address range, the upper computer can determine the compression ratio parameter according to the selected address range and the display address range, and send the compression ratio parameter and the selected address range to the target lower computer, the target lower computer reads the test data of the selected address range from the AFM space, and compresses the test data of the selected address range based on the compression ratio parameter to obtain the compressed test data corresponding to the selected address range, and returns the compressed test data corresponding to the selected address range to the upper computer, the upper computer generates the corresponding logic matrix bitmap based on the compressed test data corresponding to the selected address range of the selected digital input and output pins, and overlays the generated logic matrix bitmap to obtain a logic overlay layer.

[0115] When reading the original test data corresponding to the selected address range, the upper computer sends the selected address range to the target lower computer, the target lower computer reads the original test data of the selected address range from the AFM space, and returns the original test data corresponding to the selected address range to the upper computer. The upper computer generates a corresponding logic matrix bitmap based on the original test data corresponding to the selected address range of the selected digital input and output pins, and overlays the generated logic matrix bitmap to obtain a logic overlay layer.

[0116] Step 320: Display the logical overlay layer in the second view window of the user interaction interface.

[0117] After the logic matrix bitmaps of at least two digital input and output pins are superimposed, the superimposed logic overlay layer can be displayed in the second view window.

[0118] Optionally, in response to an overlay operation on the detailed logic matrix bitmaps of at least two digital input / output pins, the overlayed logic overlay layer is displayed in the first area. In response to an overlay operation on the abbreviated logic matrix bitmaps of at least two digital input / output pins, the overlayed logic overlay layer is displayed in the second area.

[0119] In a possible implementation, the layer overlay process is as follows: Figure 7 As shown, the front-end user interaction interface receives the selection operation of different digital input and output pins, receives the selection operation of the logical operation mode, creates the logical operation expression, and the back-end test service unit parses the logical operation expression, obtains the test data according to the selected digital input and output pins and the selected address range, and if the test data is not cached in the host computer, the test data is read again from the target lower computer. During the reading process, if the selected address range is larger than the display address range, the compressed test data is read, and if the selected address range is smaller than the display address range, the original test data is read. If the test data has been cached in the host computer, the cached data is read directly. After reading the test data, the test data is logically operated to obtain the logic overlay layer, and the user interaction interface displays the logic overlay layer.

[0120] In the disclosed embodiment, a layer overlay operation may be performed on the logic matrix bitmaps of multiple digital input and output pins of a target test object, which is beneficial to improving the efficiency of analyzing and processing error addresses of multiple digital input and output pins.

[0121] In a possible implementation manner, the second type of view is a physical matrix view corresponding to the physical error address data, which is used to indicate the position distribution of each error address of the target test object.

[0122] Optionally, the process of displaying the second type of view in the view window of the user interaction interface includes the following steps:

[0123] Step 2301, perform address conversion on the logical error address indicated by the target test data to obtain a physical error address.

[0124] In a possible implementation, the logical error address indicated in the target test data may be converted to obtain a physical error address. The process may include the following steps:

[0125] Step 1: In response to a configuration operation on a data source configuration item of a user interaction interface, a configured logic data file and a conversion rule file are obtained.

[0126] The user interface provides a data source configuration item for configuring the relevant files for obtaining physical error address data, including a logical data file and a conversion rule file. The logical data file stores the logical error address indicated by the target test data, and the conversion rule file stores the conversion rules for converting the logical address to the physical address.

[0127] In a possible implementation manner, an acquisition path for the logic data file and the conversion rule file may be configured, and the host computer acquires the logic data file and the conversion rule file according to the acquisition path.

[0128] Step 2: In response to the address conversion operation, the logical error address is read from the logical data file and the conversion rule is read from the conversion rule file, and the logical error address is converted into a physical error address based on the conversion rule.

[0129] In one possible implementation, an address conversion control is provided in the data source configuration item. In response to a trigger operation on the address conversion control, it is determined that an address conversion operation is received, a logical error address indicated in the target test data is read from a logical data file, and based on a conversion rule indicated in a conversion rule file, the logical error address is converted into a physical error address.

[0130] Optionally, the address conversion process includes a segmentation operation on the physical address of the target test object and a sorting operation on the logical error address. By segmenting the physical address of the target test object, the physical address space can be segmented into different areas. After a logical error address is converted to a physical address, the physical address space area to which the converted physical error address belongs can be determined based on the segmented physical address space area, and the physical position corresponding to the logical error address can be quickly located. The sorting operation on the logical error address can be based on the physical error address corresponding to each logical error address obtained by the conversion, which is helpful for the rapid analysis of the physical error address.

[0131] In a possible implementation, before address conversion, a physical data source file needs to be configured, and the physical data source file is a file used to store physical error address data, including configuring the file path and file name of the physical data source file, and after address conversion, the physical error address is stored in the configured physical data source file based on the configured file path and file name.

[0132] Step 2302: Based on the physical error address, a physical matrix bitmap is displayed in the view window of the user interaction interface. The physical matrix bitmap is used to indicate the position distribution of each error address of the target test object. The physical error address is displayed in the physical matrix view.

[0133] In a possible implementation, the physical error address can be read from the physical data source file based on the configured file path and file name, a physical matrix bitmap can be generated based on the physical error address, and the physical matrix bitmap can be displayed in the view window of the user interaction interface. The physical matrix bitmap corresponds to the entire target test object, the physical error address includes the physical error address obtained after converting the logical error address of each digital input and output pin, and the generated physical matrix bitmap includes the distribution of the logical error address of each digital input and output pin at the actual physical position on the target test object.

[0134] Optionally, the physical matrix bitmap includes at least one of a thumbnail physical matrix bitmap and a detailed physical matrix bitmap.

[0135] Displaying the physical matrix bitmap in the view window of the user interface includes the following steps:

[0136] Step 1: Display a thumbnail physical matrix bitmap in the fourth area of ​​the view window.

[0137] Step 2: In response to a selection operation on an address range in the thumbnail physical matrix bitmap, a detailed physical matrix bitmap corresponding to the selected address range is displayed in a fifth area of ​​the view window.

[0138] In a possible implementation, a thumbnail physical matrix bitmap and a detailed physical matrix bitmap corresponding to the target test object may be displayed in the view window at the same time. Optionally, the thumbnail physical matrix bitmap corresponding to the target test object is displayed in the fourth area of ​​the view window, and the detailed physical matrix bitmap corresponding to the target test object is displayed in the fifth area, wherein the area of ​​the fifth area is greater than the area of ​​the fourth area. Optionally, the fourth area may be the same as the second area, and the fifth area may be the same as the first area.

[0139] In a possible implementation, the selected matrix area in the thumbnail physical matrix bitmap displayed in the fourth area corresponds to the detailed physical matrix bitmap in the fifth area. In response to the address range selection operation on the thumbnail physical matrix bitmap, the detailed physical matrix bitmap displayed in the fifth area is updated based on the selected address range. Optionally, the address range selection operation on the thumbnail physical matrix bitmap may be a box selection operation on a local matrix bitmap area in the thumbnail physical matrix bitmap, and the detailed physical matrix bitmap displayed in the fifth area is a physical matrix bitmap after the boxed local matrix bitmap area is enlarged. In response to the box selection operation on the local matrix bitmap area in the thumbnail physical matrix bitmap, the corresponding selected address range is determined according to the boxed local matrix bitmap, and the detailed physical matrix bitmap displayed in the fifth area is updated based on the physical error address corresponding to the selected address range. In a possible implementation, in response to the drag operation on the detailed physical matrix bitmap, the selected address range in the thumbnail physical matrix bitmap is updated based on the dragged physical address range. Optionally, the user can drag the detailed physical matrix bitmap displayed in the fifth area. When a drag operation on the detailed physical matrix bitmap is received, the detailed logical matrix bitmap displayed in the fifth area is updated based on the drag operation, and based on the physical address range corresponding to the updated detailed logical matrix bitmap, the selected local matrix bitmap area in the thumbnail physical matrix bitmap in the fourth area is updated.

[0140] Optionally, a horizontal drag axis and a vertical drag axis are provided in the fifth area. In response to the drag operation on the horizontal drag axis and / or the vertical drag axis, the detailed physical matrix bitmap displayed in the fifth area and the selected local matrix bitmap area in the thumbnail physical matrix bitmap in the fourth area are updated.

[0141] In a possible implementation, the user may zoom in on the detailed physical matrix bitmap, and in response to the zoom-in operation on the detailed physical matrix bitmap, the detailed physical matrix bitmap is zoomed in.

[0142] When the detailed physical matrix bitmap is enlarged to a target state, in response to a viewing operation on a target physical address, a logical address corresponding to the target physical address is displayed. The target state refers to a state in which a physical unit in the detailed physical matrix bitmap corresponds to a physical address.

[0143] Optionally, the target state may be a state in which the detailed physical matrix is ​​enlarged to the maximum, in which a physical unit in the detailed physical matrix bitmap corresponds to a physical address. In the target state, in response to a viewing operation on the target physical address, a logical address corresponding to the target physical address may be displayed. Optionally, in response to a selection operation on a target physical unit corresponding to the target physical address, it is determined that a viewing operation on the target physical address is received, and an overlay subwindow may be displayed in the view window, and the overlay subwindow displays the logical address information corresponding to the target physical address.

[0144] Indicative, such as Figure 8 As shown, in response to the selection operation on the target physical unit 801 , the corresponding logical address information is displayed in the overlay sub-window 802 .

[0145] In a possible implementation, a layer overlay operation may be performed on the physical matrix bitmaps corresponding to multiple different target test objects to compare the distribution of physical error addresses corresponding to the multiple test objects. The steps include:

[0146] Step 410, in response to a layer overlay operation on a physical matrix bitmap of at least two target test objects, overlays the physical matrix bitmaps of at least two target test objects to obtain a physical overlay layer, wherein at least two physical matrix bitmaps respectively correspond to error address test data in the same address range of at least two target test objects.

[0147] Optionally, a layer overlay control for triggering layer overlay is provided in a view window for displaying a physical matrix bitmap. A target test object selection item is also provided in the view window. The target test object selection item is used to select a target test object to be overlaid, and the address range configuration item is used to configure a specific overlaid physical address range.

[0148] In one possible implementation, in response to a selection operation of at least two target test objects, an address range, and a logical operation mode, at least two physical matrix bitmaps corresponding to the selected address ranges of the at least two target test objects are obtained, and based on the selected logical operation mode, a logical operation is performed on the at least two physical matrix bitmaps to obtain a physical overlay layer, and the logical operation mode includes at least one of an AND operation, an OR operation, and an XOR operation.

[0149] Optionally, in response to a selection operation on a target test object selection item, at least two selected target test objects are obtained, and in response to a selection operation on an address range and a logical operation mode, a selected physical address range and a selected logical operation mode are obtained.

[0150] Based on the selected address range, the physical error addresses of the selected address range of at least two selected target test objects are obtained, a corresponding physical matrix bitmap is generated, and then a layer overlay operation is performed on the at least two physical matrix bitmaps based on the selected logical operation method.

[0151] Optionally, the logical operation method includes at least one of an AND operation, an OR operation, and an XOR operation. The AND operation refers to filtering Fail addresses with the same address within the same address range, which is used to view and analyze the same Fail address distribution within the selected physical address range of different target test objects. The OR operation refers to filtering all Fail addresses within the same address range, which is used to view and analyze all Fail address distributions within the selected physical address range of different target test objects. The XOR operation is to filter Fail addresses with different addresses within the same address range, which is used to view and analyze different Fail address distributions within the selected physical address range.

[0152] Optionally, the layer overlay operation may be at least one of an overlay operation on thumbnail physical matrix bitmaps of at least two target test objects and an overlay operation on detailed logical matrix bitmaps of at least two target test objects.

[0153] Step 420: Display the physical overlay layer in the view window of the user interaction interface.

[0154] Optionally, in response to the overlay operation of the detailed physical matrix bitmaps of at least two target test objects, the overlayed physical overlay layer is displayed in the fifth area. In response to the overlay operation of the thumbnail logical matrix bitmaps of at least two target test objects, the overlayed physical overlay layer is displayed in the fourth area.

[0155] In a possible implementation, the physical layer overlay process is as follows: Fig. 9 As shown, the process includes: the front-end user interaction interface receives selection operations for different target test objects, receives selection operations for logical operation methods, and creates logical operation expressions. After that, the back-end test service unit parses the logical operation expressions, obtains data from the physical data source file according to the selected target test objects and address ranges, performs logical operations on the obtained data, obtains a physical overlay layer, and the user interaction interface displays the physical overlay layer.

[0156] In the disclosed embodiment, a layer overlay operation may be performed on the physical matrix bitmaps of multiple target test objects, which is beneficial to improving the efficiency of analyzing and processing the location distribution of physical error addresses in the multiple target test objects.

[0157] FIG. 10 is a schematic diagram of a structure of an apparatus for obtaining and processing error address information provided by an exemplary embodiment of the present disclosure, the apparatus comprising:

[0158] A data reading module 1001 is configured to read target test data of a target test object in response to a data reading operation being detected by a user interaction interface, wherein the target test data is error address test data corresponding to a specified address range in error address test data of the target test object;

[0159] A view display module 1002, configured to display a first type of view in a view window of the user interaction interface based on the target test data, wherein the first type of view is configured to indicate test result information of different addresses within the specified address range;

[0160] The view display module 1002 is also used to display a second type of view in the view window of the user interaction interface in response to the user interaction interface detecting a view switching operation, based on the target test data, wherein the second type of view is used to indicate the location distribution information of the error addresses in the specified address range on the target test object.

[0161] In an exemplary embodiment, the first type of view includes at least one of a test status view, a logic matrix bitmap, and an error address list, wherein the test status view is used to indicate the test status information of the specified address range, the logic matrix bitmap is used to indicate the test result information corresponding to each logical address in the specified address range, and the error address list is used to indicate the error address within the specified address range;

[0162] The view display module 1002 is further used for:

[0163] In response to a request to view the test status view, displaying the test status view corresponding to the target test data in a first view window of the user interaction interface; and / or,

[0164] In response to a request to view the logic matrix bitmap, displaying the logic matrix bitmap corresponding to the target test data in a second view window of the user interaction interface; and / or,

[0165] In response to a request to view the error address list, the error address list corresponding to the target test data is displayed in a third view window of the user interaction interface.

[0166] In an exemplary embodiment, the target test object includes a plurality of digital input and output pins, and the target test data includes test data corresponding to a specified address range of each of the digital input and output pins;

[0167] The view display module 1002 is further used for:

[0168] Displaying a test status view for indicating the test status of each of the digital input and output pins in the first view window;

[0169] Displaying the thumbnail logic matrix bitmap corresponding to each of the digital input / output pins in the second view window; and / or, in response to a selection operation on a target pin, displaying the detailed logic matrix bitmap corresponding to the target pin in the second view window, wherein the target pin is any digital input / output pin among the plurality of digital input / output pins;

[0170] In response to the selection operation of the target pin and the target address range, an error address list corresponding to the target address range of the target pin is displayed in the third view window, and the target address range belongs to the designated address range.

[0171] In an exemplary embodiment, the view display module 1002 is further configured to:

[0172] Displaying a detailed logic matrix bitmap corresponding to the target pin in the first area of ​​the second view window;

[0173] Displaying a thumbnail logic matrix bitmap corresponding to the target pin in a second area of ​​the second view window;

[0174] In response to an address range selection operation on the thumbnail logic matrix bitmap, updating the detailed logic matrix bitmap displayed in the first region based on the selected address range;

[0175] In response to a drag operation on the detailed logic matrix bitmap, a selected address range in the thumbnail logic matrix bitmap is updated based on the dragged address range.

[0176] In an exemplary embodiment, the view display module 1002 is further configured to:

[0177] Displaying an address information window in the third area of ​​the second view window, wherein the address information window displays address range information corresponding to the detailed logic matrix bitmap currently displayed in the first area;

[0178] In response to an update operation on the address range information in the address information window, updating the detailed logic matrix bitmap displayed in the first area based on the updated address range;

[0179] In response to a drag operation on the detailed logic matrix bitmap, the address range information in the address information window is updated based on the dragged address range information.

[0180] In an exemplary embodiment, the target test data includes at least one of compressed test data and original test data corresponding to the specified address range;

[0181] The view display module 1002 is further used for:

[0182] In response to the target test data being the compressed test data, displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window;

[0183] In response to the target test data being the original test data, a detailed logic matrix bitmap corresponding to the target pin is displayed in the second view window.

[0184] In an exemplary embodiment, the compressed test data is stored in a compressed data storage space, and the original test data is stored in an error address storage space;

[0185] The device also includes:

[0186] a page display module, configured to display a parameter configuration page in response to a trigger operation on a parameter configuration item in the user interaction interface, wherein the parameter configuration page is used to configure access parameters to a storage space, wherein the storage space includes at least one of the compressed data storage space and the error address storage space;

[0187] The data reading module is also used for:

[0188] In response to the configuration operation on the parameter configuration page and the data reading operation, the configured access parameters are acquired, and the target test data is read based on the access parameters, wherein the configured access parameters include the configured designated address range.

[0189] In an exemplary embodiment, the target test object includes a plurality of digital input and output pins, the target test data includes test data corresponding to a specified address range of each of the digital input and output pins, and different logic matrix bitmaps correspond to test data corresponding to the specified address ranges of different digital input and output pins;

[0190] The device also includes:

[0191] A layer overlay module, configured to, in response to a layer overlay operation on at least two logic matrix bitmaps, perform a logic operation on the at least two logic matrix bitmaps to obtain a logic overlay layer;

[0192] A layer display module is used to display the logical overlay layer in the second viewing window of the user interaction interface.

[0193] In an exemplary embodiment, the layer overlay module is further used to:

[0194] In response to the selection operation of at least two digital input / output pins, address range and logic operation mode, at least two logic matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins are obtained, and based on the selected logic operation mode, the at least two logic matrix bitmaps are subjected to logic operation to obtain the logic overlay layer, wherein the logic operation mode includes at least one of an AND operation, an OR operation and an XOR operation.

[0195] The layer overlay module is further used for:

[0196] In response to the selected address range belonging to the specified address range, acquiring test data corresponding to the selected address range of the at least two digital input and output pins from the target test data;

[0197] In response to the selected address range not belonging to the specified address range, reading test data corresponding to the selected address range from a storage space for storing error address test data;

[0198] The at least two logic matrix bitmaps are generated based on the test data corresponding to the selected address range.

[0199] In an exemplary embodiment, the layer overlay module is further used to:

[0200] In response to the selected address range being larger than the display address range, reading the compression test data corresponding to the selected address range, the display address range being the address range allowed to be displayed by the user interaction interface;

[0201] In response to the selected address range being not larger than the display address range, original test data corresponding to the selected address range is read.

[0202] In an exemplary embodiment, the view display module 1002 is further configured to:

[0203] Performing address conversion on the logical error address indicated by the target test data to obtain a physical error address;

[0204] Based on the physical error addresses, a physical matrix bitmap is displayed in the view window of the user interaction interface, the physical matrix bitmap is used to indicate the position distribution of each error address of the target test object, and the physical error addresses are displayed in the physical matrix view.

[0205] In an exemplary embodiment, the view display module 1002 is further configured to:

[0206] Displaying a thumbnail physical matrix bitmap in a fourth area of ​​the view window;

[0207] In response to a selection operation on an address range in the thumbnail physical matrix bitmap, a detailed physical matrix bitmap corresponding to the selected address range is displayed in a fifth area of ​​the view window.

[0208] The device also includes:

[0209] A bitmap enlarging module, configured to enlarge the detailed physical matrix bitmap in response to an enlarging operation on the detailed physical matrix bitmap;

[0210] The address information display module is used to display the logical address corresponding to the target physical address in response to the viewing operation of the target physical address when the detailed physical matrix bitmap is enlarged to the target state. The target state refers to the state in which one physical unit in the detailed physical matrix bitmap corresponds to one physical address.

[0211] In an exemplary embodiment, the layer overlay module is further used to:

[0212] In response to a layer overlay operation on physical matrix bitmaps of at least two target test objects, the physical matrix bitmaps of the at least two target test objects are overlaid to obtain a physical overlay layer, wherein the at least two physical matrix bitmaps respectively correspond to error address test data of the same address range of the at least two target test objects;

[0213] The layer display module is also used to display the physical overlay layer in the view window of the user interaction interface.

[0214] In an exemplary embodiment, the layer overlay module is further used to:

[0215] In response to the selection operation of at least two target test objects, address ranges and logical operation modes, at least two physical matrix bitmaps corresponding to the selected address ranges of the at least two target test objects are obtained, and based on the selected logical operation mode, logical operations are performed on the at least two physical matrix bitmaps to obtain the physical overlay layer, wherein the logical operation mode includes at least one of an AND operation, an OR operation and an XOR operation.

[0216] In an exemplary embodiment, the view display module 1002 is further configured to:

[0217] In response to a configuration operation on a data source configuration item of a user interaction interface, a configured logic data file and a conversion rule file are acquired, wherein the logic data file stores a logic error address of the target test data, and the conversion rule file stores a conversion rule for converting a logical address into a physical address;

[0218] In response to an address conversion operation, the logical error address is read from the logical data file and the conversion rule is read from the conversion rule file, and the logical error address is converted into a physical error address based on the conversion rule.

[0219] The device also includes:

[0220] A file configuration module, used to configure the file path and file name of the physical data source file;

[0221] A data storage module, used for storing the physical error address in a configured physical data source file;

[0222] The view display module is also used for:

[0223] Based on the configured file path and file name, read the physical error address from the physical data source file, and generate the physical matrix bitmap based on the physical error address;

[0224] The physical matrix bitmap is displayed in a view window of the user interaction interface.

[0225] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0226] Memory for storing computer programs;

[0227] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure is implemented.

[0228] like Fig.11 As shown, the electronic device includes one or more processors and memory.

[0229] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0230] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the error address information acquisition and processing method of each embodiment of the present disclosure described above and / or other desired functions.

[0231] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0232] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0233] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0234] Of course, to simplify, Fig.11 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0235] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method for obtaining and processing error address information according to various embodiments of the present disclosure described in the above part of this specification.

[0236] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0237] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the method for obtaining and processing error address information according to various embodiments of the present disclosure described in the above part of this specification.

[0238] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0239] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0240] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0241] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The word "such as" used here refers to the phrase "such as but not limited to", and can be used interchangeably with it.

[0242] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0243] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0244] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0245] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A method for obtaining and processing error address information, characterized in that: The method comprises: In response to the user interaction interface detecting a data read operation, reading target test data of a target test object, the target test data being error address test data corresponding to a specified address range in error address test data of the target test object; Based on the target test data, displaying a first type of view in a view window of the user interaction interface, wherein the first type of view is used to indicate test result information of different addresses within the specified address range; In response to the user interaction interface detecting a view switching operation, a second type of view is displayed in the view window of the user interaction interface based on the target test data, and the second type of view is used to indicate the location distribution information of the error addresses in the specified address range on the target test object.

2. The method according to claim 1, characterized in that The first type of view includes at least one of a test status view, a logic matrix bitmap, and an error address list, wherein the test status view is used to indicate the test status information of the specified address range, the logic matrix bitmap is used to indicate the test result information corresponding to each logical address in the specified address range, and the error address list is used to indicate the error address in the specified address range; The displaying the first type of view in the view window of the user interaction interface includes: In response to a request to view the test status view, displaying the test status view corresponding to the target test data in a first view window of the user interaction interface; and / or, In response to a request to view the logic matrix bitmap, displaying the logic matrix bitmap corresponding to the target test data in a second view window of the user interaction interface; and / or, In response to a request to view the error address list, the error address list corresponding to the target test data is displayed in a third view window of the user interaction interface.

3. The method according to claim 2, characterized in that The target test object includes a plurality of digital input and output pins, and the target test data includes test data corresponding to a specified address range of each of the digital input and output pins; The displaying of the test status view corresponding to the target test data in the first view window of the user interaction interface includes: Displaying a test status view for indicating the test status of each of the digital input and output pins in the first view window; The displaying of the logic matrix bitmap corresponding to the target test data in the second view window of the user interaction interface includes: Displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window; and / or, In response to a selection operation on a target pin, displaying a detailed logic matrix bitmap corresponding to the target pin in the second view window, wherein the target pin is any digital input / output pin among the plurality of digital input / output pins; The displaying of the error address list corresponding to the target test data in the third view window of the user interaction interface includes: In response to the selection operation of the target pin and the target address range, an error address list corresponding to the target address range of the target pin is displayed in the third view window, and the target address range belongs to the designated address range.

4. The method according to claim 3, characterized in that The displaying the detailed logic matrix bitmap corresponding to the target pin in the second view window includes: Displaying a detailed logic matrix bitmap corresponding to the target pin in the first area of ​​the second view window; The method further comprises: Displaying a thumbnail logic matrix bitmap corresponding to the target pin in a second area of ​​the second view window; In response to an address range selection operation on the thumbnail logic matrix bitmap, updating the detailed logic matrix bitmap displayed in the first region based on the selected address range; In response to a drag operation on the detailed logic matrix bitmap, a selected address range in the thumbnail logic matrix bitmap is updated based on the dragged address range.

5. The method according to claim 4, characterized in that The method further comprises: Displaying an address information window in the third area of ​​the second view window, wherein the address information window displays address range information corresponding to the detailed logic matrix bitmap currently displayed in the first area; In response to an update operation on the address range information in the address information window, updating the detailed logic matrix bitmap displayed in the first area based on the updated address range; In response to a drag operation on the detailed logic matrix bitmap, the address range information in the address information window is updated based on the dragged address range information.

6. The method according to claim 3, characterized in that: The target test data includes at least one of compressed test data and original test data corresponding to the specified address range; Displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window includes: In response to the target test data being the compressed test data, displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window; The displaying the detailed logic matrix bitmap corresponding to the target pin in the second view window includes: In response to the target test data being the original test data, a detailed logic matrix bitmap corresponding to the target pin is displayed in the second view window.

7. The method according to claim 6, characterized in that The compressed test data is stored in the compressed data storage space, and the original test data is stored in the error address storage space; Before the target test data of the target test object is read in response to the user interaction interface detecting the data reading operation, the method further includes: In response to a triggering operation on a parameter configuration item in a user interaction interface, displaying a parameter configuration page, the parameter configuration page being used to configure access parameters to a storage space, the storage space including at least one of the compressed data storage space and the error address storage space; The step of reading target test data of a target test object comprises: In response to the configuration operation on the parameter configuration page and the data reading operation, the configured access parameters are acquired, and the target test data is read based on the access parameters, wherein the configured access parameters include the configured designated address range.

8. The method according to any one of claims 2 to 7, characterized in that: The target test object includes a plurality of digital input and output pins, the target test data includes test data corresponding to a specified address range of each of the digital input and output pins, and different logic matrix bitmaps correspond to test data corresponding to the specified address ranges of different digital input and output pins; The method further comprises: In response to a layer overlay operation on at least two logic matrix bitmaps, performing a logic operation on the at least two logic matrix bitmaps to obtain a logic overlay layer; The logical overlay layer is displayed in a second viewing window of the user interaction interface.

9. The method according to claim 8, characterized in that In response to the layer overlay operation on at least two logic matrix bitmaps, performing a logical operation on the at least two logic matrix bitmaps to obtain a logic overlay layer includes: In response to the selection operation of at least two digital input / output pins, address range and logic operation mode, at least two logic matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins are obtained, and based on the selected logic operation mode, the at least two logic matrix bitmaps are subjected to logic operation to obtain the logic overlay layer, wherein the logic operation mode includes at least one of an AND operation, an OR operation and an XOR operation.

10. The method according to claim 9, characterized in that The obtaining of at least two logic matrix bitmaps corresponding to the selected address ranges of the at least two digital input / output pins comprises: In response to the selected address range belonging to the specified address range, acquiring test data corresponding to the selected address range of the at least two digital input and output pins from the target test data; In response to the selected address range not belonging to the specified address range, reading test data corresponding to the selected address range from a storage space for storing error address test data; The at least two logic matrix bitmaps are generated based on the test data corresponding to the selected address range.

11. The method according to claim 10, characterized in that The step of reading the test data corresponding to the selected address range from the storage space for storing error address test data includes: In response to the selected address range being larger than the display address range, reading the compression test data corresponding to the selected address range, the display address range being the address range allowed to be displayed by the user interaction interface; In response to the selected address range being not larger than the display address range, original test data corresponding to the selected address range is read.

12. The method according to any one of claims 1 to 7, characterized in that: The displaying of the second type of view in the view window of the user interaction interface based on the target test data includes: Performing address conversion on the logical error address indicated by the target test data to obtain a physical error address; Based on the physical error addresses, a physical matrix bitmap is displayed in the view window of the user interaction interface, wherein the physical matrix bitmap is used to indicate the position distribution of each error address of the target test object, and the physical error addresses are displayed in the physical matrix view.

13. The method according to claim 12, characterized in that The displaying of the physical matrix view in the view window of the user interaction interface includes: Displaying a thumbnail physical matrix bitmap in a fourth area of ​​the view window; In response to a selection operation on an address range in the thumbnail physical matrix bitmap, displaying a detailed physical matrix bitmap corresponding to the selected address range in a fifth area of ​​the view window; In response to a drag operation on the detailed physical matrix bitmap, a selected address range in the thumbnail physical matrix bitmap is updated based on the dragged address range.

14. The method according to claim 13, characterized in that The method further comprises: In response to a zoom-in operation on the detailed physical matrix bitmap, zooming in the detailed physical matrix bitmap; When the detailed physical matrix bitmap is enlarged to a target state, in response to a viewing operation on a target physical address, a logical address corresponding to the target physical address is displayed, wherein the target state refers to a state in which one physical unit in the detailed physical matrix bitmap corresponds to one physical address.

15. The method according to claim 12, characterized in that The method further comprises: In response to a layer overlay operation on physical matrix bitmaps of at least two target test objects, the physical matrix bitmaps of the at least two target test objects are overlaid to obtain a physical overlay layer, wherein the at least two physical matrix bitmaps respectively correspond to error address test data of the same address range of the at least two target test objects; The physical overlay layer is displayed in a view window of the user interaction interface.

16. The method according to claim 15, characterized in that In response to the layer overlay operation on the physical matrix bitmaps of at least two target test objects, the physical matrix bitmaps of the at least two target test objects are overlaid to obtain a physical overlay layer, including: In response to the selection operation of at least two target test objects, address ranges and logical operation modes, at least two physical matrix bitmaps corresponding to the selected address ranges of the at least two target test objects are obtained, and based on the selected logical operation mode, logical operations are performed on the at least two physical matrix bitmaps to obtain the physical overlay layer, wherein the logical operation mode includes at least one of an AND operation, an OR operation and an XOR operation.

17. The method according to claim 12, characterized in that The performing address conversion on the logical error address indicated by the target test data to obtain a physical error address includes: In response to a configuration operation on a data source configuration item of a user interaction interface, a configured logic data file and a conversion rule file are acquired, wherein the logic data file stores a logic error address indicated by the target test data, and the conversion rule file stores a conversion rule for converting a logical address into a physical address; In response to an address conversion operation, the logical error address is read from the logical data file and the conversion rule is read from the conversion rule file, and the logical error address is converted into a physical error address based on the conversion rule.

18. The method according to claim 17, characterized in that The method further comprises: Configure the file path and file name of the physical data source file; storing the physical error address in a configured physical data source file; The displaying of a physical matrix bitmap in a view window of the user interaction interface based on the physical error address includes: Based on the configured file path and file name, read the physical error address from the physical data source file, and generate the physical matrix bitmap based on the physical error address; The physical matrix bitmap is displayed in a view window of the user interaction interface.

19. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method for obtaining and processing error address information described in any one of claims 1 to 18 is implemented.

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