Thermal noise elimination high-speed assembly line successive approximation hybrid analog-to-digital converter

Abstract

The invention discloses a thermal noise elimination high-speed assembly line successive approximation hybrid analog-to-digital converter, which comprises a first sampling branch and a second sampling branch, and is characterized in that the first sampling branch is used for top plate sampling and is used for quantizing an MSB bit of an input sampling signal after a sampling clock signal becomes a low level for a preset time; and the second sampling branch is used for sampling the bottom plate and directly quantizing the MSB bit of the input sampling signal after the sampling clock signal is changed into the low level, and the second sampling branch is also used for quantizing the residual bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the MSB bit quantization. According to the invention, the problems of amplitude attenuation and insufficient time utilization caused by a bottom plate technology are solved, and meanwhile, the problem of trade-off between residual thermal noise average power and power consumption is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter. Background Art

[0002] Pipelined-SAR ADC (pipelined successive approximation hybrid analog-to-digital converter) is the mainstream architecture in the field of high-speed and high-precision ADC, but the thermal noise introduced by the sampling switch has always been a key factor limiting the performance improvement in this field. The average power of the sampling thermal noise is related to the size of the sampling capacitor. The larger the sampling capacitor, the smaller the average power of the thermal noise. However, due to the increase in the load of the sampling switch, its design difficulty also increases; the smaller the sampling capacitor, the lower the bandwidth requirement for the sampling switch, but the average power of the noise will increase.

[0003] The thermal noise elimination technology currently proposed for Pipelined-SAR ADC is based on the principle of sampling the signal through the bottom plate sampling technology, and using the first stage of the operational amplifier through a specific timing to store the thermal noise introduced by the sampling switch as an offset on the offset capacitor between the first and second stages of the operational amplifier. Due to the use of the offset storage technology, the amplification object of the multiplying digital-to-analog converter (MDAC) only contains the residual information but not the thermal noise introduced by the sampling switch.

[0004] The application of thermal noise elimination technology is inseparable from the bottom plate sampling technology, but this technology has two problems: the first problem is that the bottom plate sampling technology will be affected by the parasitic capacitance and feedback capacitance at the top plate of the sampling capacitor, causing the collected signal to attenuate in amplitude and lose part of the fundamental wave energy, resulting in a decrease in the effective number of bits and signal-to-noise ratio of the ADC; the second problem is that compared with the top plate sampling, the bottom plate sampling technology will undergo a signal flipping process and then quantization after the sampling is completed, and this flipping process takes up a certain time budget. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter, comprising a first sampling branch and a second sampling branch, wherein:

[0007] The first sampling branch is a top plate sampling, which is used to quantize the MSB bit of the input sampling signal after the sampling clock signal becomes low level for a predetermined time;

[0008] The second sampling branch is a bottom plate sampling, which is used to directly quantize the MSB bit of the input sampling signal after the sampling clock signal becomes a low level, and the second sampling branch also quantizes the remaining bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the MSB bit quantization.

[0009] In one embodiment of the present invention, the first sampling branch includes a capacitor array C S1N 、Capacitor array C S1P , operational amplifier A1, operational amplifier A 2,3 , offset capacitor C N1 , offset capacitor C N2 , feedback capacitor C F1 , feedback capacitor C F2 , switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, switch K9, switch K10, switch K17 and switch K18, wherein,

[0010] The switch K1 and the capacitor array C S1P Connect in series to the first differential input terminal V IP The first input terminal V of the operational amplifier A1 is IP1 Between the switch K2 and the capacitor array C S1n In series with the second differential input V IN The second input terminal V of the operational amplifier A1 IN1 Between the first differential input terminal V IP and the second differential input terminal V IN Used to input sampling signal;

[0011] The offset capacitor C N1 Connect the first output terminal V of the operational amplifier A1 to OP1 With the operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitor C N2 Connect the second output terminal V of the operational amplifier A1 to ON1 With the operational amplifier A 2,3 The second input terminal V IN2 between;

[0012] The feedback capacitor C F1 The switch K5 is connected in series with the first input terminal V of the operational amplifier A1. IP1 between the operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2The switch K10 is connected in series with the second input terminal V of the operational amplifier A1. IN2 between the operational amplifier A 2,3 The first output terminal V OP2 between;

[0013] The first end of the switch K3 is connected to the first differential input terminal V IP , the second end is connected to the feedback capacitor C F1 The first end of the switch K4 is connected to the common mode voltage input terminal V CM , the second end is connected to the feedback capacitor C F1 and the switch K5; the first end of the switch K8 is connected to the second differential input terminal V IN , the second end is connected to the feedback capacitor C F2 Between the switch K10, the first end of the switch K9 is connected to the common mode voltage input terminal V CM , the second end is connected to the feedback capacitor C F2 Between the switch K10;

[0014] The switch K6 is connected to the common mode voltage input terminal V CM With the operational amplifier A 2,3 The first input terminal V IP2 The switch K7 is connected to the common mode voltage input terminal V CM With the operational amplifier A 2,3 The second input terminal V IN2 between;

[0015] The switch K17 is connected to the common mode voltage input terminal V CM The first input terminal V of the operational amplifier A1 is IP1 The switch K18 is connected to the common mode voltage input terminal V CM The second input terminal V of the operational amplifier A1 IN1 between;

[0016] The switches K1, K2, K3, K8, K6 and K7 are all controlled by the sampling clock signal CLKS, the switches K4 and K9 are all controlled by the clock signal φ1, the switches K5 and K10 are all controlled by the clock signal AMP; the switches K17 and K18 are all controlled by the clock signal CLKSE.

[0017] In one embodiment of the present invention, the first sampling branch further includes a switch K11 and a switch K12, wherein:

[0018] The switch K11 is connected to the operational amplifier A 2,3 The second output terminal V ON2 and the first input terminal of the subsequent ADC; the switch K12 is connected to the operational amplifier A 2,3 The first output terminal V OP2 Between the second input terminal of the subsequent ADC;

[0019] The switch K11 and the switch K12 are both controlled by the clock signal AMP.

[0020] In one embodiment of the present invention, when the sampling clock signal CLKS changes to a low level, the clock signal φ1 changes to a high level, and when the clock signal φ1 changes to a low level, the clock signal AMP changes to a high level;

[0021] The sum of the duration that the clock signal φ1 is at a high level and the duration that the clock signal AMP is at a high level is equal to the duration that the sampling clock signal CLKS is at a low level;

[0022] The clock signal CLKSE and the sampling clock signal CLKS are triggered to high level at the same time, and the high level duration of the clock signal CLKSE is shorter than the high level duration of the sampling clock signal CLKS by a predetermined time.

[0023] In one embodiment of the present invention, the second sampling branch includes a comparator COM1, a comparator COM2, a capacitor array C S2N 、Capacitor array C S2P , switch K13, switch K14, switch K15, switch K16, logic control module, wherein,

[0024] The switch K13 is connected to the operational amplifier A 2,3 The first input terminal V IP2 The switch K14 is connected between the first input terminal of the comparator COM1 and the first input terminal of the comparator COM1. 2,3 The second input terminal V IN2 and a second input terminal of the comparator COM1;

[0025] The switch K15 is connected to the first differential input terminal V IP The switch K16 is connected between the second differential input terminal V IN and a second input terminal of the comparator COM2;

[0026] The capacitor array C S2P is connected between the ground terminal and the first input terminal of the comparator COM2, the capacitor array C S2Nconnected between the ground terminal and the second input terminal of the comparator COM2, the output terminal of the comparator COM1 is connected to the first input terminal of the logic control module, and the output terminal of the comparator COM2 is connected to the second input terminal of the logic control module;

[0027] The output end of the logic control module is connected to the capacitor array C S1N and the capacitor array C S1P , used to change the capacitor array C according to the output results of the comparator COM1 and the comparator COM2 S1N and the capacitor array C S1P The voltage connected to the lower plate of the corresponding capacitor;

[0028] The switch K13 , the switch K14 , the switch K15 , and the switch K16 are all controlled by the sampling clock signal CLKS.

[0029] In one embodiment of the present invention, the operational amplifier A1 includes MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, a common-mode feedback circuit, a switch K19, and a switch K20, wherein:

[0030] The source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3 and the source of the MOS tube M4 are all connected to the power supply terminal VDD, and the drain of the MOS tube M1, the drain of the MOS tube M2, the drain of the MOS tube M3, the drain of the MOS tube M4 and the source of the MOS tube M5 are all connected to the source of the MOS tube M6;

[0031] The gate of the MOS transistor M5 is connected to the gate of the MOS transistor M7 and serves as the first input terminal V of the operational amplifier A1. IP1 The drain of the MOS tube M5 is connected to the drain of the MOS tube M7 and serves as the second output terminal V of the operational amplifier A1. ON1 The gate of the MOS tube M6 is connected to the gate of the MOS tube M8 and serves as the second input terminal V of the operational amplifier A1. IN1 The drain of the MOS tube M6 is connected to the drain of the MOS tube M6 and serves as the first output terminal V of the operational amplifier A1. OP1 ;

[0032] The source of the MOS tube M7 is connected to the source of the MOS tube M8, and the drain of the MOS tube M9, the drain of the MOS tube M10, the drain of the MOS tube M11 and the drain of the MOS tube M12 are all connected to the ground end;

[0033] The gate of the MOS tube M1 and the gate of the MOS tube M9 are both connected to the second output terminal V of the operational amplifier A1. ON1 The gate of the MOS tube M4 and the gate of the MOS tube M12 are both connected to the first output terminal V of the operational amplifier A1. OP1 ;

[0034] The gate of the MOS transistor M3 inputs a clock signal φ2B, and the gate of the MOS transistor M11 inputs a clock signal φ2;

[0035] The two input terminals of the common mode feedback circuit CMFB are respectively connected to the operational amplifier A 2,3 The first output terminal V OP2 and the second output terminal V ON2 The first terminal input of the switch K19 is connected to the common mode voltage input terminal V CM , the second end is connected to the gate of the MOS tube M2 and the gate of the MOS tube M10; the first end of the switch K20 is connected to the output end of the common mode feedback circuit CMFB, and the second end is connected to the gate of the MOS tube M2;

[0036] The switch K19 is controlled by the clock signal CLKS, and the switch K20 is controlled by the clock signal CLKSB.

[0037] In one embodiment of the present invention, the clock signal φ2B and the clock signal φ2 are opposite signals, and the clock signal CLKS and the clock signal CLKSB are opposite signals.

[0038] In one embodiment of the present invention, the operational amplifier A 2,3 It includes MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, switch S1 and switch S2, wherein:

[0039] The source of the MOS tube M13, the source of the MOS tube M17, the source of the MOS tube M21 and the source of the MOS tube M25 are all connected to the power supply terminal VDD, and the drain of the MOS tube M13, the gate of the MOS tube M14, the gate of the MOS tube M15 and the drain of the MOS tube M16 are all connected to the operational amplifier A 2,3 The second output terminal V ON2 The gate of the MOS tube M13 is connected to the drain of the MOS tube M14, the drain of the MOS tube M17, the drain of the MOS tube M19, and the source of the MOS tube M18; the gate of the MOS tube M16 is connected to the drain of the MOS tube M15, the drain of the MOS tube M20, the drain of the MOS tube M18, and the source of the MOS tube M19;

[0040] The source of the MOS tube M14 and the source of the MOS tube M15 are both connected to the common mode voltage input terminal V CM The gate of the MOS tube M17 is connected to the gate of the MOS tube M20 and serves as the operational amplifier A 2,3 The second output terminal V IN2 The first terminal of the switch S1 is connected to the common mode voltage input terminal V CM The second end is connected to the gate of the MOS tube M17, and the gate of the MOS tube M18 inputs the first bias voltage V BL , the gate of the MOS tube M19 inputs the second bias voltage V BH , the source of the MOS tube M16, the source of the MOS tube M20, the source of the MOS tube M24 and the source of the MOS tube M28 are all connected to the ground terminal GND;

[0041] The drain of the MOS tube M25, the gate of the MOS tube M26, the gate of the MOS tube M27 and the drain of the MOS tube M28 are all connected to the operational amplifier A 2,3 The first output terminal V OP2 The gate of the MOS tube M25 is connected to the drain of the MOS tube M26, the drain of the MOS tube M21, the drain of the MOS tube M22, and the source of the MOS tube M23; the gate of the MOS tube M28 is connected to the drain of the MOS tube M27, the drain of the MOS tube M23, the drain of the MOS tube M24, and the source of the MOS tube M22;

[0042] The source of the MOS transistor M26 and the source of the MOS transistor M27 are both connected to the common mode voltage input terminal V CM The gate of the MOS tube M21 is connected to the gate of the MOS tube M24 and serves as the operational amplifier A2,3 The first output terminal V IP2 The first end of the switch S2 is connected to the common mode voltage input terminal V CM The second end is connected to the gate of the MOS tube M21, and the gate of the MOS tube M23 inputs the first bias voltage V BL The gate of the MOS tube M22 inputs the second bias voltage V BH .

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] 1. The present invention proposes a high-energy-efficiency thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter, comprising a first sampling branch and a second sampling branch, wherein the first sampling branch is a top plate sampling, used for quantizing the MSB bit of the input sampling signal after the sampling clock signal becomes a low level for a predetermined time; the second sampling branch is a bottom plate sampling, used for directly quantizing the MSB bit of the input sampling signal after the sampling clock signal becomes a low level, and the second sampling branch is also used for quantizing the remaining bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the MSB bit quantization. By combining the top plate and bottom plate sampling technologies, one bit of quantization time budget is saved, so that the time allocated to the margin amplification is increased, the linearity of the system is improved, and the amplitude attenuation problem and the insufficient time utilization problem caused by the bottom plate technology are solved.

[0045] 2. The present invention uses variable bandwidth technology to change the bandwidth of the first-stage operational amplifier (i.e., operational amplifier A1) as its functional requirements change, which can greatly improve the signal-to-noise ratio under the premise of slightly increasing power consumption, thereby solving the trade-off problem between the average power of residual thermal noise and power consumption.

[0046] 3. The present invention allows the feedback capacitor to participate in the sampling process, thereby alleviating the amplitude attenuation problem caused by bottom plate sampling and effectively improving the signal-to-noise ratio of the system.

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a module schematic diagram of a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise elimination provided by an embodiment of the present invention;

[0049] Figure 2 It is a structural schematic diagram of a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise elimination provided by an embodiment of the present invention;

[0050] Figure 3It is a working timing diagram of a thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter provided by an embodiment of the present invention;

[0051] Figure 4 The present invention provides a circuit diagram of a fully differential variable bandwidth ring amplifier. DETAILED DESCRIPTION

[0052] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise elimination proposed by the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0053] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0055] Embodiment 1

[0056] In order to solve the above problems, the present invention proposes a high-efficiency thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter, and uses the bottom plate and top plate sampling technology at the same time to enable the ADC to quantize the MSB (highest bit) of the input signal during the signal flipping process, thereby reducing the time budget occupied; the input signal is sampled by the feedback capacitor in the MDAC to alleviate the signal amplitude attenuation problem; and a variable bandwidth fully differential ring amplifier is proposed to solve the compromise problem between bandwidth and power consumption. At the same time, due to the small capacitance of the sampling capacitor in this technology, the signal sampled by the bottom plate technology will be attenuated due to the influence of parasitic capacitance. In order to alleviate the amplitude attenuation phenomenon, the lower plate of the feedback capacitor in this patent is connected to the input signal when the sampling clock is at a high level and also participates in the sampling process. After the sampling is completed, in the quantization stage, the lower plate of the feedback capacitor is connected to VCM, thereby avoiding the amplitude attenuation problem.

[0057] See also Figure 1 , Figure 1 It is a module schematic diagram of a thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter provided by an embodiment of the present invention. The analog-to-digital converter includes a first sampling branch and a second sampling branch, wherein the first sampling branch is a top plate sampling, which is used to quantize the MSB bit of the input sampling signal after the sampling clock signal CLKS becomes a low level for a predetermined time; the second sampling branch is a bottom plate sampling, which is used to directly quantize the MSB bit of the input sampling signal after the sampling clock signal becomes a low level, and the second sampling branch also quantizes the remaining bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the quantization of the MSB bit.

[0058] Specifically, the first sampling branch is for bottom plate sampling, and the second sampling branch is for top plate sampling. When the sampling clock signal becomes low level, the first sampling branch needs a certain time to start quantization, while the second sampling branch can quantize directly. Therefore, the second sampling branch directly quantizes the MSB bit of the sampled signal after the sampling clock signal becomes low level. When the first sampling branch completes the MSB bit quantization, the second sampling branch then completes the quantization of the remaining bits of the first-stage ADC according to the result of the first sampling branch.

[0059] For further information, see Figure 2 , Figure 2 1 is a schematic diagram of a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise elimination provided by an embodiment of the present invention. The first sampling branch of this embodiment includes a capacitor array C S1N 、Capacitor array C S1P , operational amplifier A1, operational amplifier A 2,3 , offset capacitor C N1 , offset capacitor C N2 , feedback capacitor CF1 , feedback capacitor C F2 , switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, switch K9, switch K10, switch K17 and switch K18.

[0060] Switch K1 and capacitor array C S1P Connect in series to the first differential input terminal V IP The first input terminal V of the operational amplifier A1 is connected to IP1 Between switch K2 and capacitor array C S1n In series with the second differential input V IN The second input terminal V IN1 Between the first differential input terminal V IP and the second differential input terminal V IN Used for input sampling signal; offset capacitor C N1 Connect to the first output terminal V of operational amplifier A1 OP1 With operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitor C N2 Connect to the second output terminal V of operational amplifier A1 ON1 With operational amplifier A 2,3 The second input terminal V IN2 Between; feedback capacitor C F1 and switch K5 are connected in series to the first input terminal V of operational amplifier A1. IP1 Between the operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2 The switch K10 is connected in series to the second input terminal V of the operational amplifier A1. IN2 Between the operational amplifier A 2,3 The first output terminal V OP2 between.

[0061] The first end of the switch K3 is connected to the first differential input terminal V IP The second end is connected to the feedback capacitor C F1 Between switch K5, the first end of switch K4 is connected to the common mode voltage input terminal V CM The second end is connected to the feedback capacitor C F1 and switch K5; the first end of switch K8 is connected to the second differential input terminal V IN The second end is connected to the feedback capacitor C F2 Between the switch K10, the first end of the switch K9 is connected to the common mode voltage input terminal V CM The second end is connected to the feedback capacitor C F2and switch K10; switch K6 is connected to the common mode voltage input terminal V CM With operational amplifier A 2,3 The first input terminal V IP2 The switch K7 is connected between the common mode voltage input terminal V CM With operational amplifier A 2,3 The second input terminal V IN2 Switch K17 is connected between the common mode voltage input terminal V CM The first input terminal V of the operational amplifier A1 is connected to IP1 The switch K18 is connected between the common mode voltage input terminal V CM The second input terminal V IN1 between; switch K1, switch K2, switch K3, switch K8, switch K6 and switch K7 are all controlled by the sampling clock signal CLKS, switch K4 and switch K9 are all controlled by the clock signal φ1, switch K5 and switch K10 are all controlled by the clock signal AMP, and switch K17 and switch K18 are all controlled by the clock signal CLKSE.

[0062] Furthermore, the first sampling branch further includes a switch K11 and a switch K12, wherein the switch K11 is connected to the operational amplifier A 2,3 The second output terminal V ON2 and the first input terminal of the subsequent ADC; the switch K12 is connected to the operational amplifier A 2,3 The first output terminal V OP2 and the second input terminal of the subsequent ADC; the switch K11 and the switch K12 are both controlled by the clock signal AMP.

[0063] When the sampling clock signal CLKS changes to a low level, the clock signal φ1 changes to a high level, and when the clock signal φ1 changes to a low level, the clock signal AMP changes to a high level; the sum of the duration of the clock signal φ1 being at a high level and the duration of the clock signal AMP being at a high level is equal to the duration of the sampling clock signal CLKS being at a low level. The clock signal CLKSE and the sampling clock signal CLKS trigger a high level at the same time, and the high level duration of the clock signal CLKSE is less than the high level duration of the sampling clock signal CLKS by a predetermined time.

[0064] Continue to see Figure 2 and Figure 3 , Figure 2 It is a structural schematic diagram of a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise elimination provided by an embodiment of the present invention; Figure 3 The second sampling branch of this embodiment includes comparator COM1, comparator COM2, capacitor array CS2N 、Capacitor array C S2P , switch K13, switch K14, switch K15, switch K16, logic control module, wherein switch K13 is connected to operational amplifier A 2,3 The first input terminal V IP2 The switch K14 is connected between the operational amplifier A and the first input terminal of the comparator COM1. 2,3 The second input terminal V IN2 and the second input terminal of the comparator COM1; the switch K15 is connected to the first differential input terminal V IP The switch K16 is connected between the second differential input terminal V IN and the second input terminal of the comparator COM2; capacitor array C S2P Connected between the ground terminal and the first input terminal of the comparator COM2, the capacitor array C S2N The output end of the comparator COM1 is connected to the first input end of the logic control module, and the output end of the comparator COM2 is connected to the second input end of the logic control module; the output end of the logic control module is connected to the capacitor array C S1N and capacitor array C S1P , used to change the capacitor array C according to the output results of comparator COM1 and comparator COM2 S1N and capacitor array C S1P The voltage connected to the lower plate of the corresponding capacitor; switch K13, switch K14, switch K15 and switch K16 are all controlled by the sampling clock signal CLKS.

[0065] Specifically, during the SAR ADC successive quantization process, each comparison result of comparator COM1 and comparator COM2 will be stored in the corresponding register in the logic control module (SAR LOGIC), and the output of each register will be connected to the capacitor array C S1N and capacitor array C S1P The working principle is as follows: after the comparison between comparator COM1 and comparator COM2 is completed, the comparison result is written into the corresponding register in the logic control module (SAR LOGIC), thereby changing the capacitor array C S1N and capacitor array C S1P The voltage on the capacitor array changes according to the potential connected to the lower plate of the corresponding capacitor. This voltage difference will then be compared by the comparator, and the cycle will be repeated until all quantization is completed.

[0066] For further information, see Figure 4 , Figure 4A fully differential variable bandwidth ring amplifier (including an operational amplifier A1 and an operational amplifier A2) provided in an embodiment of the present invention 2,3 ). The operational amplifier A1 includes MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, a common mode feedback circuit, a switch K19 and a switch K20.

[0067] The source of MOS tube M1, the source of MOS tube M2, the source of MOS tube M3 and the source of MOS tube M4 are all connected to the power supply terminal VDD, the drain of MOS tube M1, the drain of MOS tube M2, the drain of MOS tube M3, the drain of MOS tube M4 and the source of MOS tube M5 are all connected to the source of MOS tube M6; the gate of MOS tube M5 is connected to the gate of MOS tube M7 and serves as the first input terminal VDD of operational amplifier A1. IP1 The drain of MOS tube M5 is connected to the drain of MOS tube M7 and serves as the second output terminal V of operational amplifier A1. ON1 The gate of MOS tube M6 is connected to the gate of MOS tube M8 and serves as the second input terminal V of operational amplifier A1. IN1 , the drain of MOS tube M6 is connected to the drain of MOS tube M6 and serves as the first output terminal V of operational amplifier A1 OP1 .

[0068] The source of MOS tube M7 is connected to the source of MOS tube M8, the drain of MOS tube M9, the drain of MOS tube M10, the drain of MOS tube M11 and the drain of MOS tube M12 are all connected to the ground terminal; the gate of MOS tube M1 and the gate of MOS tube M9 are both connected to the second output terminal V of operational amplifier A1. ON1 The gate of MOS tube M4 and the gate of MOS tube M12 are both connected to the first output terminal V of operational amplifier A1. OP1 ; The gate of the MOS tube M3 inputs the clock signal φ2B, and the gate of the MOS tube M11 inputs the clock signal φ2.

[0069] The two input terminals of the common-mode feedback circuit CMFB are connected to the operational amplifier A 2,3 The first output terminal V OP2 and the second output terminal V ON2 , the first end of switch K19 inputs the common mode voltage V CMThe first end of the switch K20 is connected to the output end of the common-mode feedback circuit CMFB, and the second end is connected to the gate of the MOS tube M2 and the gate of the MOS tube M10; the first end of the switch K20 is connected to the output end of the common-mode feedback circuit CMFB, and the second end is connected to the gate of the MOS tube M2; the switch K19 is controlled by the clock signal CLKS, and the switch K20 is controlled by the clock signal CLKSB. The clock signal φ2B and the clock signal φ2 are opposite signals, and the clock signal CLKS and the clock signal CLKSB are opposite signals.

[0070] Operational Amplifier A 2,3 It includes MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, switch S1 and switch S2.

[0071] The source of MOS tube M13, the source of MOS tube M17, the source of MOS tube M21 and the source of MOS tube M25 are all connected to the power supply terminal VDD, and the drain of MOS tube M13, the gate of MOS tube M14, the gate of MOS tube M15 and the drain of MOS tube M16 are all connected to the operational amplifier A 2,3 The second output terminal V ON2 The gate of MOS tube M13 is connected to the drain of MOS tube M14, the drain of MOS tube M17, the drain of MOS tube M19 and the source of MOS tube M18; the gate of MOS tube M16 is connected to the drain of MOS tube M15, the drain of MOS tube M20, the drain of MOS tube M18 and the source of MOS tube M19; the source of MOS tube M14 and the source of MOS tube M15 are both input with common mode voltage V CM The gate of MOS tube M17 is connected to the gate of MOS tube M20 and serves as an operational amplifier A 2,3 The second output terminal V IN2 , the first end of switch S1 inputs the common mode voltage V CM The second end is connected to the gate of the MOS tube M17, and the gate of the MOS tube M18 inputs the first bias voltage V BL , the gate of MOS tube M19 inputs the second bias voltage V BH The source of the MOS tube M16, the source of the MOS tube M20, the source of the MOS tube M24 and the source of the MOS tube M28 are all connected to the ground terminal GND.

[0072] The drain of MOS tube M25, the gate of MOS tube M26, the gate of MOS tube M27 and the drain of MOS tube M28 are all connected to operational amplifier A 2,3 The first output terminal V OP2The gate of MOS tube M25 is connected to the drain of MOS tube M26, the drain of MOS tube M21, the drain of MOS tube M22 and the source of MOS tube M23; the gate of MOS tube M28 is connected to the drain of MOS tube M27, the drain of MOS tube M23, the drain of MOS tube M24 and the source of MOS tube M22; the source of MOS tube M26 and the source of MOS tube M27 are both input with common mode voltage V CM The gate of MOS tube M21 is connected to the gate of MOS tube M24 and serves as an operational amplifier A. 2,3 The first output terminal V IP2 , the first end of switch S2 inputs the common mode voltage V CM The second end is connected to the gate of the MOS tube M21, and the gate of the MOS tube M23 inputs the first bias voltage V BL , the gate of MOS tube M22 inputs the second bias voltage V BH .

[0073] The working principle of the analog-to-digital converter is:

[0074] Combination Figure 3 and Figure 4 As shown, initially, when the clock signals CLKS, CLKSE, and φ2 are at a high level, switches K1, K2, K6, K7, K15, K16, K3, K8, K19, and K20 are closed at the same time, and switches K4, K5, K9, K10, K11, and K12 are opened, and the signal is transmitted by the first sampling branch, the second sampling branch, and the feedback capacitor C F1 And the feedback capacitor C F2 When CLKSE changes from high level to low level, K19 and K20 are disconnected, and the noise information is stored in the capacitor array C S1N and capacitor array C S1P At this time, the operational amplifier A1 amplifies the noise signal and stores it in the offset capacitor C N1 and offset capacitor C N2 At this time, since the MOS tubes M3 and M11 are in the on state, a large current flows through the first stage of the operational amplifier (operational amplifier A1), and the operational amplifier A1 is in a large bandwidth working mode, which accelerates the sampling and amplification of the noise. When the storage of the noise is completed and the clock φ2 becomes a low level, the MOS tubes M3 and M11 are in the off state, a small current flows through the first stage of the operational amplifier, and the operational amplifier works in a small bandwidth mode to reduce the power consumption of the operational amplifier.

[0075] When the clock signal CLKS becomes a low level, switches K1, K2, K15, K16, K3, K6, K7, and K8 are disconnected. In the traditional thermal noise elimination structure, bottom plate sampling is adopted. Since bottom plate sampling needs a certain time to complete the voltage flipping after the sampling clock signal CLKS becomes a low level before quantization can be started, the voltage flipping process occupies a certain time budget. In order to overcome this problem, the analog-to-digital converter of the present invention adopts two-way sampling, including a first sampling branch and a second sampling branch. The added second sampling branch is top plate sampling. When the first sampling branch (bottom plate sampling branch) is still in the flipping process, the second sampling branch (top plate sampling branch) first performs the quantization of the MSB bit, making full use of the flipping time. Then, after the first sampling branch completes the flipping, quantization is continued.

[0076] Compared with the traditional architecture, the architecture of the present invention can save the time budget of one quantization. The quantization process is as follows: after the clock signal CLKS becomes low level, the comparator COM2 first completes the quantization of the MSB bit of the input sampling signal, and the quantized result is written into the first register of the logic control module, and then the capacitor array C is changed. S1N and capacitor array C S1P The voltage on the capacitor array changes accordingly, and this voltage difference is then compared by the comparator COM1. The comparison result of the comparator COM1 is written into the second register of the logic control module, and the capacitor array C continues to change. S1N and capacitor array C S1P The potential of the lower plate of the corresponding capacitor is connected, and the cycle repeats until the comparator COM1 completes the quantization of all bits. At the same time, when the sampling clock signal CLKS becomes low, the clock φ1 becomes high, and the switches K4 and K9 are closed, and the feedback capacitor C F1 and feedback capacitor C F2 The lower board is connected to the common mode voltage V CM When the quantization stage is over, clock φ1 becomes low level and clock φ2 becomes high level. At this time, switches K5, K10, K11, and K12 are closed, and operational amplifier A1 and operational amplifier A 2,3 The residual information is amplified and transmitted to the back-end ADC.

[0077] As mentioned above, in the traditional thermal noise elimination technology, after sampling, a signal flipping process will be experienced before quantization. In order to make full use of the time of the signal flipping process, the present invention adds a second sampling branch, which obtains the input signal at time ts through bottom plate sampling, and quantizes the MSB bit of the input signal after sampling. Since the second sampling branch only quantizes the MSB bit of the sampled signal, the capacitor array C S2N and capacitor array C S2PThe total capacitance value of can be appropriately small. Although the increase of sampling noise may cause MSB bit comparison error, this error can be eliminated by the inter-stage redundancy design. S1N and capacitor array C S1P After completing the signal flipping step, the second sampling branch has completed the quantization of the MSB bit, so the first sampling branch can directly quantize the second bit using the quantization result of the MSB bit of the second sampling branch, thereby reducing time waste.

[0078] Furthermore, assuming that the feedback capacitor C F1 and feedback capacitor C F2 Does not participate in the sampling process, because the capacitor array C S1N and capacitor array C S1P There are feedback capacitors and parasitic capacitors at the upper plate, with the first differential input terminal V IP Taking the input signal as an example, the signal amplitude actually sampled by the analog-to-digital converter is:

[0079]

[0080] Among them, C PP represents the parasitic capacitance of the first differential input terminal.

[0081] It can be seen that the amplitude of the signal has been attenuated, resulting in the loss of fundamental wave energy. In order to alleviate the above phenomenon, Figure 2 The circuit shown and Figure 3 As shown in the timing, when the clock signal CLKS is high, the input signal is connected to the capacitor array C S1N and capacitor array C S1P In addition to the lower plate, a feedback capacitor C is also connected F1 and feedback capacitor C F2 When Φ1 is high, the capacitor array C S1N and capacitor array C S1P The lower plate of the common mode voltage V CM , with the first differential input terminal V IP The input signal, the sampled signal amplitude is:

[0082]

[0083] It can be seen that the feedback capacitor C F1 and feedback capacitor C F2 After adding the sampling operation, the attenuation problem of the input signal amplitude is alleviated and the loss of fundamental wave energy is reduced.

[0084] In addition, in order to solve the compromise between bandwidth and power consumption in traditional thermal noise elimination technology, the present invention proposes a fully differential variable bandwidth ring amplifier. Variable bandwidth technology is used at the first stage of the operational amplifier, and the bandwidth is changed by adjusting the current of the first stage of the operational amplifier at different times to cope with different working scenarios, thereby achieving high energy efficiency.

[0085] correspond Figure 4 In the timing of the upper right corner, in the △t (t1~t3) time period, the bandwidth of the first stage of the op amp is adjustable. In the △t1 (t1~t2) time period, Φ2 is at a high level, at this time M3 and M4 are turned on, the current flowing through the first stage of the op amp is a large current, the bandwidth of the first stage of the op amp increases, and its establishment of sampling thermal noise is accelerated; in the △t2 (t2~t3) time period, Φ2 drops to a low level, so that M3 and M4 are turned off, the current flowing through the first stage of the op amp is a small current, and the bandwidth of the first stage of the op amp is reduced to meet the bandwidth requirements in the residual amplification process, thereby improving the energy efficiency ratio of the circuit.

[0086] In the time period of △t (t1~t3) w p is a time-varying function (in the design w p1 Greater than w p2 )

[0087] w p =w p1 (t∈Δt1)

[0088] w p =w p2 (t∈Δt2)

[0089] Among them, w p The general notation for the bandwidth of operational amplifier A1, w p1 represents the bandwidth in the time period Δt1, w p2 It represents the bandwidth in the time period of Δt2.

[0090] Then the equivalent bandwidth of the first stage of the op amp during the entire △t time can be expressed as the following formula.

[0091]

[0092] Comparing the variable bandwidth to the constant bandwidth, the ratio of the equivalent input thermal noise power is:

[0093]

[0094] in, It represents the thermal noise power equivalent to the residual at the input end under variable bandwidth. It represents the thermal noise power equivalent to the residual at the input end under the condition of constant bandwidth.

[0095] It can be seen from the above formula that the average power of the sampled thermal noise can be significantly reduced by simply increasing the bandwidth of the first stage of the operational amplifier within the time period △t1 (t1~t2), while making the first stage of the operational amplifier have a high energy efficiency ratio.

[0096] The present invention proposes a high-energy-efficiency thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter, comprising a first sampling branch and a second sampling branch, wherein the first sampling branch is a top plate sampling, used for quantizing the MSB bit of the input sampling signal after the sampling clock signal becomes a low level for a predetermined time; the second sampling branch is a bottom plate sampling, used for directly quantizing the MSB bit of the input sampling signal after the sampling clock signal becomes a low level, and the second sampling branch is also used for quantizing the remaining bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the MSB bit quantization. By combining the top plate and bottom plate sampling technologies, one bit of quantization time budget is saved, so that the time allocated to the margin amplification is increased, the linearity of the system is improved, and the amplitude attenuation problem and the insufficient time utilization problem caused by the bottom plate technology are solved.

[0097] The present invention uses variable bandwidth technology to change the bandwidth of the first-stage operational amplifier (i.e., operational amplifier A1) according to its functional requirements, which can greatly improve the signal-to-noise ratio under the premise of slightly increasing power consumption, and solve the trade-off problem between the average power of residual thermal noise and power consumption. The present invention allows the feedback capacitor to participate in the sampling process, which reduces the amplitude attenuation problem caused by bottom plate sampling and effectively improves the signal-to-noise ratio of the system.

[0098] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0099] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0100] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter, characterized in that: It includes a first sampling branch and a second sampling branch, wherein: The first sampling branch is a top plate sampling, which is used to quantize the MSB bit of the input sampling signal after the sampling clock signal becomes low level for a predetermined time; The second sampling branch is a bottom plate sampling, which is used to directly quantize the MSB bit of the input sampling signal after the sampling clock signal becomes a low level, and the second sampling branch also quantizes the remaining bits of the sampling signal according to the quantization result of the first sampling branch after the first sampling branch completes the MSB bit quantization.

2. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 1, characterized in that: The first sampling branch includes a capacitor array C S1N 、Capacitor array C S1P , operational amplifier A1, operational amplifier A 2,3 , offset capacitor C N1 , offset capacitor C N2 , feedback capacitor C F1 , feedback capacitor C F2 , switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, switch K9, switch K10, switch K17 and switch K18, wherein, The switch K1 and the capacitor array C S1P Connect in series to the first differential input terminal V IP The first input terminal V of the operational amplifier A1 is IP1 Between the switch K2 and the capacitor array C S1n In series with the second differential input V IN The second input terminal V of the operational amplifier A1 IN1 Between the first differential input terminal V IP and the second differential input terminal V IN Used to input sampling signal; The offset capacitor C N1 Connect the first output terminal V of the operational amplifier A1 to OP1 With the operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitor C N2 Connect the second output terminal V of the operational amplifier A1 to ON1 With the operational amplifier A 2,3 The second input terminal V IN2 between; The feedback capacitor C F1 The switch K5 is connected in series with the first input terminal V of the operational amplifier A1. IP1 between the operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2 The switch K10 is connected in series with the second input terminal V of the operational amplifier A1. IN2 between the operational amplifier A 23 The first output terminal V OP2 between; The first end of the switch K3 is connected to the first differential input terminal V IP , the second end is connected to the feedback capacitor C F1 The first end of the switch K4 is connected to the common mode voltage input terminal V CM , the second end is connected to the feedback capacitor C F1 and the switch K5; the first end of the switch K8 is connected to the second differential input terminal V IN , the second end is connected to the feedback capacitor C F2 Between the switch K10, the first end of the switch K9 is connected to the common mode voltage input terminal V CM , the second end is connected to the feedback capacitor C F2 Between the switch K10; The switch K6 is connected to the common mode voltage input terminal V CM With the operational amplifier A 2,3 The first input terminal V IP2 The switch K7 is connected to the common mode voltage input terminal V CM With the operational amplifier A 2,3 The second input terminal V IN2 between; The switch K17 is connected to the common mode voltage input terminal V CM The first input terminal V of the operational amplifier A1 is IP1 The switch K18 is connected to the common mode voltage input terminal V CM The second input terminal V of the operational amplifier A1 IN1 between; The switches K1, K2, K3, K8, K6 and K7 are all controlled by the sampling clock signal CLKS, the switches K4 and K9 are all controlled by the clock signal φ1, the switches K5 and K10 are all controlled by the clock signal AMP; the switches K17 and K18 are all controlled by the clock signal CLKSE.

3. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that: The first sampling branch further includes a switch K11 and a switch K12, wherein: The switch K11 is connected to the operational amplifier A 2,3 The second output terminal V ON2 and the first input terminal of the subsequent ADC; the switch K12 is connected to the operational amplifier A 2,3 The first output terminal V OP2 Between the second input terminal of the subsequent ADC; The switch K11 and the switch K12 are both controlled by the clock signal AMP.

4. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 3, characterized in that: When the sampling clock signal CLKS changes to a low level, the clock signal φ1 changes to a high level, and when the clock signal φ1 changes to a low level, the clock signal AMP changes to a high level; The sum of the duration that the clock signal φ1 is at a high level and the duration that the clock signal AMP is at a high level is equal to the duration that the sampling clock signal CLKS is at a low level; The clock signal CLKSE and the sampling clock signal CLKS are triggered to high level at the same time, and the high level duration of the clock signal CLKSE is shorter than the high level duration of the sampling clock signal CLKS by a predetermined time.

5. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that: The second sampling branch includes a comparator COM1, a comparator COM2, a capacitor array C S2N 、Capacitor array C S2P , switch K13, switch K14, switch K15, switch K16, logic control module, wherein, The switch K13 is connected to the operational amplifier A 2,3 The first input terminal V IP2 The switch K14 is connected between the first input terminal of the comparator COM1 and the first input terminal of the comparator COM1. 2,3 The second input terminal V IN2 and a second input terminal of the comparator COM1; The switch K15 is connected to the first differential input terminal V IP The switch K16 is connected between the second differential input terminal V IN and a second input terminal of the comparator COM2; The capacitor array C S2P is connected between the ground terminal and the first input terminal of the comparator COM2, the capacitor array C S2N connected between the ground terminal and the second input terminal of the comparator COM2, the output terminal of the comparator COM1 is connected to the first input terminal of the logic control module, and the output terminal of the comparator COM2 is connected to the second input terminal of the logic control module; The output end of the logic control module is connected to the capacitor array C S1N and the capacitor array C S1P , used to change the capacitor array C according to the output results of the comparator COM1 and the comparator COM2 S1N and the capacitor array C S1P The voltage connected to the lower plate of the corresponding capacitor; The switch K13 , the switch K14 , the switch K15 , and the switch K16 are all controlled by the sampling clock signal CLKS.

6. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that: The operational amplifier A1 includes MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, a common mode feedback circuit, a switch K19 and a switch K20, wherein: The source of the MOS tube M1, the source of the MOS tube M2, the source of the MOS tube M3 and the source of the MOS tube M4 are all connected to the power supply terminal VDD, and the drain of the MOS tube M1, the drain of the MOS tube M2, the drain of the MOS tube M3, the drain of the MOS tube M4 and the source of the MOS tube M5 are all connected to the source of the MOS tube M6; The gate of the MOS transistor M5 is connected to the gate of the MOS transistor M7 and serves as the first input terminal V of the operational amplifier A1. IP1 The drain of the MOS tube M5 is connected to the drain of the MOS tube M7 and serves as the second output terminal V of the operational amplifier A1. ON1 The gate of the MOS tube M6 is connected to the gate of the MOS tube M8 and serves as the second input terminal V of the operational amplifier A1. IN1 The drain of the MOS tube M6 is connected to the drain of the MOS tube M6 and serves as the first output terminal V of the operational amplifier A1. OP1 ; The source of the MOS tube M7 is connected to the source of the MOS tube M8, and the drain of the MOS tube M9, the drain of the MOS tube M10, the drain of the MOS tube M11 and the drain of the MOS tube M12 are all connected to the ground end; The gate of the MOS tube M1 and the gate of the MOS tube M9 are both connected to the second output terminal V of the operational amplifier A1. ON1 The gate of the MOS tube M4 and the gate of the MOS tube M12 are both connected to the first output terminal V of the operational amplifier A1. OP1 ; The gate of the MOS transistor M3 inputs a clock signal φ2B, and the gate of the MOS transistor M11 inputs a clock signal φ2; The two input terminals of the common mode feedback circuit CMFB are respectively connected to the operational amplifier A 2,3 The first output terminal V OP2 and the second output terminal V ON2 The first terminal input of the switch K19 is connected to the common mode voltage input terminal V CM , the second end is connected to the gate of the MOS tube M2 and the gate of the MOS tube M10; the first end of the switch K20 is connected to the output end of the common mode feedback circuit CMFB, and the second end is connected to the gate of the MOS tube M2; The switch K19 is controlled by the clock signal CLKS, and the switch K20 is controlled by the clock signal CLKSB.

7. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 6, characterized in that: The clock signal φ2B and the clock signal φ2 are opposite signals, and the clock signal CLKS and the clock signal CLKSB are opposite signals.

8. The thermal noise elimination high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that: The operational amplifier A 2,3 It includes MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, switch S1 and switch S2, wherein: The source of the MOS tube M13, the source of the MOS tube M17, the source of the MOS tube M21 and the source of the MOS tube M25 are all connected to the power supply terminal VDD, and the drain of the MOS tube M13, the gate of the MOS tube M14, the gate of the MOS tube M15 and the drain of the MOS tube M16 are all connected to the operational amplifier A 2,3 The second output terminal V ON2 The gate of the MOS tube M13 is connected to the drain of the MOS tube M14, the drain of the MOS tube M17, the drain of the MOS tube M19, and the source of the MOS tube M18; the gate of the MOS tube M16 is connected to the drain of the MOS tube M15, the drain of the MOS tube M20, the drain of the MOS tube M18, and the source of the MOS tube M19; The source of the MOS tube M14 and the source of the MOS tube M15 are both connected to the common mode voltage input terminal V CM The gate of the MOS tube M17 is connected to the gate of the MOS tube M20 and serves as the operational amplifier A 23 The second output terminal V IN2 The first terminal of the switch S1 is connected to the common mode voltage input terminal V CM The second end is connected to the gate of the MOS tube M17, and the gate of the MOS tube M18 inputs the first bias voltage V BL , the gate of the MOS tube M19 inputs the second bias voltage V BH , the source of the MOS tube M16, the source of the MOS tube M20, the source of the MOS tube M24 and the source of the MOS tube M28 are all connected to the ground terminal GND; The drain of the MOS tube M25, the gate of the MOS tube M26, the gate of the MOS tube M27 and the drain of the MOS tube M28 are all connected to the operational amplifier A 2,3 The first output terminal V OP2 The gate of the MOS tube M25 is connected to the drain of the MOS tube M26, the drain of the MOS tube M21, the drain of the MOS tube M22, and the source of the MOS tube M23; the gate of the MOS tube M28 is connected to the drain of the MOS tube M27, the drain of the MOS tube M23, the drain of the MOS tube M24, and the source of the MOS tube M22; The source of the MOS transistor M26 and the source of the MOS transistor M27 are both connected to the common mode voltage input terminal V CM The gate of the MOS tube M21 is connected to the gate of the MOS tube M24 and serves as the operational amplifier A 2,3 The first output terminal V IP2 The first end of the switch S2 is connected to the common mode voltage input terminal V CM The second end is connected to the gate of the MOS tube M21, and the gate of the MOS tube M23 inputs the first bias voltage V BL The gate of the MOS tube M22 inputs the second bias voltage V BH .

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