Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region and a first region; the first region is arranged on the first surface; the well region is arranged on one side of the first region away from the first surface; the first surface is also provided with a groove, and the groove comprises a first sub-groove and a second sub-groove; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; the pressure-resistant filling layer is located in the second sub-trench; the gate structure is located in the first sub-trench; the source electrode is located on the first surface. According to the technical scheme provided by the embodiment of the invention, the specific on-resistance and the peak electric field at the bottom of the gate structure are reduced, so that the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity, making third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride a research hotspot for power semiconductor devices, and silicon carbide devices are given high expectations in high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission.

[0003] Currently, MOSFET semiconductor devices including trench gate structures cannot simultaneously reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, resulting in relatively poor electrical performance of the semiconductor devices. Summary of the invention

[0004] The present invention provides a semiconductor device, a power module, a power conversion circuit and a vehicle, so as to reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device.

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface;

[0007] A pressure-resistant filling layer, located in the second sub-groove;

[0008] A gate structure, located in the first sub-trench;

[0009] A source electrode, located on the first surface;

[0010] The drain is located on the second surface.

[0011] Optionally, the semiconductor body further includes a second region, and the second region is arranged between the well region and the second surface;

[0012] The conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

[0013] Optionally, the semiconductor body includes a first drift layer and a second drift layer;

[0014] The second drift layer is located on a surface of the first drift layer; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body;

[0015] The second region is disposed in the first drift layer.

[0016] Optionally, the material of the voltage-resistant filling layer includes at least one of silicon oxide, silicon nitride and polysilicon.

[0017] Optionally, the second region includes at least two sub-regions, and the at least two sub-regions are spaced apart in a direction from the second surface to the first surface.

[0018] Optionally, a vertical projection of the pressure-resistant filling layer on the first surface is located within a vertical projection of the second area on the first surface;

[0019] The pressure-resistant filling layer is disposed on a side of the second region away from the second surface, or the pressure-resistant filling layer extends from a side of the second region away from the second surface to the second region.

[0020] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0021] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region; the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first region is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface;

[0022] forming a voltage-resistant filling layer in the second sub-groove;

[0023] forming a gate structure in the first sub-trench;

[0024] forming a source electrode on the first surface;

[0025] A drain electrode is formed on the second surface.

[0026] Optionally, providing a semiconductor body comprises:

[0027] providing the semiconductor body further comprising a second region, the second region being disposed between the well region and the second surface;

[0028] The conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

[0029] Optionally, providing a semiconductor body comprises:

[0030] providing a first drift layer;

[0031] forming a second region in the first drift layer;

[0032] forming a second drift layer on a surface of the first drift layer where the second region is arranged; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body;

[0033] forming a well region and a first region on a surface of the second drift layer away from the first drift layer;

[0034] A groove is formed on a surface of the second drift layer away from the first drift layer, the groove includes a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the bottom of the second sub-groove exposes the second region.

[0035] Optionally, forming the second region on the surface of the first drift layer includes: providing a first drift layer, and forming a second region including at least two sub-regions on the surface of the first drift layer, wherein the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

[0036] In a third aspect, an embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used to carry the semiconductor device.

[0037] In a fourth aspect, an embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0038] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0039] In a fifth aspect, an embodiment of the present invention provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0040] In the MOSFET semiconductor device provided by the embodiment of the present invention, the voltage-resistant filling layer is located at the bottom of the gate structure, which reduces the peak electric field at the bottom of the trench-type gate structure and prevents the gate structure from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source electrode as a trench-type source electrode structure to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate structure, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device.

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0044] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 6 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 7-10 yes Figure 6 The structural schematic diagram corresponding to each relevant step in the figure;

[0050] Fig.11 yes Figure 6 The flowchart included in S110;

[0051] Figure 12-14 yes Fig.11 The structural schematic diagram corresponding to each relevant step in the figure;

[0052] Figure 15-17 yes Fig.11 Schematic diagram of the process included in S1102. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or structures that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] Figure 1 It is a schematic diagram of the structure of a semiconductor device provided by the prior art. Figure 1As shown, the semiconductor device includes a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104 and a third region 105, the conductivity type of the first region 104 is opposite to the conductivity type of the well region 103, the conductivity type of the third region 105 is the same as the conductivity type of the well region 103, and the doping concentration of the third region 105 is greater than the doping concentration of the well region 103. The first surface 101 is provided with a gate trench T1 and a source trench T2. The semiconductor device also includes a gate structure 200, a source structure 300 and a drain 400. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the gate trench T1. The spacer insulating layer 203 is used to space the gate structure 200 and the source structure 300. The source structure 300 is located in the source trench T2 , and includes a source 301 , an ohmic contact layer 302 , a polysilicon filling layer 303 and a second insulating layer 304 .

[0056] Figure 1 The MOSFET semiconductor device shown is a double trench MOSFET semiconductor device, and the source structure 300 is located in the source trench T2. Although the setting of the source structure 300 can reduce the peak electric field at the first insulating layer 201 at the bottom of the gate structure 200, the source structure 300 occupies the area of ​​the semiconductor body 100, reduces the specific on-resistance of the semiconductor device, and makes the electrical performance of the semiconductor device relatively poor.

[0057] In order to reduce the specific on-resistance of a MOSFET semiconductor device and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0058] like Figure 2 As shown, Figure 21 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further comprises a well region 103 and a first region 104; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101; the first surface 101 is further provided with a trench T3, the trench T3 comprises a first sub-trench T4 and a second sub-trench T5, the first sub-trench T4 is arranged on the first surface 10 1, the second sub-trench T5 is connected to the first sub-trench T4, and the second sub-trench T5 is located between the first sub-trench T4 and the second surface 102; the conductivity type of the first region 104 is the same as and opposite to the conductivity type of the well region 103; the vertical projection of the second sub-trench T5 on the first surface 101 coincides with the vertical projection of the first sub-trench T4 on the first surface 101; the voltage-resistant filling layer 107 is located in the second sub-trench T5; the gate structure 200 is located in the first sub-trench T4; the source 305 is located on the first surface 101; the drain 400 is located on the second surface 102.

[0059] For example, Figure 2 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0060] In the MOSFET semiconductor device provided by the embodiment of the present invention, the voltage-resistant filling layer 107 is located at the bottom of the gate structure 200, which reduces the peak electric field at the bottom of the trench-type gate structure 200 and prevents the gate structure 200 from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as a trench-type source structure to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device.

[0061] Optionally, the thickness of the voltage-resistant filling layer 107 is greater than or equal to 0.5 micrometers and less than or equal to 8 micrometers. Optionally, the depth of the trench T3 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers.

[0062] Optionally, based on the above technical solution, the semiconductor body 100 also includes a second region 106, which is arranged between the well region 103 and the second surface 102; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103.

[0063] Specifically, at the bottom of the gate structure 200, the second sub-trench T5 where the voltage-resistant filling layer 107 is placed extends to the second region 106, the doping concentration of the second region 106 is greater than the doping concentration of the well region 103, and the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, that is, the drift layer between the second region 106 and the second surface 102 constitutes a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200.

[0064] Optionally, the thickness of the second region 106 is greater than or equal to 0.1 micrometers and less than or equal to 3 micrometers.

[0065] Optionally, the MOSFET semiconductor device further includes a third region 105 , and the conductivity type of the third region 105 is the same as the conductivity type of the well region 103 .

[0066] MOSFET semiconductor devices include N-type MOSFET semiconductor devices or P-type MOSFET semiconductor devices. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the third region 105 is a P+ doped region, the second region 106 is a P+ doped region, and the well region 103 is a P-well region.

[0067] The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the first sub-trench T4. The spacing insulating layer 203 is used to space the gate structure 200 and the source 305. The ohmic contact layer 302 enables the source 305 to form a good ohmic contact with the first region 104 and the third region 105. The material of the ohmic contact layer 302 includes one or more of metal Ni, an alloy or stack of metal Ti and metal Ni, an alloy or stack of metal Ni and metal Pt, metal Co, an alloy or stack of metal Ti and metal Al, and a stack of metal Ti and TiN.

[0068] Optionally, based on the above technical solution, Figure 2 As shown, the semiconductor body 100 includes a first drift layer 108 and a second drift layer 109 ; the second drift layer 109 is located on the surface of the first drift layer 108 ; the surface of the second drift layer 109 away from the first drift layer 108 is the first surface 101 of the semiconductor body 100 ; and the second region 106 is disposed in the first drift layer 108 .

[0069] Specifically, the second region 106 is disposed in the first drift layer 108, and can be directly prepared in the first drift layer 108 by an ion doping process before forming the second drift layer 109. Compared with the technical solution of forming the second region 106 on the first surface of the semiconductor body 100, the diffusion distance of the ion doping is reduced, and the difficulty of ion doping of the second region 106 is reduced. Among them, the ion doping process includes ion implantation, ion diffusion or vapor deposition and other processes.

[0070] Optionally, based on the above technical solution, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0071] like Figure 2 and Figure 3 As shown, Figure 3 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes silicon oxide. Figure 4 As shown, Figure 4 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes polysilicon. Figure 5 As shown, Figure 5 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes silicon nitride.

[0072] Specifically, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon, which increases the thickness of the dielectric layer at the bottom of the gate structure 200 , thereby further reducing the peak electric field at the bottom of the trench-type gate structure 200 .

[0073] Optionally, based on the above technical solution, Figure 3-Figure 5 As shown, the second region 106 includes at least two sub-regions 1061 , and the at least two sub-regions 1061 are arranged at intervals in a direction from the second surface 102 to the first surface 101 .

[0074] For example, Figure 3-Figure 5 As shown, the second region 106 includes three sub-regions 1061, the first drift layer 108 includes a first sub-drift layer 1081 and two second sub-drift layers 1082, and the three sub-regions 1061 are arranged at intervals in the direction from the second surface 102 to the first surface 101. The direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0075] Specifically, the more the number of the second sub-drift layers 1082 is, the more the number of the sub-regions 1061 is. In the process of preparing the sub-regions 1061 by ion doping on the surface where the first sub-drift layer 1081 and the second sub-drift layer 1082 are in contact and on the surface where the second sub-drift layer 1082 is away from the first sub-drift layer 1081, the shorter the diffusion distance of the ion doping is, the lower the difficulty of ion doping in the second region 106. In other embodiments, at least two sub-regions 1061 can also be arranged continuously in the direction from the second surface 102 to the first surface 101.

[0076] Optionally, based on the above technical solution, the vertical projection of the pressure-resistant filling layer 107 on the first surface 101 is located within the vertical projection of the second region 106 on the first surface 101; the pressure-resistant filling layer 107 is arranged on the side of the second region 106 away from the second surface 102, or, the pressure-resistant filling layer 107 extends from the side of the second region 106 away from the second surface 102 to the second region 106.

[0077] For example, Figure 2-Figure 5 , the pressure-resistant filling layer 107 extends from the side of the second region 106 away from the second surface 102 to the second region 106. In other embodiments, the pressure-resistant filling layer 107 may also be disposed only on the side of the second region 106 away from the second surface 102.

[0078] Specifically, the above technical solution enables the second region 106 to wrap the voltage-resistant filling layer 107 near the bottom of the second surface 102, or the second region 106 to wrap the voltage-resistant filling layer 107 near the bottom and part of the side of the second surface 102, and the second region 106 and the drift region between the second region 106 and the second surface 102 constitute a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200, or the peak electric field at the bottom and side of the trench-type gate structure 200 can be further reduced.

[0079] Optionally, based on the above technical solution, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0080] Specifically, the semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0081] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 6 As shown, Figure 6 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, and the method for manufacturing a semiconductor device comprises the following steps:

[0082] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is also provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface.

[0083] like Figure 7 As shown, a semiconductor body 100 is provided, and the semiconductor body 100 includes a first surface 101 and a second surface 102 that are arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101; the first surface 101 is also provided with a trench T3, and the trench T3 includes a first sub-trench T4 and a second sub-trench T5, the first sub-trench T4 is arranged on the first surface 101, the second sub-trench T5 is connected to the first sub-trench T4, and the second sub-trench T5 is located between the first sub-trench T4 and the second surface 102; the conductivity type of the first region 104 is the same as and opposite to the conductivity type of the well region 103; the vertical projection of the second sub-trench T5 on the first surface 101 coincides with the vertical projection of the first sub-trench T4 on the first surface 101.

[0084] Optionally, providing a semiconductor body comprises:

[0085] A semiconductor body is provided, which further includes a second region, wherein the second region is arranged between the well region and the second surface, and the second region and the well region are spaced apart from each other.

[0086] like Figure 7 As shown, a semiconductor body 100 is provided which also includes a second region 106 , which is arranged between the well region 103 and the second surface 102 ; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103 , and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103 .

[0087] For example, Figure 7As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0088] In other embodiments, the MOSFET semiconductor device further includes a third region 105 , and the conductivity type of the third region 105 is the same as the conductivity type of the well region 103 .

[0089] MOSFET semiconductor devices include N-type MOSFET semiconductor devices or P-type MOSFET semiconductor devices. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the third region 105 is a P+ doped region, the second region 106 is a P+ doped region, and the well region 103 is a P-well region.

[0090] S120 , forming a voltage-resistant filling layer in the second sub-trench.

[0091] like Figure 8 As shown, a voltage-resistant filling layer 107 is formed in the second sub-trench T5. Optionally, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0092] S130 , forming a gate structure in the first sub-trench.

[0093] like Fig. 9 As shown, a gate structure 200 is formed in the first sub-trench T4. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the first sub-trench T4. The spacer insulating layer 203 is used to separate the gate structure 200 and the source 305 formed subsequently.

[0094] S140 , forming a source on the first surface.

[0095] like Fig.10 As shown, a source electrode 305 is formed on the first surface 101 , wherein the ohmic contact layer 302 enables the source electrode 305 to form a good ohmic contact with the first region 104 and the third region 105 .

[0096] S150, forming a drain on the second surface.

[0097] like Figure 2As shown, a drain electrode 400 is formed on the second surface 102. The drain electrode 400 may include a stack of metal Ti, metal Ni, and metal Ag.

[0098] In the MOSFET semiconductor device obtained by the manufacturing method provided in the embodiment of the present invention, the voltage-resistant filling layer 107 is located at the bottom of the gate structure 200, which reduces the peak electric field at the bottom of the trench-type gate structure 200 and prevents the gate structure 200 from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as the area of ​​the semiconductor body occupied by the trench-type source structure to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device.

[0099] Optionally, when the semiconductor body 100 also includes the second region 106, at the bottom of the gate structure 200, the second sub-trench T5 for placing the voltage-resistant filling layer 107 extends to the second region 106, the doping concentration of the second region 106 is greater than the doping concentration of the well region 103, and the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, that is, the second region 106 and the drift region between the second region 106 and the second surface 102 constitute a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200.

[0100] Optionally, based on the above technical solution, Fig.11 As shown, Fig.11 yes Figure 6 The flowchart included in S110, S110 provides a semiconductor body including:

[0101] S1101 . Provide a first drift layer.

[0102] like Fig.12 As shown, a first drift layer 108 is provided. Fig.12 As shown, the first drift layer 108 is an epitaxial layer 20. In other embodiments of the present invention, the first drift layer 108 may also be a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0103] S1102 , forming a second region in the first drift layer.

[0104] like Fig.13 As shown, the second region 106 is formed in the first drift layer 108 by an ion doping process. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0105] S1103 , forming a second drift layer on a surface of the first drift layer where the second region is arranged; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body.

[0106] like Fig.14 As shown, a second drift layer 109 is formed on the surface of the first drift layer 108 where the second region 106 is disposed; a surface of the second drift layer 109 away from the first drift layer 108 is the first surface 101 of the semiconductor body 100. The second drift layer 109 may be an epitaxial layer.

[0107] S1104 , forming a well region and a first region on a surface of the second drift layer away from the first drift layer.

[0108] like Fig.14 As shown, the well region 103 and the first region 104 are formed on the surface of the second drift layer 109 away from the first drift layer 108 by an ion doping process. Optionally, a third region 105 may be formed on the surface of the second drift layer 109 away from the first drift layer 108 by an ion doping process, and the conductivity type of the third region 105 is the same as that of the well region 103.

[0109] S1105, forming a groove on a surface of the second drift layer away from the first drift layer, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove being arranged on the first surface, the second sub-groove being connected to the first sub-groove, and the bottom of the second sub-groove exposing the second region.

[0110] like Figure 7 As shown, a trench T3 is formed on the surface of the second drift layer 109 away from the first drift layer 108 by photolithography and etching processes, and the trench T3 includes a first sub-trench T4 and a second sub-trench T5. The first sub-trench T4 is arranged on the first surface 101, and the second sub-trench T5 is connected to the first sub-trench T4, and the bottom of the second sub-trench T5 exposes the second area 106.

[0111] Specifically, the second region 106 is disposed on the surface where the first drift layer 108 and the second drift layer 109 contact each other. Before forming the second drift layer 109, the second region 106 can be directly prepared by an ion doping process on the surface of the first drift layer 108. Compared with the technical solution of forming the second region 106 on the first surface of the semiconductor body 100, the diffusion distance of the ion doping is reduced, and the difficulty of ion doping of the second region 106 is reduced. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0112] Optionally, based on the above technical solution, S1102 forming a second region in the first drift layer includes:

[0113] A first drift layer is provided, and a second region including at least two sub-regions is formed in the first drift layer, wherein the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

[0114] like Figure 15-17 As shown, a first drift layer 108 is provided, and a second region 106 including at least two sub-regions 1061 is formed in the first drift layer 108 . The at least two sub-regions 1061 are arranged at intervals in a direction from the second surface 102 to the first surface 101 .

[0115] like Fig.15 As shown, a first drift sub-layer 1081 is provided. Fig.15 As shown, the first sub-drift layer 1081 is an epitaxial layer 20. In other embodiments of the present invention, the first sub-drift layer 1081 may also include a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0116] like Fig.15 As shown, the sub-region 1061 is formed on the surface of the first sub-drift layer 1081 by an ion doping process. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0117] like Fig.16 As shown, a first second sub-drift layer 1082 is formed on one side of the first sub-drift layer 1081 where the sub-region 1061 is provided. Fig.16 As shown, a second sub-drift layer 1082 is formed on one side of the first sub-drift layer 1081 where the sub-region 1061 is provided. The second sub-drift layer 1082 may be an epitaxial layer. At least one second sub-drift layer 1082 is located between the first sub-drift layer 1081 and the second drift layer 109 .

[0118] like Fig.17 As shown, after each formation of the second sub-drift layer 1082 , it also includes: forming a sub-region 1061 on the surface of the second sub-drift layer 1082 away from the first sub-drift layer 1081 ; at least two sub-regions 1061 spaced apart or continuously arranged in the direction from the second surface 102 to the first surface 101 constitute the second region 106 .

[0119] Exemplarily, the manufacturing method described above prepares a second region 106 including three sub-regions 1061, the first drift layer 108 includes a first sub-drift layer 1081 and two second sub-drift layers 1082, and the three sub-regions 1061 are arranged at intervals in the direction from the second surface 102 to the first surface 101. The direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0120] Specifically, the more the number of second sub-drift layers 1082 is, the more the number of sub-regions 1061 is. In the process of preparing the sub-region 1061 by ion doping on the surface where the first sub-drift layer 1081 and the second sub-drift layer 1082 are in contact and on the surface of the second sub-drift layer 1082 away from the first sub-drift layer 1081, the shorter the diffusion distance of the ion doping is, and the lower the difficulty of ion doping in the second region 106 is.

[0121] The embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device described in any embodiment of the present invention are not described in detail here.

[0122] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0123] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0124] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0126] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; A pressure-resistant filling layer, located in the second sub-groove; A gate structure, located in the first sub-trench; A source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The semiconductor body further includes a second region disposed between the well region and the second surface; The conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

3. The semiconductor device according to claim 2, characterized in that The semiconductor body includes a first drift layer and a second drift layer; The second drift layer is located on a surface of the first drift layer; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body; The second region is disposed in the first drift layer.

4. The semiconductor device according to claim 1, wherein: The material of the voltage-resistant filling layer includes at least one of silicon oxide, silicon nitride and polysilicon.

5. The semiconductor device according to claim 3, characterized in that The second region further includes at least two sub-regions, and the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

6. The semiconductor device according to claim 2, wherein: The vertical projection of the pressure-resistant filling layer on the first surface is located within the vertical projection of the second area on the first surface; The voltage-resistant filling layer is disposed on a side of the second region away from the second surface, or the voltage-resistant filling layer extends from a side of the semiconductor body close to the first surface to the second region.

7. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

8. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; forming a voltage-resistant filling layer in the second sub-groove; forming a gate structure in the first sub-trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: providing the semiconductor body further comprising a second region, the second region being disposed between the well region and the second surface; The conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: providing a first drift layer; forming a second region in the first drift layer; forming a second drift layer on a surface of the first drift layer where the second region is arranged; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body; forming a well region and a first region on a surface of the second drift layer away from the first drift layer; A groove is formed on a surface of the second drift layer away from the first drift layer, the groove includes a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the bottom of the second sub-groove exposes the second region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Providing a first drift layer, and forming a second region on a surface of the first drift layer comprises: A first drift layer is provided, and a second region including at least two sub-regions is formed on a surface of the first drift layer, wherein the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

12. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used for carrying the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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