Arm server starting method and arm server
By retaining only one on-chip ROM in the SOC of the ARM server and using the running program of the non-volatile memory storage processor, the problem of ROM occupancy of logical resources and bugs during the startup process of the ARM server in the prior art is solved, and the problem of difficult to fix is realized. The system startup is safe and reliable.
Patent Information
- Application Number
- CN202411285519.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-02-14
Smart Images
Figure CN119441125A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a server of ARM architecture, and in particular to starting the server of ARM architecture. Background Art
[0002] The ARM64 SOC used in ARM servers generally integrates multiple homogeneous or heterogeneous processing units on the chip, and each processing unit is integrated with on-chip ROM and on-chip RAM, so that after the system is cold-started, each processing unit can start from its own on-chip ROM. This has several disadvantages:
[0003] 1. Each processing unit needs to integrate on-chip ROM, which occupies the system's valuable logic resources and increases the chip area
[0004] 2. Since the ROM program cannot be burned and changed, once the SOC is taped out, the bugs in the ROM program are difficult to fix. Severe bugs may even endanger system security and affect the normal startup of the system.
[0005] Therefore, an arm server startup method that can solve the above problems is urgently needed. Summary of the invention
[0006] The purpose of the present invention is to provide an arm server startup method and an arm server, wherein the on-chip program is simplified and the startup process is safe and reliable.
[0007] In order to achieve the above-mentioned purpose, the present invention provides an arm server startup method, wherein a SOC has multiple processors, one of which is a first processor, and the remaining processors are second processors, the first processor has an on-chip ROM and an on-chip RAM, the second processor has an on-chip RAM and does not have an on-chip ROM, and the on-chip ROM of the first processor stores a ROM boot program of the first processor; a non-volatile memory is set to store a first operating program of the first processor and a second operating program of the second processor; after the SOC is powered on, the first processor starts to run the ROM boot program; the ROM boot program obtains the first operating program of the first processor from the non-volatile memory, and loads it into the on-chip RAM of the first processor for execution; the first operating program obtains the second operating program of the second processor from the non-volatile memory, and loads it into the on-chip RAM of the second processor for execution.
[0008] Preferably, before the first operating program loads the second operating program into the on-chip RAM of the second processor for execution, the method further includes: verifying the second operating program, and after the verification passes, loading the second operating program into the on-chip RAM of the second processor for execution.
[0009] Preferably, loading the second operating program into the on-chip RAM of the second processor for execution specifically includes: the first operating program loads the second operating program into the on-chip RAM of the second processor, powers on and resets the second processing unit, and enables the on-chip RAM on the second processor to start running the second operating program.
[0010] Preferably, the initialization work includes initializing PLL, CLOCK, and CMN networks.
[0011] Preferably, the first processor is an SCP processor, and the second processor includes an MCP processor and an AP processor.
[0012] Preferably, the first operating program is BL2 operating firmware of the first processor, and the second operating program includes BL1 operating firmware, BL2 operating firmware, BL31 operating firmware, BL32 operating firmware and BL33 operating firmware of the second processor.
[0013] Preferably, the non-volatile memory is EEPROM or SPI FLASH (a flash storage device operated via a serial interface) or the like.
[0014] Preferably, the first operating program of the first processor and the second operating program of the second processor are packaged or burned into the non-volatile memory respectively.
[0015] The present invention also provides an arm server, comprising at least one SOC and a non-volatile memory, each of the SOCs having a plurality of processors, one of the processors being a first processor, and the remaining processors being second processors, the first processor having an on-chip ROM and an on-chip RAM, the second processor having an on-chip RAM but not an on-chip ROM, the on-chip ROM of the first processor storing a ROM boot program of the first processor; the non-volatile memory storing a first operating program of the first processor and a second operating program of the second processor; after the SOC is powered on, the first processor starts to run the ROM boot program, and the ROM boot program guides the first processor and the second processor to start according to the arm server startup method as described above.
[0016] Preferably, the arm server has multiple SOCs, each of which is located on a chip, one SOC is communicatively connected to the non-volatile memory, and the first processor of the SOC is communicatively connected to the first processors of other SOCs through a reserved I2C / I3C interface, so as to synchronously distribute the first running program and the second running program of the startup running to the first processors of other SOCs when starting the running.
[0017] Preferably, the arm server has a plurality of SOCs, each of which is located on a core; each of the SOCs is respectively connected to the non-volatile memory for communicating with the non-volatile memory so as to obtain the first running program and the second running program of the non-volatile memory respectively at startup.
[0018] Compared with the prior art, on the one hand, the present invention only retains one on-chip ROM in the arm server SOC, achieving the most streamlined ROM. On the other hand, the on-chip ROM program of the present invention is only responsible for loading the runtime firmware (first running program) of the first processor where it is located, and the first running program continues to load the running firmware program (second running program) used by the second processor, so that the ROM boot program can be simplified, the probability of ROM boot program errors can be reduced, and the safety and reliability of arm server startup can be effectively increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a structural diagram of the arm server in Example 1 of the present invention.
[0020] Figure 2 This is a structural diagram of an arm server in a preferred embodiment based on Example 1.
[0021] Figure 3 It is a structural diagram of the arm server in Example 2 of the present invention.
[0022] Figure 4 It is a flow chart of the arm server startup method of the present invention.
[0023] Figure 5 It is a flow chart of an arm server startup method in a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0024] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.
[0025] Example 1, reference Figure 1 The present invention discloses an arm server, which has at least one SOC and a non-volatile memory, each of which has multiple processors, one of which is a first processor, and the remaining processors are second processors, the first processor has an on-chip ROM and an on-chip RAM, the second processor has an on-chip RAM and no on-chip ROM, and the on-chip ROM of the first processor stores a ROM boot program of the first processor. The non-volatile memory stores a first operating program of the first processor and a second operating program of the second processor.
[0026] After the SOC of the arm server is powered on, the on-chip ROM of the first processor runs the ROM boot program, then obtains the first running program from the non-volatile memory and loads it into the on-chip RAM of the first processor for execution. Then the first running program obtains the second running program from the non-volatile memory and loads it into the on-chip RAM of the second processor for execution.
[0027] refer to Figure 2 In this embodiment, the first processor is an SCP processor, and the second processor includes an MCP processor and an AP processor. Of course, it is not limited thereto, and any processor in the SOC can be used as the first processor, and the other processors are the second processors.
[0028] In one embodiment, the first operating program is BL2 operating firmware of the first processor, and the second operating program includes BL1 operating firmware, BL2 operating firmware, BL31 operating firmware, BL32 operating firmware and BL33 operating firmware of the second processor.
[0029] The non-volatile memory is EEPROM or SPI FLASH (a flash storage device operated via a serial interface), etc. The first operating program of the first processor and the second operating program of the second processor are packaged or burned into the non-volatile memory respectively.
[0030] refer to Figure 3 In Example 2, the arm server has multiple SOCs, each of which is located on a core particle, and the multiple core particles are connected through a reserved I2C / I3C interface. Each core particle reserves an I2C / I3C interface for the first processor, which is used as a distribution channel for starting the runtime firmware.
[0031] In this embodiment, one of the SOCs is communicatively connected to the non-volatile memory, and the first processor of the SOC is communicatively connected to the first processors of other SOCs through a reserved I2C / I3C interface, so as to synchronously distribute the first and second running programs during startup to the first processors of other SOCs during startup.
[0032] Of course, not limited to this, in another embodiment, each of the SOCs is respectively connected to the non-volatile memory for communication, so as to respectively obtain the first operating program and the second operating program in the non-volatile memory when the SOC is started.
[0033] refer to Figure 4 Based on Example 1 and Example 2, the startup steps of the arm server include steps S1 to S3.
[0034] S1, after the SOC is powered on, the first processor starts to run the ROM boot program.
[0035] S2, the ROM boot program obtains the first operating program of the first processor from the non-volatile memory, and loads it into the on-chip RAM of the first processor for execution, so as to complete the system initialization work, wherein the initialization work includes initializing PLL, CLOCK, CMN network, etc.
[0036] S3, the first operating program obtains the second operating program of the second processor from the non-volatile memory, and loads the second operating program into the on-chip RAM of the second processor for execution.
[0037] Specifically, the first operating program loads the second operating program into the on-chip RAM of the second processor, powers on and resets the second processing unit, and enables the on-chip RAM on the second processor to start running the second operating program.
[0038] Preferably, before step S3, the method further includes: verifying the second operating program, and after the verification is qualified, loading the second operating program into the on-chip RAM of the second processor for execution.
[0039] refer to Figure 2 and Figure 5 , taking the SCP processor as the first processor, the AP processor and the MCP processor as the second processor, the entire arm server startup process is illustrated as follows:
[0040] 1. After the SOC is powered on, it starts running from the SCP processor with the ROM program.
[0041] 2. The ROM boot program of the SCP processor first loads the BL2 runtime program (first runtime program) of the SCP processor from the off-chip non-volatile memory to the on-chip RAM of the SCP processor for execution;
[0042] 3. The SCP BL2 program (short for the BL2 runtime program of the SCP processor) continues to run on the SCP RAM (short for the on-chip RAM of the SCP processor) to complete the necessary system initialization work (such as initializing the system PLL, CLOCK, CMN network, etc.).
[0043] 4. The SCP BL2 program obtains the runtime firmware (second running program) of the processors such as the MCP and AP (second processor) from the non-volatile memory, and performs a security check on the signature of the firmware (verifies the validity of the signature).
[0044] 5. After the runtime firmware of the MCP, AP and other processors are verified by SCP BL2, the verified firmware is loaded into the on-chip RAM of the MCP processor through an internal reserved bus (such as APB), and the BL2 runtime firmware (second runtime firmware) of the AP processor is loaded into the on-chip RAM of the AP processor;
[0045] 6. SCP BL2 powers on and resets the MCP, AP and other processors, allowing the MCP and AP processors to start running from their respective on-chip RAMs.
[0046] After the BL1 running firmware of the subsequent AP processor is run, the subsequent BL2 running firmware, BL31 running firmware, BL32 running firmware and BL33 running firmware are run according to the preset startup process. The startup process after the AP processor BL1 runs the firmware is well known to those skilled in the art and will not be described in detail here.
[0047] MCP: Management Control Processor. SCP: System Control Processor. AP: Application Processor. ATF: arm-trusted-firmware. UEFI: Unified Extensible Firmware Interface. SOC, system-on-chip or system-on-chip.
[0048] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.
Claims
1. An arm server startup method, characterized in that: The SOC has a plurality of processors, one of which is a first processor, and the remaining processors are second processors, the first processor has an on-chip ROM and an on-chip RAM, the second processor has an on-chip RAM but no on-chip ROM, and the on-chip ROM of the first processor stores a ROM boot program of the first processor; Setting a non-volatile memory to store a first operating program of the first processor and a second operating program of the second processor; After the SOC is powered on, the first processor starts to run the ROM boot program; The ROM boot program obtains the first running program of the first processor from the non-volatile memory, and loads the first running program into the on-chip RAM of the first processor for execution; The first operating program obtains the second operating program of the second processor from the non-volatile memory, and loads the second operating program into the on-chip RAM of the second processor for execution.
2. The arm server startup method as claimed in claim 1, characterized in that: Before the first operating program loads the second operating program into the on-chip RAM of the second processor for execution, the method further includes: verifying the second operating program, and after the verification passes, loading the second operating program into the on-chip RAM of the second processor for execution.
3. The arm server startup method as claimed in claim 1, characterized in that: Loading the second operating program into the on-chip RAM of the second processor for execution specifically includes: the first operating program loads the second operating program into the on-chip RAM of the second processor, powers on and resets the second processing unit, and enables the on-chip RAM on the second processor to start running the second operating program.
4. The arm server startup method as claimed in claim 1, characterized in that: The initialization work includes initializing PLL, CLOCK, and CMN networks.
5. The arm server startup method as claimed in claim 1, characterized in that: The first processor is an SCP processor, and the second processor includes an MCP processor and an AP processor.
6. The arm server startup method as claimed in claim 1, characterized in that: The first operating program is BL2 operating firmware of the first processor, and the second operating program includes BL1 operating firmware, BL2 operating firmware, BL31 operating firmware, BL32 operating firmware and BL33 operating firmware of the second processor.
7. The arm server startup method as claimed in claim 1, characterized in that: The non-volatile memory is EEPROM or SPI FLASH.
8. The arm server startup method as claimed in claim 1, characterized in that: The first operating program of the first processor and the second operating program of the second processor are packaged or burned into the non-volatile memory respectively.
9. An arm server, characterized in that: The invention comprises at least one SOC and a non-volatile memory, wherein each of the SOCs has a plurality of processors, wherein one of the processors is a first processor, wherein the remaining processors are second processors, wherein the first processor has an on-chip ROM and an on-chip RAM, wherein the second processor has an on-chip RAM but no on-chip ROM, and the on-chip ROM of the first processor stores a ROM boot program of the first processor; and the non-volatile memory stores a first operating program of the first processor and a second operating program of the second processor; After the SOC is powered on, the first processor starts to run the ROM boot program, and the ROM boot program guides the first processor and the second processor to start according to the arm server startup method according to any one of claims 1 to 8.
10. The arm server according to claim 9, characterized in that: The arm server has multiple SOCs, each of which is located on a chip; The SOC is communicatively connected to the non-volatile memory, and the first processor of the SOC is communicatively connected to the first processors of other SOCs through a reserved I2C / I3C interface, so as to synchronously distribute the first and second running programs of startup operation to the first processors of other SOCs when startup operation is performed; Alternatively, each of the SOCs is respectively connected to the non-volatile memory for communication, so as to obtain the first operating program and the second operating program from the non-volatile memory respectively when starting.