Memory, data operation method thereof and electronic equipment

Abstract

The invention provides a memory, a data operation method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for solving the technical problem that a memory is complex in structure. The memory comprises a plurality of memory units arranged in an array, a plurality of first bit lines, a plurality of second bit lines and a plurality of word lines, each memory unit comprises a write transistor and a read transistor, a first source drain electrode of the write transistor is connected with a grid electrode of the read transistor, each first bit line is correspondingly connected with a second source drain electrode of the write transistor of one row of memory units, and each second bit line is correspondingly connected with a grid electrode of the read transistor. Each second bit line is correspondingly connected with the first source and drain electrodes of the read transistors of one row of storage units, each word line is correspondingly and electrically coupled with the multiple storage units arranged in the columns, in every two adjacent columns of storage units, the grid electrodes of the write transistors in the front column and the second source and drain electrodes of the read transistors in the rear column are coupled with the same word line, and the word lines are electrically coupled with the word lines. The two adjacent columns of storage units share one word line, so that the number of the word lines is reduced, the framework of the memory is simplified, and the complexity of the manufacturing process of the storage unit array is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory and a data operation method thereof, and an electronic device. Background Art

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read and write speed. Dynamic random access memory includes multiple storage cells, each of which usually includes a transistor and a capacitor, forming a 1T1C (1Transistors 1Capacitor) structure.

[0003] In the above-mentioned memory cell with 1T1C structure, the manufacturing process of the capacitor occupies a large area, which is not conducive to the miniaturization of the size. For this reason, the memory cell can also adopt a 2T0C (2Transistor 0Capacitor) structure, that is, the memory cell includes two transistors, wherein the first source and drain of one transistor are connected to the gate of the other transistor to remove the capacitor. However, the other poles of the two transistors in the memory cell of the 2T0C structure need to be connected by leads (word lines or bit lines), which makes the dynamic random access memory structure complicated and inconvenient for the arrangement (array) of the memory cell. Summary of the invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a memory and a data operation method thereof, and an electronic device to simplify the structure of the memory.

[0005] According to some embodiments, the present disclosure provides a memory according to a first aspect, comprising:

[0006] A plurality of memory cells arranged in an array, each of the memory cells comprising a write transistor and a read transistor, wherein a first source and a drain of the write transistor are connected to a gate of the read transistor;

[0007] A plurality of first bit lines, each of the first bit lines correspondingly connected to the second source and drain of the write transistor of a row of the memory cells;

[0008] A plurality of second bit lines, each of the second bit lines correspondingly connected to the first source and drain of the read transistor of a row of the memory cells;

[0009] A plurality of word lines, each of which is electrically coupled to a plurality of the memory cells arranged in columns, wherein in two adjacent columns of the memory cells, the gate of the write transistor in the previous column and the second source and drain of the read transistor in the next column are coupled to the same word line.

[0010] In some possible examples, the plurality of word lines include a plurality of first word lines and two second word lines, and each of the first word lines is correspondingly connected to the gate of the write transistor of the memory cell in the first column and the second source and drain of the read transistor of the memory cell in the second column in two adjacent columns of the memory cells;

[0011] The two second word lines are respectively connected to the second source and drain of the read transistor of the front memory cell in the two outermost columns of the memory cells and the gate of the write transistor of the rear memory cell.

[0012] In some possible examples, the memory further includes a plurality of sense amplifiers, each of the sense amplifiers being connected between the first bit line and the second bit line corresponding to a row of the storage cells;

[0013] The sense amplifier is configured to sense and amplify a voltage difference between the corresponding first bit line and the second bit line during a data reading operation, so as to read out data stored in the memory cell from the second bit line.

[0014] In some possible examples, the gate of the read transistor is a storage node, the read transistor and the write transistor are both N-type transistors, or the read transistor and the write transistor are both P-type transistors.

[0015] The memory in the disclosed embodiment includes a plurality of memory cells arranged in an array, a plurality of first bit lines, a plurality of second bit lines, and a plurality of word lines, each word line being electrically coupled to a plurality of memory cells arranged in a column. Among them, in two adjacent columns of memory cells, the gate of the write transistor in the previous column and the second source and drain of the read transistor in the next column are coupled to the same word line, so that the word line is used as both a write word line of the connected write transistor and a read word line of the connected read transistor. By sharing a word line between two adjacent columns of memory cells, the number of word lines is reduced, the architecture of the memory is simplified, and the complexity of the memory cell array manufacturing process is reduced.

[0016] According to some embodiments, the second aspect of the present disclosure provides an electronic device, including the memory as described above, which at least has the advantages of simplified memory architecture and simple manufacturing process. The specific effects are referred to above and will not be repeated here.

[0017] According to some embodiments, a third aspect of the present disclosure provides a data operation method of a memory, which is applied to the memory as described above, and the data operation method includes:

[0018] A data writing operation or a data reading operation is performed on a column of the storage cells.

[0019] In some possible examples, performing the data writing operation on a column of the storage cells includes:

[0020] Applying a first voltage to a word line coupled to the gate of a write transistor in the memory cell in the column, and applying a data signal to each of a plurality of first bit lines to turn on the write transistor in the memory cell in the column and write the data signal into the gate of a read transistor in the memory cell in the column; and,

[0021] A first reference voltage is applied to the word lines other than the word lines to which the gates of the write transistors in the memory cells in the column are coupled, and complementary signals of the data signals are respectively applied to a plurality of second bit lines to cut off the write transistors in the memory cells in the columns other than the memory cells in the column and to cut off the read transistors in the memory cells in each column.

[0022] In some possible examples, the read transistor and the write transistor are both N-type transistors, and the difference between the first voltage and the voltage of the data signal is greater than a threshold voltage of the write transistor to turn on the write transistor coupled to the word line to which the first voltage is applied;

[0023] The difference between the first reference voltage and the voltage of the data signal is smaller than the threshold voltage of the write transistor to turn off the write transistor coupled to the word line to which the first reference voltage is applied;

[0024] The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first low-level signal and the first high-level signal is less than the threshold voltage of the read transistor, and the difference between the voltage of the first low-level signal and the first reference voltage is less than the threshold voltage of the read transistor, so as to cut off each of the read transistors.

[0025] In some possible examples, the read transistor and the write transistor are both P-type transistors, and the difference between the first voltage and the voltage of the data signal is less than a threshold voltage of the write transistor, so as to turn on the write transistor coupled to the word line to which the first voltage is applied;

[0026] The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor to turn off the write transistor coupled to the word line to which the first reference voltage is applied;

[0027] The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first high-level signal and the first low-level signal is greater than the threshold voltage of the read transistor, and the difference between the voltage of the first high-level signal and the first reference voltage is greater than the threshold voltage of the read transistor to cut off each of the read transistors.

[0028] In some possible examples, performing the data reading operation on a column of the storage cells includes:

[0029] precharging the plurality of second bit lines to a second reference voltage;

[0030] A second voltage is applied to the word line coupled to the first source and drain of the read transistor in the memory cell in the column, and the read transistor in the memory cell in the column is turned on or off according to the storage signal of the gate of the read transistor in the memory cell in the column, so as to read out the storage signal of the read transistor in the memory cell in the column to the second connected bit line; and a third reference voltage is applied to the word lines other than the word line coupled to the gate of the read transistor in the memory cell in the column, and a fourth reference voltage is applied to each of the plurality of first bit lines, so as to turn off the read transistors in the memory cells in the other columns except the memory cell in the column and turn off the write transistors in the memory cells in each column.

[0031] In some possible examples, the read transistor and the write transistor are both N-type transistors;

[0032] The storage signal includes a second high level signal and a second low level signal, the difference between the voltage of the second high level signal and the second reference voltage is smaller than the threshold voltage of each of the read transistors, so as to turn off each of the read transistors after precharging;

[0033] When the storage signal of the gate of the read transistor in the storage unit of the column is a second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the read transistor, so as to turn on the read transistor whose storage signal is the second high level signal, and the voltage of the second bit line connected to the turned-on read transistor changes from the second reference voltage to the second voltage;

[0034] When the storage signal of the gate of the read transistor in the storage unit of the column is a second low level signal, the difference between the voltage of the second low level signal and the second voltage is smaller than the threshold voltage of the transistor being read, so as to cut off the read transistor whose storage signal is the second low level signal, and the voltage of the second bit line connected to the cut-off read transistor maintains the second reference voltage.

[0035] In some possible examples, the difference between the voltage of the second high level signal and the third reference voltage is smaller than the threshold voltage of the read transistor, so as to turn off the read transistors in other columns;

[0036] The difference between the third reference voltage and the voltage of the second low level signal is smaller than the threshold voltage of the write transistor, and the difference between the third reference voltage and the fourth reference voltage is smaller than the threshold voltage of the write transistor, so that each of the write transistors is turned off.

[0037] In some possible examples, the read transistor and the write transistor are both P-type transistors;

[0038] The storage signal includes a second high level signal and a second low level signal, the difference between the voltage of the second low level signal and the second reference voltage is greater than the threshold voltage of each of the read transistors, so as to turn off each of the read transistors after precharging;

[0039] When the storage signal of the gate of the read transistor in the storage unit of the column is a second low level signal, the difference between the voltage of the second low level signal and the second voltage is less than the threshold voltage of the read transistor, so as to turn on the read transistor whose storage signal is the second low level signal, and the voltage of the second bit line connected to the turned-on read transistor changes from the second reference voltage to the second voltage;

[0040] When the storage signal of the gate of the read transistor in the storage unit in the column is a second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the transistor being read, so as to cut off the read transistor whose storage signal is the second high level signal, and the voltage of the second bit line connected to the cut-off read transistor maintains the second reference voltage.

[0041] In some possible examples, the difference between the voltage of the second low level signal and the third reference voltage is greater than the threshold voltage of the read transistor, so as to turn off the read transistors in other columns;

[0042] The difference between the third reference voltage and the voltage of the second high level signal is greater than the threshold voltage of the write transistor, and the difference between the third reference voltage and the fourth reference voltage is greater than the threshold voltage of the write transistor, so that each of the write transistors is turned off.

[0043] In some possible examples, the third reference voltage and the fourth reference voltage are half of a difference between a voltage of the second high level signal and a voltage of the second low level signal.

[0044] In summary, the data operation method in the embodiment of the present disclosure is applied to the above-mentioned memory to implement data writing operation or data reading operation on a column of storage cells in the above-mentioned storage, thereby simplifying the memory architecture and reducing complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram of a storage unit in the related art;

[0046] Figure 2 is a schematic diagram of a memory in an embodiment of the present disclosure;

[0047] Figure 3 A schematic diagram of a data writing operation of a memory in an embodiment of the present disclosure;

[0048] Figure 4 A specific process diagram of a data writing operation of a memory in an embodiment of the present disclosure;

[0049] Figure 5 A schematic diagram of a data reading operation of a memory in an embodiment of the present disclosure;

[0050] Figure 6 The figure is a specific process diagram of a data reading operation of a memory in one embodiment of the present disclosure.

[0051] Description of reference numerals:

[0052] 10- memory; 11- storage unit;

[0053] 12- write transistor; 13- read transistor;

[0054] 14-word line; 15-first bit line;

[0055] 16 - second bit line; 17 - sense amplifier. DETAILED DESCRIPTION

[0056] The related art has the problem of complex memory structure. The inventor has found that the reason is: Figure 1The memory cell 11 includes a read transistor 13 and a write transistor 12. The first source and drain of the write transistor 12 are connected to the gate of the read transistor 13, the first source and drain of the write transistor 12 are connected to the write bit line (WBL), and the gate of the write transistor 12 is connected to the write word line (WWL). The first source and drain of the read transistor 13 are connected to the read bit line (RBL), and the second source and drain of the read transistor 13 are connected to the read word line (RWL). Each memory cell 11 requires four leads (write bit line, write word line, read bit line and read word line), and the structure of the memory is complex.

[0057] An embodiment of the present disclosure provides a memory in which two adjacent columns of memory cells share a word line, wherein the gate of a write transistor in a previous column and the second source and drain of a read transistor in a subsequent column are coupled to the same word line, so that the word line is used as both a write word line of the connected write transistors and a read word line of the connected read transistors, thereby reducing the number of word lines, simplifying the architecture of the memory, and reducing the complexity of the memory cell array manufacturing process.

[0058] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0059] See also Figure 2 The present disclosure provides a memory 10, which includes a plurality of memory cells 11 arranged in an array. Exemplarily, the plurality of memory cells 11 are arranged in a plurality of rows and columns at intervals, and the row direction is Figure 2 The horizontal direction is shown, and the column direction is as Figure 1 Vertical direction shown.

[0060] like Figure 2 As shown, each memory cell 11 includes a write transistor 12 and a read transistor 13, and the first source and drain of the write transistor 12 are connected to the gate of the read transistor 13. The gate of the read transistor 13 is used as a storage node to store data, such as data "1" or data "0". The memory cell 11 is a 2T0C memory cell 11, which reduces the volume of the memory cell 11 and improves the storage density.

[0061] The memory 10 further includes a plurality of first bit lines 15 and a plurality of second bit lines 16. The plurality of first bit lines 15 are arranged at intervals, and each first bit line 15 corresponds to a second source and drain of a write transistor 12 connected to a row of memory cells 11. The plurality of second bit lines 16 are arranged at intervals, and each second bit line 16 corresponds to a first source and drain of a read transistor 13 connected to a row of memory cells 11. Data is written to the storage node through the write transistor 12, or data is read from the storage node through the read transistor 13.

[0062] The first bit lines 15 and the second bit lines 16 are arranged along the row direction of the array formed by the memory cells 11 ( Figure 2 The first bit line 15 and the second bit line 16 are respectively located on both sides of a row of memory cells 11 and are correspondingly connected to a row of memory cells 11. The first bit line 15 is used as a write bit line of the connected write transistor 12, and the second bit line 16 is used as a read bit line of the connected read transistor 13.

[0063] The memory 10 further includes a plurality of word lines 14, each word line 14 being electrically coupled to a plurality of memory cells 11 arranged in a column. In two adjacent columns of memory cells 11, the gate of the previous column write transistor 12 and the second source and drain of the next column read transistor 13 are coupled to the same word line 14. Figure 2 In the left-right direction shown, the previous column is the left column, and the next column is the right column.

[0064] The conduction or cutoff of the write transistor 12 and the read transistor 13 is controlled by the word line 14, and two adjacent storage cells 11 share one word line 14, that is, one word line 14 is used as both a write word line of the connected write transistor 12 and a read word line of the connected read transistor 13, thereby reducing the number of word lines 14, simplifying the architecture of the memory 10, and reducing the complexity of the storage cell 11 array manufacturing process.

[0065] By controlling the voltage of each word line 14, each first bit line 15, and the second bit line 16, the conduction or cut-off of each write transistor 12 and the conduction or cut-off of each read transistor 13 can be controlled to write data into the storage node or read data from the storage node. Among them, through each word line 14, a data write operation or a data read operation can be performed on a column of data cells, and the data of each first bit line 15 can be written into the corresponding storage node, or the data of the storage node can be read out to the corresponding second bit line 16.

[0066] The gate of each read transistor 13 in the memory cell 11 is a storage node, and the read transistor 13 and the write transistor 12 are of the same type, for example, the read transistor 13 and the write transistor 12 are both N-type transistors, or the read transistor 13 and the write transistor 12 are both P-type transistors. When the read transistor 13 and the write transistor 12 are both N-type transistors, the voltage on each word line 14, each first bit line 15, and each second bit line 16 is adapted to the N-type transistor to turn on or off each read transistor 13 and the write transistor 12. When the read transistor 13 and the write transistor 12 are both P-type transistors, the voltage on each word line 14, each first bit line 15, and each second bit line 16 is adapted to the P-type transistor to turn on or off each read transistor 13 and the write transistor 12.

[0067] In some examples, the plurality of word lines 14 include a plurality of first word lines and two second word lines, each first word line correspondingly connecting the gate of the write transistor 12 of the first column of memory cells 11 and the second source and drain of the read transistor 13 of the second column of memory cells 11 in two adjacent columns. The two second word lines are respectively connected to the second source and drain of the read transistor 13 of the first column of memory cells 11 and the gate of the write transistor 12 of the second column of memory cells 11 in the two outermost columns of memory cells 11.

[0068] The word line 14 between two adjacent columns of memory cells 11 is the first word line, that is, the two adjacent columns of memory cells 11 can share one word line 14. The read transistors 13 or write transistors 12 in the two outermost columns of memory cells 11 need to be connected to a separate word line 14, which is the second word line. Figure 2 As shown, the read transistors 13 in the leftmost column of memory cells 11 and the write transistors 12 in the rightmost column of memory cells 11 are each connected to a second word line.

[0069] The second word line connected to the read transistor 13 of the front memory cell 11 is used as the read word line of the connected read transistor 13 , and the second word line connected to the write transistor 12 of the rear memory cell 11 is used as the write word line of the connected write transistor 12 .

[0070] In some examples, the memory 10 further includes a plurality of sense amplifiers 17 (sense amplifiers, SA for short), each sense amplifier 17 being connected between a first bit line 15 and a second bit line 16 corresponding to a row of memory cells 11. The sense amplifier 17 is configured to sense and amplify a voltage difference between the corresponding first bit line 15 and the second bit line 16 during a data read operation, so as to facilitate reading data stored in the memory cell 11 from the second bit line 16.

[0071] A sense amplifier 17 is connected between the corresponding first bit line 15 and the second bit line 16, and is used to sense and amplify the voltage difference between the first bit line 15 and the second bit line 16 connected thereto. When performing a data read operation, the voltages on the corresponding first bit line 15 and the second bit line 16 are different and have a difference, and the sense amplifier 17 senses the voltage difference and amplifies the voltage difference. For example, when the voltage on the second bit line 16 is lower than the voltage on the first bit line 15, the voltage on the second bit line 16 is made lower than the voltage on the first bit line 15 by pulling down the voltage on the second bit line 16 and / or pulling up the voltage on the first bit line 15; when the voltage on the second bit line 16 is higher than the voltage on the first bit line 15, the voltage on the second bit line 16 is made higher than the voltage on the first bit line 15 by pulling up the voltage on the second bit line 16 and / or pulling down the voltage on the first bit line 15. Thus, it is convenient to read the data stored in the storage unit 11 from the second bit line 16.

[0072] In summary, the memory 10 in the embodiment of the present disclosure includes a plurality of memory cells 11 arranged in an array, a plurality of first bit lines 15, a plurality of second bit lines 16, and a plurality of word lines 14, each word line 14 being electrically coupled to a plurality of memory cells 11 arranged in a column, wherein in two adjacent columns of memory cells 11, the gate of the previous column of write transistors 12 and the second source and drain of the next column of read transistors 13 are coupled to the same word line 14, so that the word line 14 is used as both a write word line of the connected write transistors 12 and a read word line of the connected read transistors 13. By sharing a word line 14 between two adjacent columns of memory cells 11, the number of word lines 14 is reduced, the architecture of the memory 10 is simplified, and the complexity of the memory cell 11 array manufacturing process is reduced.

[0073] It should be noted that in the present disclosure, the concepts of "row" and "column" are relative, that is, "row" and "column" are interchangeable. In addition, in the present disclosure, the positive and negative signs are considered when comparing the magnitudes of voltages.

[0074] The present disclosure also provides an electronic device, which may be a computer or a server, etc., and includes the above-mentioned memory 10 (see Figure 2 ), thus at least having the advantages of simplified memory 10 architecture and simple manufacturing process, the specific effects are referred to above and will not be repeated here.

[0075] The electronic device may further include at least one processor to execute the computer-executable instructions stored in the memory 10. The processor may be a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or other programmable logic devices.

[0076] For example, the electronic device includes but is not limited to a server, a printer, a scanner, a tablet computer, a smart phone, a driving recorder, a navigator, a wearable device, etc.

[0077] The present disclosure also provides a method for operating data in a memory. Figures 3 to 6 , applied to the above-mentioned memory 10, the data operation method includes: performing a data write operation or a data read operation on a column of storage cells 11 to store data in the gate of the read transistor 13 of the column of storage cells 11, or reading out the data stored in the gate of the read transistor 13 of the column of storage cells 11.

[0078] For some examples, see Figure 3 , performing a data writing operation on a column of storage cells 11, including: applying a first voltage to a word line 14 coupled to the gate of a write transistor 12 in the column of storage cells 11, and applying data signals to a plurality of first bit lines 15 respectively to turn on the write transistor 12 in the column of storage cells 11, and writing the data signal into the gate of a read transistor 13 in the column of storage cells 11.

[0079] Among them, the first voltage can be recorded as V wlw , the first voltage can turn on all the write transistors 12 in the column of storage cells 11. The data signal can be a first high level signal or a first low level signal, that is, it can be one of the first high level signal and the first low level signal. The voltages of the first high level signal and the first low level signal are respectively denoted as V H1 and V L1 . For example, when the data signal is a first high-level signal, data "1" is stored in the storage node through the turned-on write transistor 12, and when the data signal is a first low-level signal, data "0" is stored in the storage node through the turned-on write transistor 12; or, when the data signal is a first high-level signal, data "0" is stored in the storage node through the turned-on write transistor 12, and when the data signal is a first low-level signal, data "1" is stored in the storage node through the turned-on write transistor 12.

[0080] The data writing operation for a column of memory cells 11 also includes: applying a first reference voltage to other word lines 14 except the word line 14 coupled to the gate of the write transistor 12 in the column of memory cells 11, and applying complementary signals of the data signal to multiple second bit lines 16 respectively to cut off the write transistors 12 in other columns of memory cells 11 except the column of memory cells 11 and cut off the read transistors 13 in each column of memory cells 11.

[0081] Among them, the first reference voltage can be recorded as V ref1 , the first reference voltage turns off the write transistors 12 in the other column storage cells 11. The complementary signal is complementary to the data signal, and the complementary signal and the data signal are respectively a first high level signal and a first low level signal, that is, the data signal is one of the first high level signal and the first low level signal, and the complementary signal is the other of the first high level signal and the first low level signal.

[0082] In some possible implementations, the read transistor 13 and the write transistor 12 are both N-type transistors, and the difference between the first voltage and the voltage of the data signal (including the first high-level signal and the first low-level signal) is greater than the threshold voltage of the write transistor 12, so as to turn on the write transistor 12 coupled to the word line 14 to which the first voltage is applied. The difference between the first reference voltage and the voltage of the data signal (including the first high-level signal and the first low-level signal) is less than the threshold voltage of the write transistor 12, so as to turn off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied.

[0083] Wherein, the threshold voltage of the write transistor 12 is denoted as V tw , the threshold voltage of the read transistor 13 is denoted as V tr The difference refers to the value of the former minus the latter. The difference between the first voltage and the voltage of the data signal is equal to the first voltage minus the voltage of the data signal. The difference in the following text refers to the meaning here.

[0084] When both the read transistor 13 and the write transistor 12 are N-type transistors, the threshold voltage of the write transistor 12 and the threshold voltage of the read transistor 13 are both greater than zero. The difference between the first voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, so as to turn on the write transistor 12 coupled to the word line 14 to which the first voltage is applied, thereby writing the data on the first bit line 15 into the storage node. The difference between the first reference voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, so as to turn off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied, that is, the other column storage cells 11 do not perform data writing operations.

[0085] The data signal is one of a first high level signal or a first low level signal, and the voltage of the first high level signal is greater than the voltage of the first low level signal. When the difference between the first voltage and the voltage of the first high level signal is greater than the threshold voltage of the write transistor 12, that is, V wlw -V H1 >V tw When the difference between the first reference voltage and the voltage of the first low level signal is less than the threshold voltage of the write transistor 12, that is, V ref1 -V L1 <V tw When the first reference voltage is applied, the column write transistors 12 coupled to the word line 14 to which the first reference voltage is applied are all turned off.

[0086] When a data writing operation is performed on a column of memory cells 11, each read transistor 13 is turned off. That is, when the write transistor 12 coupled to the word line 14 to which the first voltage is applied is turned on and the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied is turned off, each read transistor 13 is turned off. For example, the difference between the voltage of the first high-level signal and the first low-level signal is less than the threshold voltage of the read transistor 13, and the difference between the voltage of the first high-level signal and the first reference voltage is less than the threshold voltage of the read transistor 13, so that each read transistor 13 is turned off. That is, V H1 -V L1 <V tr , V H1 -V ref1 <V tr , ensuring that each read transistor 13 is turned off. The first reference voltage may be between the voltage of the first high level signal and the voltage of the first low level signal, that is, the first reference voltage is less than the voltage of the first high level signal and greater than the voltage of the first low level signal.

[0087] For example, see Figure 4 , the threshold voltage of the write transistor 12 is X (X>0), the voltage of the read transistor 13 is 1.5X, the first voltage is 2.5X, the first reference voltage is 0.5X, the voltage of the first high-level signal is X, and the voltage of the first low-level signal is 0, that is, V tw =X,V tr =1.5X, V wlw =2.5X, V ref1 =0.5X, V H1 =X,V L1 = 0. At this time, the first high level signal or the first low level signal on the first bit line 15 is written into the corresponding memory cell 11 in a column of memory cells 11 coupled to the word line 14 to which the first voltage is applied. It should be noted that the embodiments of the present disclosure include but are not limited to this.

[0088] In some possible implementations, the read transistor 13 and the write transistor 12 are both P-type transistors, and the difference between the first voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, so as to turn on the write transistor 12 coupled to the word line 14 to which the first voltage is applied. The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, so as to turn off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied.

[0089] Furthermore, the data signal is one of the first high-level signal and the first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor 13, and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor 13, so as to cut off each read transistor 13.

[0090] When both the read transistor 13 and the write transistor 12 are P-type transistors, the threshold voltage of the write transistor 12 and the threshold voltage of the read transistor 13 are both less than zero. The difference between the first voltage and the voltage of the data signal is less than the threshold voltage of the write transistor 12, so as to turn on the write transistor 12 coupled to the word line 14 to which the first voltage is applied, thereby writing the data on the first bit line 15 to the storage node. The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor 12, so as to turn off the write transistor 12 coupled to the word line 14 to which the first reference voltage is applied, that is, the other column storage cells 11 do not perform data writing operations.

[0091] When the difference between the first voltage and the voltage of the first high level signal is less than the threshold voltage of the write transistor 12, that is, V wlw –V H1 <V tw , the column of write transistors 12 coupled to the word line 14 to which the first voltage is applied are all turned on. When the difference between the first reference voltage and the voltage of the first high level signal is greater than the threshold voltage of the write transistor 12, that is, V ref1 -V H1 >V tw , the column write transistors 12 coupled to the word line 14 to which the first reference voltage is applied are all turned off.

[0092] When a data writing operation is performed on a column of storage cells 11, each read transistor 13 is turned off. The difference between the voltage of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor 13, and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor 13, so as to turn off each read transistor 13. That is, V L1 -V H1 >V tr , V L1 -V ref1 >Vtr , ensuring that each read transistor 13 is turned off. The first reference voltage may be between the voltage of the first high level signal and the voltage of the first low level signal. Thus, when V L1 -V H1 <V tr When V L1 -V ref1 <V tr .

[0093] In some possible examples, see Figure 5 , performing a data reading operation on a column of memory cells 11, including: precharging multiple second bit lines 16 to a second reference voltage; applying a second voltage to a word line 14 coupled to a first source and drain of a read transistor 13 in the column of memory cells 11, and turning on or off the read transistor 13 in the column of memory cells 11 according to a storage signal of a gate of the read transistor 13 in the column of memory cells 11, so as to read out the storage signal of the read transistor 13 in the column of memory cells 11 to the connected second bit line 16.

[0094] The second reference voltage can be recorded as V ref2 , the second voltage can be recorded as V wlr The second voltage turns on all the read transistors 13 in the column of storage cells 11. The storage signal of the gate of the read transistor 13 includes a second high level signal and a second low level signal, and the second high level signal and the second low level signal are respectively denoted as V H2 and V L2 When the storage signal at the gate of the read transistor 13 is the second high level signal, the gate of the read transistor 13 stores data “1”, and when the storage signal at the gate of the read transistor 13 is the second low level signal, the gate of the read transistor 13 stores data “0”; or, when the storage signal at the gate of the read transistor 13 is the second high level signal, the gate of the read transistor 13 stores data “0”, and when the storage signal at the gate of the read transistor 13 is the second low level signal, the gate of the read transistor 13 stores data “1”.

[0095] The voltage of the storage signal at the gate of the read transistor 13 is compared with the second reference voltage, so that the read transistor 13 is turned on or off. For example, in the case where the read transistor 13 is an N-type transistor, when the storage signal at the gate of the read transistor 13 is a second high-level signal, the read transistor 13 is turned on to read out the second high-level signal. When the storage signal at the gate of the read transistor 13 is a second low-level signal, the read transistor 13 is turned off, and the voltage on the second bit line 16 remains unchanged to read out the second low-level signal.

[0096] The data reading operation for a column of memory cells 11 also includes: applying a third reference voltage to other word lines 14 except the word line 14 coupled to the gate of the read transistor 13 in the column of memory cells 11, and applying a fourth reference voltage to each of the plurality of first bit lines 15 to cut off the read transistors 13 in other columns of memory cells 11 except the column of memory cells 11 and to cut off the write transistors 12 in each column of memory cells 11.

[0097] The third reference voltage can be recorded as V ref3 , the fourth reference voltage can be recorded as V ref4 , the other column read transistors 13 are turned off, and all write transistors 12 are turned off. In some possible implementations, the read transistor 13 and the write transistor 12 are both N-type transistors. The storage signal includes a second high level signal and a second low level signal, and the difference between the voltage of the second high level signal and the second reference voltage is less than the threshold voltage of each read transistor 13, that is, V H2 -V ref2 <V tr , to turn off each read transistor 13 after pre-charging.

[0098] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the read transistor 13, that is, V H2 -V wlr >V tr , the read transistor 13 whose storage signal is the second high level signal is turned on. The voltage of the second bit line 16 connected to the turned-on read transistor 13 changes from the second reference voltage to the second voltage.

[0099] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second low level signal, the difference between the voltage of the second low level signal and the second voltage is less than the threshold voltage of the transistor being read, that is, V L2 -V wlr <V tr , by turning off the read transistor 13 whose storage signal is the second low level signal, the voltage of the second bit line 16 connected to the turned-off read transistor 13 maintains the second reference voltage.

[0100] The difference between the voltage of the second high level signal and the third reference voltage is less than the threshold voltage of the read transistor 13, that is, V H2 -V ref3 <V tr When V H2 -V ref3 <V tr When V L2 -V ref3 <V H2 -V ref3 <Vtr , no matter the storage signal of other column read transistors 13 is the second high level signal or the second low level signal, they remain cut off.

[0101] The difference between the third reference voltage and the voltage of the second low level signal is less than the threshold voltage of the write transistor 12, and the difference between the third reference voltage and the fourth reference voltage is less than the threshold voltage of the write transistor 12, that is, V ref3 -V L2 <V tw , and V ref3 -V ref4 <V tw , to turn off each write transistor 12.

[0102] For example, see Figure 6 , the threshold voltage of the write transistor 12 is X (X>0), the voltage of the read transistor 13 is 1.5X, the voltage of the first high level signal is X, the voltage of the first low level signal is 0, the second voltage can be -X, the second reference voltage can be X, the third reference voltage and the fourth reference voltage are both 0.5X, that is, V tw =X,V tr =1.5X, V wlr =-X, V ref2 =1X, V ref3 =V ref4 =0.5X, V H2 =X,V L2 =0. At this time, the storage signal in the storage unit 11 is read out to the connected second bit line 16. It should be noted that the embodiments of the present disclosure include but are not limited to this.

[0103] In some other possible implementations, the read transistor 13 and the write transistor 12 are both P-type transistors, the storage signal includes a second high-level signal and a second low-level signal, and the difference between the voltage of the second low-level signal and the second reference voltage is greater than the threshold voltage of each read transistor 13, that is, V L2 -V ref2 >V tr , to turn off each read transistor 13 after pre-charging.

[0104] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second low level signal and the second voltage is smaller than the threshold voltage of the read transistor 13, V L2 -V wlr <V tr , to turn on the read transistor 13 whose storage signal is the second low level signal, the voltage of the second bit line 16 connected to the turned-on read transistor 13 changes from the second reference voltage to the second voltage.

[0105] When the storage signal of the gate of the read transistor 13 in the column of storage cells 11 is the second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the transistor being read, that is, V H2 -V wlr <V tr , the read transistor 13 whose storage signal is the second high level signal is turned off, and the voltage of the second bit line 16 connected to the turned-off read transistor 13 maintains the second reference voltage.

[0106] The difference between the voltage of the second low level signal and the third reference voltage is greater than the threshold voltage of the read transistor 13, that is, V L2 -V ref3 >V tr Furthermore, due to V H2 -V ref3 >V L2 -V ref3 >V tr , no matter the storage signal of other column read transistors 13 is the second high level signal or the second low level signal, they remain cut off.

[0107] The difference between the third reference voltage and the voltage of the second high level signal is greater than the threshold voltage of the write transistor 12, and the difference between the third reference voltage and the fourth reference voltage is greater than the threshold voltage of the write transistor 12, that is, V ref3 -V H2 >V tw , and V ref3 -V ref4 >V tw , to turn off each write transistor 12.

[0108] In some possible examples, the third reference voltage and the fourth reference voltage are half of the difference between the voltages of the second high level signal and the second low level signal. The voltage of the second high level signal may be the same as the voltage of the first high level signal, and the voltage of the second low level signal may be the same as the voltage of the first low level signal.

[0109] In summary, the data operation method in the embodiment of the present disclosure is applied to the above-mentioned memory 10 to implement data writing operation or data reading operation on a column of storage cells 11 in the above-mentioned storage, and the architecture of the memory 10 is simplified and the complexity is reduced.

[0110] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory, characterized in that: include: A plurality of memory cells arranged in an array, each of the memory cells comprising a write transistor and a read transistor, wherein a first source and a drain of the write transistor are connected to a gate of the read transistor; A plurality of first bit lines, each of the first bit lines correspondingly connected to the second source and drain of the write transistor of a row of the memory cells; A plurality of second bit lines, each of the second bit lines correspondingly connected to the first source and drain of the read transistor of a row of the memory cells; A plurality of word lines, each of which is electrically coupled to a plurality of the memory cells arranged in columns, wherein in two adjacent columns of the memory cells, the gate of the write transistor in the previous column and the second source and drain of the read transistor in the next column are coupled to the same word line.

2. The memory according to claim 1, characterized in that: The plurality of word lines include a plurality of first word lines and two second word lines, each of the first word lines correspondingly connects the gate of the write transistor of the memory cell in the first column and the second source and drain of the read transistor of the memory cell in the second column in two adjacent columns of the memory cells; The two second word lines are respectively connected to the second source and drain of the read transistor of the front memory cell in the two outermost columns of the memory cells and the gate of the write transistor of the rear memory cell.

3. The memory according to claim 1 or 2, characterized in that: The memory further comprises a plurality of sense amplifiers, each of the sense amplifiers being connected between the first bit line and the second bit line corresponding to a row of the memory cells; The sense amplifier is configured to sense and amplify a voltage difference between the corresponding first bit line and the second bit line during a data reading operation, so as to read out data stored in the memory cell from the second bit line.

4. The memory according to claim 1 or 2, characterized in that: The gate of the read transistor is a storage node, and both the read transistor and the write transistor are N-type transistors, or both the read transistor and the write transistor are P-type transistors.

5. An electronic device, characterized in that: A memory comprising any one of claims 1 to 4.

6. A data operation method of a memory, characterized in that: Applied to the memory according to any one of claims 1 to 4, the data operation method comprises: A data writing operation or a data reading operation is performed on a column of the storage cells.

7. The data operation method according to claim 6, characterized in that: Performing the data writing operation on a column of the storage cells includes: Applying a first voltage to a word line coupled to the gate of a write transistor in the memory cell in the column, and applying a data signal to each of a plurality of first bit lines to turn on the write transistor in the memory cell in the column and write the data signal into the gate of a read transistor in the memory cell in the column; and, A first reference voltage is applied to the word lines other than the word lines to which the gates of the write transistors in the memory cells in the column are coupled, and complementary signals of the data signals are respectively applied to a plurality of second bit lines to cut off the write transistors in the memory cells in the columns other than the memory cells in the column and to cut off the read transistors in the memory cells in each column.

8. The data operation method according to claim 7, characterized in that: The read transistor and the write transistor are both N-type transistors, and the difference between the first voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor to turn on the write transistor coupled to the word line to which the first voltage is applied; The difference between the first reference voltage and the voltage of the data signal is smaller than the threshold voltage of the write transistor to turn off the write transistor coupled to the word line to which the first reference voltage is applied; The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first high-level signal and the first low-level signal is less than the threshold voltage of the read transistor, and the difference between the voltage of the first high-level signal and the first reference voltage is less than the threshold voltage of the read transistor, so as to cut off each of the read transistors.

9. The data operation method according to claim 7, characterized in that: The read transistor and the write transistor are both P-type transistors, and the difference between the first voltage and the voltage of the data signal is smaller than the threshold voltage of the write transistor, so as to turn on the write transistor coupled to the word line to which the first voltage is applied; The difference between the first reference voltage and the voltage of the data signal is greater than the threshold voltage of the write transistor to turn off the write transistor coupled to the word line to which the first reference voltage is applied; The data signal is one of a first high-level signal and a first low-level signal, the complementary signal is the other of the first high-level signal and the first low-level signal, and the difference between the voltages of the first low-level signal and the first high-level signal is greater than the threshold voltage of the read transistor, and the difference between the voltage of the first low-level signal and the first reference voltage is greater than the threshold voltage of the read transistor, so as to cut off each of the read transistors.

10. The data operation method according to claim 7, characterized in that: Performing the data reading operation on a column of the storage cells includes: precharging the plurality of second bit lines to a second reference voltage; Applying a second voltage to the word line coupled to the first source and drain of the read transistor in the memory cell in the column, and turning on or off the read transistor in the memory cell in the column according to the storage signal of the gate of the read transistor in the memory cell in the column, so as to read out the storage signal of the read transistor in the memory cell in the column to the connected second bit line; and A third reference voltage is applied to the word lines other than the word lines to which the gates of the read transistors in the memory cells in the column are coupled, and a fourth reference voltage is applied to each of the plurality of first bit lines to cut off the read transistors in the memory cells in the columns other than the memory cells in the column and to cut off the write transistors in the memory cells in each column.

11. The data operation method according to claim 10, characterized in that: The read transistor and the write transistor are both N-type transistors; The storage signal includes a second high level signal and a second low level signal, the difference between the voltage of the second high level signal and the second reference voltage is smaller than the threshold voltage of each of the read transistors, so as to turn off each of the read transistors after precharging; When the storage signal of the gate of the read transistor in the storage unit of the column is a second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the read transistor, so as to turn on the read transistor whose storage signal is the second high level signal, and the voltage of the second bit line connected to the turned-on read transistor changes from the second reference voltage to the second voltage; When the storage signal of the gate of the read transistor in the storage unit of the column is a second low level signal, the difference between the voltage of the second low level signal and the second voltage is smaller than the threshold voltage of the transistor being read, so as to cut off the read transistor whose storage signal is the second low level signal, and the voltage of the second bit line connected to the cut-off read transistor maintains the second reference voltage.

12. The data operation method according to claim 11, characterized in that: The difference between the voltage of the second high level signal and the third reference voltage is smaller than the threshold voltage of the read transistor, so as to turn off the read transistors of other columns; The difference between the third reference voltage and the voltage of the second low level signal is smaller than the threshold voltage of the write transistor, and the difference between the third reference voltage and the fourth reference voltage is smaller than the threshold voltage of the write transistor, so that each of the write transistors is turned off.

13. The data operation method according to claim 10, characterized in that: The read transistor and the write transistor are both P-type transistors; The storage signal includes a second high level signal and a second low level signal, the difference between the voltage of the second low level signal and the second reference voltage is greater than the threshold voltage of each of the read transistors, so as to turn off each of the read transistors after precharging; When the storage signal of the gate of the read transistor in the storage unit of the column is a second low level signal, the difference between the voltage of the second low level signal and the second voltage is less than the threshold voltage of the read transistor, so as to turn on the read transistor whose storage signal is the second low level signal, and the voltage of the second bit line connected to the turned-on read transistor changes from the second reference voltage to the second voltage; When the storage signal of the gate of the read transistor in the storage unit in the column is a second high level signal, the difference between the voltage of the second high level signal and the second voltage is greater than the threshold voltage of the transistor being read, so as to cut off the read transistor whose storage signal is the second high level signal, and the voltage of the second bit line connected to the cut-off read transistor maintains the second reference voltage.

14. The data operation method according to claim 13, characterized in that: The difference between the voltage of the second low level signal and the third reference voltage is greater than the threshold voltage of the read transistor, so as to turn off the read transistors in other columns; The difference between the third reference voltage and the voltage of the second high level signal is greater than the threshold voltage of the write transistor, and the difference between the third reference voltage and the fourth reference voltage is greater than the threshold voltage of the write transistor, so that each of the write transistors is turned off.

15. The data operation method according to any one of claims 11 to 14, characterized in that: The third reference voltage and the fourth reference voltage are half of a difference between a voltage of the second high level signal and a voltage of the second low level signal.

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