Configuration method of DUT interface and VIP interface

Abstract

The invention provides a configuration method for a DUT interface and a VIP interface. The configuration method comprises the steps that a table file pre-filled with bus basic information, an RTL file naming a bus in a unified mode and an SV file are obtained; capturing bus information of the DUT end in the RTL file and the table file, and extracting interface information of the DUT according to the bus information of the DUT end; capturing bus information of the VIP end in the SV file and the table file, and extracting interface information of the VIP according to the bus information of the VIP end; and comparing the interface information of the DUT with the interface information of the VIP, and if the interface information is consistent, performing interconnection. According to the invention, the function of connecting the interface of the DUT and the VIP is realized, the frequency of manual connection is reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a configuration method of a DUT interface and a VIP interface. Background Art

[0002] In recent years, as the scale of SOC (System On Chip) has gradually increased, the number and types of buses involved in DUT (Design Under Test) have also increased, and DUT may contain hundreds or thousands of interfaces. After the SOC design is completed, it needs to be verified. Before verification, the verification environment needs to be built. The key is to ensure that the interface of DUT is correctly connected to the interface of VIP in Testbench (test platform) before subsequent verification can be carried out.

[0003] Currently, there are many ways to automatically generate verification platforms, making subsequent verification simple and convenient. However, the way to connect DUT and VIP is still manual connection, that is, people manually input code instructions to control the connection between DUT and VIP.

[0004] The above-mentioned prior art realizes the connection between DUT and VIP by adopting manual connection. However, in large-scale SOC scenarios, the interface of DUT is frequently changed. After the interface of DUT is changed, DUT and VIP need to be reconnected. Many files need to be changed manually, which will consume a lot of manual effort and affect the subsequent verification efficiency. When it is necessary to verify the bus of the entire SOC, if only manual connection between DUT and VIP is relied on, it is not only difficult to maintain, but also very easy to make mistakes, which also seriously affects the verification efficiency. Therefore, it is necessary to automatically realize the interface connection between DUT and VIP to improve the verification efficiency. Therefore, the present invention provides a configuration method of DUT interface and VIP interface to solve the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a configuration method of a DUT interface and a VIP interface to realize the function of connecting the interface of the DUT and the VIP, thereby reducing the frequency of manual connection and improving the verification efficiency.

[0006] In order to achieve the purpose of the present invention, the technical solution adopted by the present invention is: A method for configuring a DUT interface and a VIP interface comprises the following steps: Obtain a table file pre-filled with basic bus information, an RTL file with unified bus naming, and an SV file; Capture the bus information of the DUT end in the RTL file and the table file, and extract the interface information of the DUT according to the bus information of the DUT end; Capture the bus information of the VIP end in the SV file and the table file, and extract the interface information of the VIP according to the bus information of the VIP end; The interface information of the DUT is compared with the interface information of the VIP, and interconnection is performed if the interface information is consistent.

[0007] Further, the bus information of the DUT end in the RTL file and the table file is captured, and the interface information of the DUT is extracted according to the bus information of the DUT end, specifically including: Capture the bus information of the DUT end in the RTL file and the table file; Filtering the bus information of the DUT end in the RTL file and the bus information of the DUT end in the table file; Valid DUT interface information is extracted based on the filtered bus information at the DUT end.

[0008] Further, screening the bus information of the DUT end in the RTL file and the bus information of the DUT end in the table file specifically includes: It is determined whether the bus information of the DUT end in the RTL file is consistent with the bus information of the DUT end in the table file. If they are consistent, they are retained for subsequent interface information extraction; if they are inconsistent, they are discarded.

[0009] Further, the bus information of the VIP end in the SV file and the table file is captured, and the interface information of the VIP is extracted according to the bus information of the VIP end, specifically including: Capture the bus information of the VIP end in the SV file and the table file; Filtering the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file; The effective VIP interface information is extracted based on the bus information of the filtered VIP end.

[0010] Further, screening the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file specifically includes: Determine whether the bus information of the VIP end in the SV file is consistent with the bus information of the VIP end in the table file. If they are consistent, keep them for subsequent interface information extraction. If they are inconsistent, discard them.

[0011] Further, the interface information of the DUT is compared with the interface information of the VIP, and if the interface information is consistent, interconnection is performed, specifically including: The DUT interface signal and interface direction are obtained according to the valid DUT interface information, the corresponding bus is selected according to the DUT interface signal, the DUT interface signal is connected to the signal in the selected corresponding bus, and the selected bus interface is connected to the VIP, thereby realizing the connection between the DUT interface and the VIP interface.

[0012] Further, the interface information of the DUT is compared with the interface information of the VIP, and if the interface information is consistent, interconnection is performed, specifically including: The read and write signals on the selected bus interface are captured, and the read and write signals are used to determine whether to generate a specific verification component.

[0013] Furthermore, the basic bus information includes a sending transaction type supported by the bus, and a corresponding transaction constraint can be generated according to the sending transaction type.

[0014] Furthermore, before comparing the interface information of the DUT with the interface information of the VIP, the method further includes: Fill the valid DUT interface information and the valid VIP interface information into a preset template file to generate an interface file, thereby realizing the templating of the interface information.

[0015] Furthermore, the interface file is re-read and the interface information is checked.

[0016] Beneficial effects of the present invention: 1. The present invention captures the bus information of the DUT end in the RTL file and the table file, extracts the interface information of the DUT according to the bus information of the DUT end, captures the bus information of the VIP end in the SV file and the table file, extracts the interface information of the VIP according to the bus information of the VIP end, and then compares the interface information of the DUT with the interface information of the VIP, interconnects the interfaces of the VIP and the DUT with consistent information to realize the configuration of the DUT interface and the VIP interface, eliminates the operation of manually inputting code instructions to control the connection between the DUT and the VIP, simplifies the verification process, and thus effectively improves the verification efficiency.

[0017] 2. The present invention uniformly names the bus when writing the RTL file in the SOC design stage, so that the bus information is standardized, so that the interface information can be obtained by capturing the bus information in the verification stage, and the DUT and VIP are effectively interconnected using the interface information. The interface information is formed based on the bus declaration information configured in the SOC design stage. When dealing with large-scale SOC designs, the DUT interface changes frequently, and the interface file generated during verification will also change accordingly, without the need for manual modification, thereby achieving rapid response to bus modifications and achieving the purpose of low latency.

[0018] 3. The present invention can extract bus information based on the RTL file written by the designer in the DUT design stage and the SV file in the VIP, and can connect the VIP and the DUT according to the interface information. When the interface of the DUT changes, the extracted interface information will also change accordingly, without the need to manually modify the file, saving a lot of manual effort and reducing the errors caused by manual operation, thereby improving the verification efficiency and verification quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is an overall flow chart of a configuration method of a DUT interface and a VIP interface of the present invention; Figure 2 A schematic diagram of the implementation flow of capturing the bus information of the DUT end in the RTL file and the table file, and extracting the interface information of the DUT according to the bus information of the DUT end, in a configuration method of the DUT interface and the VIP interface of the present invention; Figure 3 A schematic diagram of the implementation flow of a configuration method of a DUT interface and a VIP interface of the present invention for capturing the bus information of the VIP end in the SV file and the table file, and extracting the interface information of the VIP according to the bus information of the VIP end; Figure 4 The present invention provides a SOC bus structure and a corresponding verification environment schematic diagram of a configuration method of a DUT interface and a VIP interface. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0021] SOC is an important technology that promotes the development of the electronics field. The increase of SOC is part of the growing mainstream trend of integrated and embedded computing, which makes computing devices smaller, cheaper, faster and less power-hungry. From smartphones to tablets, IoT devices, routers, cameras, etc., SOC is everywhere. When verifying SOC, the verification environment needs to find the corresponding interfaces of DUT and VIP, and then manually input instructions to connect them. Only after the interfaces of DUT and VIP are connected can subsequent verification be carried out. When verifying different DUTs, the instructions need to be modified accordingly. In large-scale SOC scenarios, many files need to be changed manually, which will consume a lot of manual effort and affect the subsequent verification efficiency. An embodiment of the present invention provides a configuration method for DUT interface and VIP interface, which can capture the bus information of DUT according to the RTL file and table file written by the designer in the DUT design stage, capture the interface information of VIP according to the table file and SV file, and compare the interface information of DUT with the interface information of VIP, and interconnect the DUT and VIP with consistent interface information. When the interface of the DUT changes, the extracted interface information will also change accordingly. There is no need to manually modify the file, which saves a lot of manual effort and improves verification efficiency.

[0022] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings. The method provided in this embodiment uses Python scripts as carriers, which can flexibly realize functions such as data capture, configuration, execution, and simulation. The simulation script can be called by Python to realize the connection between the DUT interface and the VIP interface, thereby facilitating subsequent verification. Compared with the existing manual connection, it is more time-saving and labor-saving, and can greatly improve the verification efficiency. Figure 1 As shown, a configuration method of a DUT interface and a VIP interface provided in an embodiment of the present application may include the following steps: Step S1: Obtain a table file pre-filled with basic bus information, an RTL file that uniformly names the bus, and an SV file.

[0023] Specifically, the designer fills in the basic information of the bus in the EXCEL spreadsheet file during the SOC design phase, where the basic information of the bus mainly includes: bus type, input interface, output interface, bus width, naming format, etc., and writes the bus in the RTL file in a unified name in the form of "prefix + suffix", where the prefix is ​​the module where the bus is located, and the suffix is ​​the bus type, and declares the interface in the RTL file. It is a routine operation for designers to make spreadsheet files and write RTL files during the SOC design phase. The RTL file is written based on the information in the EXCEL spreadsheet file. Step S1 of this embodiment is intended to require designers to write the bus information according to a unified naming specification. VIP is a standardized verification component, and the interface information of VIP and the information of the bus connected to VIP are stored in the SV file. In the EXCEL spreadsheet file, the designer can also fill in the sending transaction type supported by the bus, and the corresponding transaction constraints can be generated later based on the sending transaction type.

[0024] Step S2: Capture the bus information of the DUT end in the RTL file and the table file, and extract the interface information of the DUT according to the bus information of the DUT end.

[0025] Specifically, Figure 2 As shown, the bus information of the DUT end in the table file and the RTL file with unified bus naming is captured, the bus information of the DUT end captured in the RTL file and the bus information of the DUT end captured in the table file are filtered, and it is determined whether the bus information of the DUT end captured in the RTL file and the bus information of the DUT end captured in the table file are consistent. If they are consistent, they are retained for subsequent interface information extraction, and if they are inconsistent, they are discarded. According to the filtered bus information of the DUT end, the valid interface information of the DUT is extracted. The RTL interface declaration is at the beginning of the file, and the bus information with the bus type keyword is captured. The bus information has prefix keywords such as input or output and suffix keywords corresponding to the bus type. The bus type in the bus information, the prefix and suffix in the bus information are extracted to obtain the valid interface information of the DUT.

[0026] Step S3: Capture the bus information of the VIP end in the SV file and the table file, and extract the interface information of the VIP according to the bus information of the VIP end.

[0027] Specifically, Figure 3As shown, the bus information of the VIP end in the SV file and the table file is captured, the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file are filtered, and it is determined whether the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file are consistent. If they are consistent, they are retained for subsequent interface information extraction, and if they are inconsistent, they are discarded. According to the filtered bus information of the VIP end, the effective VIP interface information is extracted.

[0028] Step S4: Compare the interface information of the DUT with the interface information of the VIP. If the interface information is consistent, interconnection is performed.

[0029] Specifically, the DUT interface signal and interface direction are obtained according to the effective DUT interface information, the corresponding bus is determined and selected according to the DUT interface signal, the DUT interface signal is connected to the signal in the selected corresponding bus, and the selected bus interface is connected to the VIP, thereby realizing the connection between the DUT interface and the VIP interface.

[0030] Furthermore, the extracted valid DUT interface information and valid VIP interface information need to be stored in a standard template file for subsequent reading and inspection. The interface file connecting VIP and DUT is generated according to the format of the template file by using the preset template file. After the interface file is generated, the interface file will be re-read to check the interface information inside, thereby improving the correctness of the interface configuration. The DUT interface and VIP are configured by the method of this embodiment. Once the configuration is successful, the interface of VIP and DUT can be connected, thereby reducing the need for the verification personnel to write additional code instructions to connect the interface of VIP and DUT. The corresponding transaction constraints can also be generated according to the sending transaction type filled in by the designer in the SOC design phase, thereby ensuring the consistency and integrity of the data during verification.

[0031] Furthermore, in the process of connecting the DUT interface and the VIP interface, the read and write signals on the selected bus interface will be captured, and it can be determined whether to generate a specific verification component based on the read and write signals and the bus information in the table file. Specifically, the verification component can be a collection coverage component. During the design phase, the designer determines whether a standardized verification component can be used for subsequent verification based on the design situation, and indicates it in the table file. If the information in the table file shows that a specific verification component is not generated, then no specific verification component is generated. The verification platform itself has a standardized verification component, and verification is achieved by using the standardized verification component; if the information in the table file shows that a specific verification component is generated, it means that a specific design needs to be verified, and the existing standardized verification components of the verification platform are no longer sufficient for verification, then a specific verification component is generated, and the VIP is encapsulated in a specific verification component to achieve verification under specific conditions.

[0032] The following uses the AHB to APB bus bridge ahb2apb module as an example. Figure 4 , for specific instructions: The first step is to obtain an EXCEL spreadsheet file, an RTL file, and an SV file. During the SOC design phase, the designer will fill in the basic information of the AHB bus and the APB bus in the EXCEL spreadsheet file, where the basic information of the AHB bus can be the AHB bus type, input interface, output interface, AHB bus bit width, naming format, the type of transaction supported by the AHB bus, whether specific condition verification is required, such as whether to collect coverage, etc. The basic information of the APB bus can be the APB bus type, input interface, output interface, APB bus bit width, naming format, the type of transaction supported by the APB bus, whether specific condition verification is required, i.e., whether to collect coverage, etc. The designer will write the RTL file to design the DUT based on the filled-in EXCEL spreadsheet file, and write the AHB bus and the APB bus into the RTL file in a unified name in the form of "prefix + suffix", and declare the interface information of the DUT at the beginning of the RTL file. The interface information of the VIP and the general configuration required by the bus are declared in the SV file.

[0033] The second step is to capture the bus information of the DUT end in the table file and the RTL file, and capture the bus information with the bus type keyword. The example of this embodiment captures the interface signal input AHB_HADDR_ahb2apb. The captured information is screened to determine whether the bus information input AHB_HADDR_ahb2apb of the DUT end captured from the RTL file and the bus information of the DUT end captured from the table file are consistent. If they are consistent, they are retained for subsequent interface information extraction. If they are inconsistent, they are discarded, thereby ensuring that the captured bus information is valid and correct bus information, that is, the interface signal input AHB_HADDR_ahb2apb is valid and correct bus information. According to the filtered bus information of the DUT end, the valid DUT interface information is extracted, that is, the keywords in the interface signal input AHB_HADDR_ahb2apb: input, AHB, HADDR, ahb2apb are extracted as valid DUT interface information.

[0034] The third step is to capture the bus information of the VIP end in the SV file and the table file. The example in this embodiment captures the HADDR interface signal. The bus information of the VIP end in the SV file and the bus information of the VIP end in the table file are filtered to determine whether the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file are consistent, that is, to determine whether the bus information HADDR of the VIP end captured from the SV file is consistent with the VIP interface signal HADDR pre-filled in the table. If they are consistent, they are retained for subsequent interface information extraction. If they are inconsistent, they are discarded. Valid VIP interface information is extracted based on the filtered bus information of the VIP end. The valid VIP interface information extracted in this embodiment is HADDR.

[0035] In the fourth step, the extracted valid DUT interface information and valid VIP interface information are stored in a preset template file, so that the valid DUT interface information and valid VIP interface information are generated according to the format of the template file to generate an interface file connecting VIP and DUT, thereby realizing the templating of interface information.

[0036] The fifth step is to compare the interface information of the DUT with the interface information of the VIP. According to the AHB extracted from the valid DUT interface information, it is determined that the AHB bus needs to be used. According to the extracted input, it is determined to be the input interface. According to the extracted HADDR, it is determined that the signal belongs to the HADDR signal in the AHB bus. According to the extracted ahb2apb, it is determined that the signal belongs to the ahb2apb module, and the signal in the AHB is connected to the DUT. According to the HADDR extracted from the valid VIP interface information, it is determined that the signal belongs to the HADDR signal in the AHB bus, which is consistent with the HADDR signal of the DUT. Connect the AHB VIP with the prefix and suffix of the AHB interface. Since the signal in the AHB is connected to the DUT and the prefix and suffix of the AHB interface are connected to the AHB VIP, the DUT interface and the VIP interface are interconnected.

[0037] In addition, by filling in the AHB supported sending transaction types and the APB supported sending transaction types in the Excel table, the corresponding transaction constraints are generated. By capturing the read and write signals on the AHB and APB interfaces, and based on the information in the Excel table, it is determined whether to generate a specific verification component and whether to generate the corresponding collection coverage component. If the bus information shows that a specific verification component is not generated, then no specific verification component is generated, and verification is achieved by using the standardized verification component owned by the verification platform itself; if the bus information shows that a specific verification component is generated, then the VIP can be encapsulated in a specific verification component to achieve specific conditional verification. During the configuration process, the interface file will be re-read to check the interface information in the interface file, thereby improving the correctness of the interface configuration.

[0038] Beneficial effects of the present invention: The present invention captures the bus information of the DUT end in the RTL file and the table file, extracts the interface information of the DUT according to the bus information of the DUT end, captures the bus information of the VIP end in the SV file and the table file, extracts the interface information of the VIP according to the bus information of the VIP end, and then compares the interface information of the DUT with the interface information of the VIP, interconnects the interfaces of the VIP and the DUT with consistent information to realize the configuration of the DUT interface and the VIP interface, eliminates the operation of manually inputting code instructions to control the connection between the DUT and the VIP, simplifies the verification process, and thus effectively improves the verification efficiency.

[0039] The present invention uniformly names the bus when writing the RTL file in the SOC design stage, so that the bus information is standardized, so that the interface information can be obtained by capturing the bus information in the verification stage, and the DUT and VIP are effectively interconnected using the interface information. The interface information is formed based on the bus declaration information configured in the SOC design stage. When dealing with large-scale SOC design, the DUT interface changes frequently, and the interface file generated during verification will also change accordingly, without manual modification, thereby achieving rapid response to bus modification and achieving the purpose of low latency.

[0040] The present invention can extract bus information based on the RTL file written by the designer in the DUT design stage and the SV file in the VIP, and can connect the VIP and the DUT according to the interface information. When the interface of the DUT changes, the extracted interface information will also change accordingly, without the need to manually change the file, saving a lot of manual effort, and reducing the errors caused by manual operation, thereby improving the verification efficiency and verification quality.

[0041] The present invention is described with reference to the flowcharts and / or block diagrams of the methods and configuration programs according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0042] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0043] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0044] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0045] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0046] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0047] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A method for configuring a DUT interface and a VIP interface, characterized in that: The following steps are involved: Obtain a table file pre-filled with basic bus information, an RTL file with unified bus naming, and an SV file; Capture the bus information of the DUT end in the RTL file and the table file, and extract the interface information of the DUT according to the bus information of the DUT end; Capture the bus information of the VIP end in the SV file and the table file, and extract the interface information of the VIP according to the bus information of the VIP end; The interface information of the DUT is compared with the interface information of the VIP, and interconnection is performed if the interface information is consistent.

2. A method for configuring a DUT interface and a VIP interface as claimed in claim 1, characterized in that: Capturing the bus information of the DUT end in the RTL file and the table file, and extracting the interface information of the DUT according to the bus information of the DUT end, specifically including: Capture the bus information of the DUT end in the RTL file and the table file; Filtering the bus information of the DUT end in the RTL file and the bus information of the DUT end in the table file; Valid DUT interface information is extracted based on the filtered bus information at the DUT end.

3. A method for configuring a DUT interface and a VIP interface as claimed in claim 2, characterized in that: Screening the bus information of the DUT end in the RTL file and the bus information of the DUT end in the table file specifically includes: It is determined whether the bus information of the DUT end in the RTL file is consistent with the bus information of the DUT end in the table file. If they are consistent, they are retained for subsequent interface information extraction; if they are inconsistent, they are discarded.

4. A method for configuring a DUT interface and a VIP interface as claimed in claim 2, characterized in that: Capture the bus information of the VIP end in the SV file and the table file, and extract the interface information of the VIP according to the bus information of the VIP end, specifically including: Capture the bus information of the VIP end in the SV file and the table file; Filtering the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file; The effective VIP interface information is extracted based on the bus information of the filtered VIP end.

5. A method for configuring a DUT interface and a VIP interface as claimed in claim 4, characterized in that: Filtering the bus information of the VIP end in the SV file and the bus information of the VIP end in the table file specifically includes: Determine whether the bus information of the VIP end in the SV file is consistent with the bus information of the VIP end in the table file. If they are consistent, keep them for subsequent interface information extraction. If they are inconsistent, discard them.

6. A method for configuring a DUT interface and a VIP interface as claimed in claim 4, characterized in that: Comparing the interface information of the DUT with the interface information of the VIP, and interconnecting them if the interface information is consistent, specifically including: The DUT interface signal and interface direction are obtained according to the valid DUT interface information, the corresponding bus is selected according to the DUT interface signal, the DUT interface signal is connected to the signal in the selected corresponding bus, and the selected bus interface is connected to the VIP, thereby realizing the connection between the DUT interface and the VIP interface.

7. A method for configuring a DUT interface and a VIP interface as claimed in claim 6, characterized in that: Comparing the interface information of the DUT with the interface information of the VIP, and interconnecting them if the interface information is consistent, specifically including: The read and write signals on the selected bus interface are captured, and the read and write signals are used to determine whether to generate a specific verification component.

8. A method for configuring a DUT interface and a VIP interface as claimed in claim 1, characterized in that: The basic bus information includes the sending transaction types supported by the bus, and corresponding transaction constraints can be generated according to the sending transaction types.

9. A method for configuring a DUT interface and a VIP interface as claimed in claim 4, characterized in that: Before comparing the interface information of the DUT with the interface information of the VIP, the method further includes: Fill the valid DUT interface information and the valid VIP interface information into a preset template file to generate an interface file, thereby realizing the templating of the interface information.

10. A method for configuring a DUT interface and a VIP interface as claimed in claim 9, characterized in that: Re-read the interface file and perform a verification check on the interface information.

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