Memory cell structure and manufacturing method thereof

Abstract

The invention relates to a memory cell structure and a manufacturing method thereof. The memory cell structure comprises a substrate and a capacitor structure, the capacitor structure is located above the substrate and comprises a first electrode structure, a capacitor dielectric layer and a second electrode structure which are sequentially arranged from bottom to top; wherein the first electrode structure is provided with at least one accommodating groove, and the second electrode structure is provided with at least one conductive column; the conductive columns are correspondingly embedded in the containing grooves. On the premise that the integration level of the memory unit structure is not affected, the effective areas of the electrode structure and the capacitor dielectric layer are increased, so that the polarization capability of the capacitor dielectric layer is improved, and the storage capability and the operation efficiency of the memory device structure are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage unit structure and a manufacturing method thereof. Background Art

[0002] Ferroelectric Random Access Memory (FRAM) is a memory device that integrates storage cells (CELLs) in the back-end of line (BEOL) process, and has the advantages of high speed, high density, low power consumption and radiation resistance. The storage cell of ferroelectric memory is composed of upper and lower electrodes and a capacitor medium (such as phase change material or ferroelectric material) in the middle, and the storage performance of ferroelectric memory is positively correlated with the effective area of ​​the storage layer material and the electrode layer material.

[0003] As semiconductor manufacturing processes tend to be miniaturized, the related art adopts a method of forming a storage unit between a first metal connection layer and a second metal connection layer to form a three-dimensional ferroelectric memory structure, thereby achieving the purpose of device miniaturization. However, this method easily causes the effective area of ​​the storage layer material and the electrode layer material in the ferroelectric memory to be reduced, and causes the polarization ability of the storage layer material to be reduced, thereby having an adverse effect on the storage capacity and operating efficiency of the memory device. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a storage unit structure and a manufacturing method thereof, which can increase the effective area of ​​the electrode structure and the capacitor dielectric layer without affecting the integration of the storage unit structure, so as to increase the polarization ability of the capacitor dielectric layer, thereby effectively improving the storage capacity and operating efficiency of the storage device structure.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a storage unit structure. The storage unit structure includes a substrate and a capacitor structure; the capacitor structure is located above the substrate and includes a first electrode structure, a capacitor dielectric layer, and a second electrode structure arranged in sequence from bottom to top; wherein the first electrode structure has at least one receiving groove, and the second electrode structure has at least one conductive column; each conductive column is correspondingly embedded in each receiving groove.

[0006] In some embodiments, there are multiple accommodating grooves and multiple conductive pillars; the accommodating grooves are distributed in an array on the first electrode structure; the conductive pillars are distributed in an array on the second electrode structure; wherein the accommodating grooves correspond to the conductive pillars one by one.

[0007] In some embodiments, the material of the first electrode structure and the second electrode structure both include tungsten.

[0008] In some embodiments, the substrate includes a transistor; the storage unit structure also includes a first dielectric layer, a first connection structure, a second dielectric layer, and a second connection structure; the first dielectric layer is located between the capacitor structure and the substrate, covering each transistor; the first connection structure is located in the first dielectric layer between the capacitor structure and the substrate, connecting the transistor to the first electrode structure; the second dielectric layer is located on the side of the first dielectric layer away from the substrate, covering the capacitor structure; the second connection structure is located in the second dielectric layer on the side of the capacitor structure away from the substrate, connecting the second electrode structure.

[0009] In some embodiments, the second connection structure and the second electrode structure are made of the same material.

[0010] On the other hand, the present disclosure also provides a method for manufacturing a storage unit structure according to some embodiments; the method for manufacturing the storage unit structure includes: providing a substrate; forming a first dielectric layer on one side of the substrate; forming a capacitor structure on a side of the first dielectric layer facing away from the substrate; the capacitor structure includes a first electrode structure, a capacitor dielectric layer and a second electrode structure arranged in sequence from bottom to top; wherein the first electrode structure has a receiving groove, and the second electrode structure has a conductive column; each conductive column is correspondingly embedded in each receiving groove.

[0011] In some embodiments, a capacitor structure is formed on a side of the first dielectric layer facing away from the substrate, including: forming a first electrode material layer on a side of the first dielectric layer facing away from the substrate; etching the first electrode material layer to form at least one receiving groove; forming a capacitor dielectric material layer on a side of the first electrode material layer facing away from the first dielectric layer; the capacitor dielectric material layer conformally covers the first electrode material layer and each receiving groove; forming a second electrode material layer on a side of the capacitor dielectric material layer facing away from the first electrode material layer; at least part of the second electrode material layer is filled in each receiving groove to form at least one conductive column; etching the first electrode material layer, the capacitor dielectric material layer, and the second electrode material layer to form a capacitor structure.

[0012] In some embodiments, the formation process of the second electrode material layer includes a thin film nucleation process.

[0013] In some embodiments, the substrate includes a transistor; the transistor includes a gate structure and an active area; before forming a capacitor structure on a side of the first dielectric layer away from the substrate, the manufacturing method also includes: etching the first dielectric layer to form a first contact hole and a second contact hole; forming a first connection structure in the first contact hole and forming an initial third connection structure in the second contact hole; the first connection structure is connected to the active area, and the initial third connection structure is connected to the gate structure; wherein the first electrode structure is connected to the first connection structure.

[0014] In some embodiments, after forming a capacitor structure on a side of the first dielectric layer away from the substrate, the manufacturing method further includes: forming a second dielectric layer on a side of the capacitor structure away from the first dielectric layer; etching the second dielectric layer to form a third contact hole and a fourth contact hole; forming a second connection structure in the third contact hole, and continuing to fill material in the fourth contact hole to form a third connection structure; the second connection structure is connected to the second electrode structure; and the third connection structure is connected to the gate structure.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, the capacitor dielectric layer is located between the first electrode structure and the second electrode structure, and at least one accommodating groove is formed in the first electrode structure of the capacitor structure, and at least one conductive column is formed in the second electrode structure, and each conductive column is correspondingly embedded in each accommodating groove. In this way, the embodiment of the present application increases the contact area between the first electrode structure and the second electrode structure of the capacitor structure by changing the internal structure of the first electrode structure and the second electrode structure of the capacitor structure without affecting the integration of the storage unit structure, thereby increasing the effective area of ​​the electrode structure and the capacitor dielectric layer, that is, increasing the polarization area of ​​the capacitor dielectric layer; thereby increasing the polarization ability of the capacitor dielectric layer, and effectively improving the storage capacity and operation efficiency of the storage device structure.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a storage unit structure provided in some embodiments;

[0020] Figure 2 Figure (a) is a schematic diagram of another storage unit structure provided in some embodiments. Figure 2 Figure (b) is a schematic cross-sectional view of the capacitor structure in the memory cell structure shown in Figure (a) at the AA' position;

[0021] Figure 3 A schematic flow chart of a method for manufacturing a memory cell structure provided in some embodiments;

[0022] Figure 4 A schematic diagram of a flow chart of step S300 provided in some embodiments;

[0023] Figure 5 A schematic flow chart of another method for manufacturing a memory cell structure provided in some embodiments;

[0024] Figure 6 A schematic flow chart of a method for manufacturing another memory cell structure provided in some embodiments;

[0025] Figure 7 A schematic diagram of a structure obtained after forming a first dielectric layer provided in some embodiments;

[0026] Figure 8 A schematic diagram of a structure obtained after forming a first contact hole and a second contact hole provided in some embodiments;

[0027] Fig. 9 A schematic structural diagram of a structure obtained after forming a first connection structure and an initial third connection structure provided in some embodiments;

[0028] Fig.10 A schematic diagram of a structure obtained after forming a first electrode material layer provided in some embodiments;

[0029] Fig.11 A schematic diagram of a structure obtained after forming a receiving groove provided in some embodiments;

[0030] Fig.12 Figure (a) is a schematic diagram of another structure obtained after forming a receiving groove in some embodiments. Fig.12 Figure (b) is a schematic cross-sectional view of the structure shown in Figure (a) at the AA' position;

[0031] Fig.13 A schematic diagram of a structure obtained after forming a capacitor dielectric material layer provided in some embodiments;

[0032] Fig.14 Figure (a) is a schematic diagram of another structure obtained after forming a capacitor dielectric material layer in some embodiments. Fig.14 Figure (b) is a schematic cross-sectional view of the structure shown in Figure (a) at the AA' position;

[0033] Fig.15 A schematic diagram of a structure obtained after forming a second electrode material layer provided in some embodiments;

[0034] Fig.16Figure (a) is a schematic diagram of another structure obtained after forming a second electrode material layer provided in some embodiments, Fig.16 Figure b) is a schematic cross-sectional view of the structure shown in Figure (a) at the AA' position;

[0035] Fig.17 A schematic diagram of a structure obtained after forming a capacitor structure provided in some embodiments;

[0036] Fig.18 A schematic diagram of a structure obtained after an etching opening is formed in some embodiments;

[0037] Fig.19 A schematic diagram of a structure obtained after grinding the second electrode material layer provided in some embodiments;

[0038] Fig. 20 A schematic diagram of a structure obtained after forming a second dielectric layer provided in some embodiments;

[0039] Fig.21 A schematic structural diagram of a structure obtained after forming a third contact hole and a fourth contact hole provided in some embodiments.

[0040] Description of reference numerals:

[0041] 1-base, 11-substrate, T-transistor, AA-active area, G-gate structure, G1-gate dielectric layer, G2-gate conductive layer, G3-sidewall structure, 2-capacitor structure, 21-first electrode structure, 210-first electrode material layer, 211-accommodating groove, 22-capacitor dielectric layer, 220-capacitor dielectric material layer, 23-second electrode structure, 230-second electrode material layer, 231-conductive column, 3-first dielectric layer, 4-second dielectric layer, 51-first connection structure, 52-second connection structure, 530-initial third connection structure, 53-third connection structure, H1-first contact hole, H2-second contact hole, H3-third contact hole, H4-fourth contact hole. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0045] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0047] The embodiments of the present application provide a storage unit structure and a method for manufacturing the same, which can increase the effective area of ​​the electrode structure and the capacitor dielectric layer without affecting the integration of the storage unit structure, so as to increase the polarization ability of the capacitor dielectric layer, thereby effectively improving the storage capacity and operating efficiency of the storage device structure.

[0048] In some embodiments, see Figure 1The storage unit structure includes a substrate 1 and a capacitor structure 2; the capacitor structure 2 is located above the substrate 1, and includes a first electrode structure 21, a capacitor dielectric layer 22, and a second electrode structure 23 arranged in sequence from bottom to top; wherein the first electrode structure 21 has at least one receiving groove 211, and the second electrode structure 23 has at least one conductive column 231; each conductive column 231 is correspondingly embedded in each receiving groove 211.

[0049] By way of example, the memory cell structure includes but is not limited to a three-dimensional (3D) memory; the memory cell structure may be, for example, a three-dimensional ferroelectric random access memory (FRAM) or a three-dimensional phase change memory.

[0050] In some embodiments, the base 1 includes a substrate 11 and a transistor T disposed on the substrate 11 .

[0051] For example, the substrate 11 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 11 can be a single-layer structure or a multi-layer structure. For example, the substrate 11 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 11 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 11 should not limit the scope of protection of the present application.

[0052] In some embodiments, the transistor T includes an active area AA and a gate structure G; the active area AA is located in the substrate 11 ; and the gate structure G is located on a side of the active area AA away from the substrate 11 in a second direction (eg, Y direction).

[0053] In some examples, the gate structure G includes a gate dielectric layer G1, a gate conductive layer G2, and a sidewall structure G3; the gate dielectric layer G1 is located on a side of the active area AA that is away from the substrate 11 in the second direction (for example, the Y direction); the gate conductive layer G2 is located on a side of the gate dielectric layer G1 that is away from the active area AA in the second direction (for example, the Y direction); and the sidewall structure G3 is located on both sides of the gate dielectric layer G1 and the gate conductive layer G2 in the first direction (for example, the X direction).

[0054] In some examples, the orthographic projection of the capacitor structure 2 on the substrate 1 is located on one side of the gate structure G in the first direction (eg, the X direction).

[0055] It should be noted that the first electrode structure 21 , the capacitor dielectric layer 22 and the second electrode structure 23 are arranged in sequence from bottom to top in the second direction (eg, the Y direction).

[0056] In the embodiment of the present application, the capacitor dielectric layer 22 is located between the first electrode structure 21 and the second electrode structure 23, and at least one receiving groove 211 is formed in the first electrode structure 21 of the capacitor structure 2, and at least one conductive pillar 231 is formed in the second electrode structure 23, and each conductive pillar 231 is correspondingly embedded in each receiving groove 211. In this way, the embodiment of the present application increases the contact area between the first electrode structure 21 and the second electrode structure 23 of the capacitor structure 2 by changing the internal structure without affecting the integration of the storage unit structure, thereby increasing the effective area of ​​the electrode structure and the capacitor dielectric layer 22, that is, increasing the polarization area of ​​the capacitor dielectric layer 22; thereby increasing the polarization ability of the capacitor dielectric layer 22, and effectively improving the storage capacity and operation efficiency of the storage device structure.

[0057] In some embodiments, see Figure 2 , the number of the accommodating grooves 211 and the number of the conductive pillars 231 are both multiple; the accommodating grooves 211 are distributed in an array on the first electrode structure 21; the conductive pillars 231 are distributed in an array on the second electrode structure 23; wherein the accommodating grooves 211 correspond to the conductive pillars 231 one by one.

[0058] It should be noted that Figure 2 The arrangement of the receiving grooves 211 and the conductive pillars 231 in a 3*3 array is used as an example for illustration, but it can be understood that the number of rows and columns of the receiving grooves 211 and the conductive pillars 231 can be other values, and the present application does not impose any limitation on this.

[0059] In some examples, the receiving grooves 211 correspond to the conductive pillars 231 one by one, and the shapes of the corresponding receiving grooves 211 and the conductive pillars 231 match each other.

[0060] For example, the shape of the receiving groove 211 includes but is not limited to a circular groove, a rectangular groove, a prismatic groove or a special-shaped groove.

[0061] By way of example, the shape of the conductive pillar 231 includes but is not limited to a circular pillar, a rectangular pillar, a prism, or a special-shaped pillar.

[0062] In the embodiment of the present application, by forming a plurality of receiving grooves 211 in the first electrode structure 21, forming a plurality of conductive pillars 231 in the second electrode structure 23, and embedding each conductive pillar 231 in each receiving groove 211, the area of ​​the contact interface between each conductive pillar 231 and each receiving groove 211 is significantly increased without changing the volume of the capacitor structure 2, thereby effectively increasing the effective area of ​​the electrode structure and the capacitor dielectric layer 22, that is, increasing the polarization area of ​​the capacitor dielectric layer 22.

[0063] In some embodiments, the first electrode structure 21 and the second electrode structure 23 are made of the same material.

[0064] In some examples, the materials of the first electrode structure 21 and / or the second electrode structure 23 include, but are not limited to, conductive metals.

[0065] Illustratively, the first electrode structure 21 and the second electrode structure 23 both include tungsten (W).

[0066] For example, the material of the capacitor dielectric layer 22 includes a ferroelectric material or a high dielectric (Hight-K, HK for short) material.

[0067] In the embodiment of the present application, using tungsten (W) as the material of the first electrode structure 21 and the second electrode structure 23 can effectively improve the polarization ability of the capacitor dielectric layer 22, thereby improving the storage capacity and operation efficiency of the storage device structure.

[0068] In some embodiments, see Figure 1 or Figure 2 The storage unit structure also includes a first dielectric layer 3, a first connection structure 51, a second dielectric layer 4 and a second connection structure 52; the first dielectric layer 3 is located between the capacitor structure 2 and the substrate 1, covering each transistor T; the first connection structure 51 is located in the first dielectric layer 3 between the capacitor structure 2 and the substrate 1, connecting the transistor T and the first electrode structure 21; the second dielectric layer 4 is located on the side of the first dielectric layer 3 away from the substrate 1, covering the capacitor structure 2; the second connection structure 52 is located in the second dielectric layer 4 on the side of the capacitor structure 2 away from the substrate 1, connecting the second electrode structure 23.

[0069] In some embodiments, the memory cell structure further includes a third connection structure 53 ; the third connection structure 53 is located in the first dielectric layer 3 and the second dielectric layer 4 on the side of the gate structure G away from the substrate 11 , and is connected to the gate structure G of the transistor T.

[0070] For example, the first connection structure 51 , the second connection structure 52 and / or the third connection structure 53 all include but are not limited to metal wires.

[0071] For example, the first connection structure 51 is electrically connected to the active area AA of the transistor T and the first electrode of the capacitor structure 2; the second connection structure 52 is electrically connected to the second electrode of the capacitor structure 2; and the third connection structure 53 is electrically connected to the gate conductive layer G2 of the gate structure G.

[0072] In some examples, the first dielectric layer 3 covers the transistor T and is filled between the first connection structure 51 and the third connection structure 53 ; and is used to achieve electrical isolation between the first connection structure 51 and the gate structure G and the third connection structure 53 .

[0073] In some examples, the second dielectric layer 4 covers the capacitor structure 2 and fills between the third connection structure 53 and the second connection structure 52 , and is used to achieve electrical isolation between the third connection structure 53 and the capacitor structure 2 and the second connection structure 52 .

[0074] By way of example, the material of the first dielectric layer 3 includes, but is not limited to, an insulating material; the insulating material may be, for example, oxide (OX).

[0075] By way of example, the material of the second dielectric layer 4 includes, but is not limited to, an insulating material; the insulating material may be, for example, oxide (OX).

[0076] In some examples, the first dielectric layer 3 and the second dielectric layer 4 are made of the same material; the first dielectric layer 3 and the second dielectric layer 4 may be an integral structure.

[0077] In some embodiments, the second connection structure 52 and the second electrode structure 23 are made of the same material.

[0078] In some embodiments, the first connection structure 51 and the first electrode structure 21 are made of the same material.

[0079] By way of example, the material of the second connection structure 52 includes, but is not limited to, a conductive metal; the material of the second connection structure 52 may be, for example, tungsten (W).

[0080] By way of example, the material of the first connection structure 51 includes, but is not limited to, a conductive metal; the material of the first connection structure 51 may be, for example, tungsten (W).

[0081] In the embodiment of the present application, the second connection structure 52 and the second electrode structure 23 are made of the same material, which can effectively reduce the contact resistance between the second connection structure 52 and the second electrode structure 23; the first connection structure 51 and the first electrode structure 21 are made of the same material, which can effectively reduce the contact resistance between the first connection structure 51 and the first electrode structure 21, which is beneficial to improving the polarization ability of the capacitor dielectric layer 22, so as to effectively improve the storage capacity and operating efficiency of the storage device structure.

[0082] The present application also provides a method for manufacturing a memory cell structure according to some embodiments, and the method for manufacturing the memory cell structure can be used to prepare the memory cell structure in some of the above embodiments. The method for manufacturing the memory cell structure also possesses the technical advantages of the above memory cell structure. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0083] In some embodiments, see Figure 3 , the manufacturing method of the memory cell structure includes the following steps S100~S300.

[0084] S100, providing a substrate.

[0085] S200 , forming a first dielectric layer on one side of the substrate.

[0086] S300, forming a capacitor structure on the side of the first dielectric layer away from the substrate; the capacitor structure includes a first electrode structure, a capacitor dielectric layer and a second electrode structure arranged in sequence from bottom to top; wherein the first electrode structure has a receiving groove, and the second electrode structure has a conductive column; each conductive column is correspondingly embedded in each receiving groove.

[0087] In the embodiment of the present application, at least one accommodating groove is formed in the first electrode structure of the capacitor structure, at least one conductive pillar is formed in the second electrode structure, and each conductive pillar is correspondingly embedded in each accommodating groove. In this way, the embodiment of the present application increases the contact area between the first electrode structure and the second electrode structure of the capacitor structure by changing the internal structure of the first electrode structure and the second electrode structure of the capacitor structure without affecting the integration of the storage unit structure, thereby increasing the effective area of ​​the electrode structure and the capacitor dielectric layer, that is, increasing the polarization area of ​​the capacitor dielectric layer; thereby increasing the polarization ability of the capacitor dielectric layer, and effectively improving the storage capacity and operation efficiency of the storage device structure.

[0088] In some embodiments, see Figure 4 , step S300 includes the following steps S310~S350.

[0089] S310, forming a first electrode material layer on a side of the first dielectric layer facing away from the substrate.

[0090] S320, etching the first electrode material layer to form at least one receiving groove.

[0091] S330, forming a capacitor dielectric material layer on a side of the first electrode material layer away from the first dielectric layer; the capacitor dielectric material layer conformally covers the first electrode material layer and each receiving groove.

[0092] S340, forming a second electrode material layer on a side of the capacitor dielectric material layer away from the first electrode material layer; at least a portion of the second electrode material layer is filled in each receiving groove to form at least one conductive column.

[0093] S350, etching the first electrode material layer, the capacitor dielectric material layer and the second electrode material layer to form a capacitor structure.

[0094] In some embodiments, the substrate includes a transistor; the transistor includes a gate structure and an active region; see Figure 5 Before step S300, the manufacturing method further includes the following steps S410~S420.

[0095] S410, etching the first dielectric layer to form a first contact hole and a second contact hole.

[0096] S420, forming a first connection structure in the first contact hole, and forming an initial third connection structure in the second contact hole; the first connection structure is connected to the active area, and the initial third connection structure is connected to the gate structure; wherein the first electrode structure is connected to the first connection structure.

[0097] In some embodiments, see Figure 6 , after step S300, the manufacturing method further includes the following steps S510~S530.

[0098] S510 , forming a second dielectric layer on a side of the capacitor structure away from the first dielectric layer.

[0099] S520, etching the second dielectric layer to form a third contact hole and a fourth contact hole.

[0100] S530, forming a second connection structure in the third contact hole, and continuing to fill the material in the fourth contact hole to form a third connection structure; the second connection structure is connected to the second electrode structure; and the third connection structure is connected to the gate structure.

[0101] It should be understood that although Figure 3~Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3~Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0102] In order to more clearly illustrate the manufacturing method of the memory cell structure in some of the above embodiments, the following embodiments are combined with Figure 7 to Figure 21 Understand.

[0103] In some embodiments, the method for manufacturing a memory cell structure includes the following steps S100 to S300.

[0104] In step S100 , a substrate 1 is provided.

[0105] For some examples, see Figure 7 The substrate 1 includes a substrate 11 and a transistor T arranged on the substrate 11; the transistor T includes an active area AA and a gate structure G; the active area AA is located in the substrate 11; the gate structure G is located on a side of the active area AA away from the substrate 11 in a second direction (for example, a Y direction); the gate structure G includes a gate dielectric layer G1, a gate conductive layer G2 and a sidewall structure G3; the gate dielectric layer G1 is located on a side of the active area AA away from the substrate 11 in the second direction (for example, a Y direction); the gate conductive layer G2 is located on a side of the gate dielectric layer G1 away from the active area AA in the second direction (for example, a Y direction); and the sidewall structure G3 is located on both sides of the gate dielectric layer G1 and the gate conductive layer G2 in a first direction (for example, a X direction).

[0106] In step S200, please continue to refer to Figure 7 , a first dielectric layer 3 is formed on one side of the substrate 1 .

[0107] By way of example, the first dielectric layer 3 is located on a side of the gate structure G facing away from the substrate 11 , and the first dielectric layer 3 covers the gate structure G.

[0108] By way of example, the formation process of the first dielectric layer 3 includes but is not limited to a deposition process (Dielectric Enhancement Process, DEP for short).

[0109] By way of example, the material of the first dielectric layer 3 includes, but is not limited to, an insulating material; the insulating material may be, for example, oxide (OX).

[0110] In some embodiments, before step S300, the manufacturing method further includes the following steps S410 to S420.

[0111] In step S410, refer to Figure 8 , the first dielectric layer 3 is etched to form a first contact hole H1 and a second contact hole H2.

[0112] For example, the etching process of the first dielectric layer 3 includes but is not limited to a dry etching process (Dry Etch); the etching process of the first dielectric layer 3 may be, for example, a photolithography process.

[0113] Please refer to Figure 8 The first contact hole H1 exposes the surface of the active area AA away from the substrate 11 in the second direction (eg, Y direction); the second contact hole H2 exposes the surface of the gate conductive layer G2 away from the substrate 11 in the second direction (eg, Y direction).

[0114] By way of example, the shapes of the first contact hole H1 and / or the second contact hole H2 include but are not limited to a circular hole, a rectangular hole, a prismatic hole, or a special-shaped hole.

[0115] In step S420, refer to Fig. 9 , a first connection structure 51 is formed in the first contact hole H1, and an initial third connection structure 530 is formed in the second contact hole H2; the first connection structure 51 is connected to the active area AA, and the initial third connection structure 530 is connected to the gate structure G.

[0116] By way of example, the formation process of the first connection structure 51 and / or the initial third connection structure 530 includes, but is not limited to, a filling process.

[0117] For example, the first connection structure 51 is electrically connected to the active area AA; and the initial third connection structure 530 is electrically connected to the gate structure G.

[0118] In step S300, a capacitor structure 2 is formed on the side of the first dielectric layer 3 facing away from the substrate 1; the capacitor structure 2 includes a first electrode structure 21, a capacitor dielectric layer 22 and a second electrode structure 23 arranged in sequence from bottom to top; wherein the first electrode structure 21 has a receiving groove 211, and the second electrode structure 23 has a conductive column 231; each conductive column 231 is correspondingly embedded in each receiving groove 211.

[0119] Correspondingly, the first electrode structure 21 is connected to the first connection structure 51 .

[0120] In some embodiments, step S300 includes the following steps S310 to S350.

[0121] In step S310, refer to Fig.10 , a first electrode material layer 210 is formed on a side of the first dielectric layer 3 facing away from the substrate 1 .

[0122] For example, the formation process of the first electrode material layer 210 includes but is not limited to a deposition process (Dielectric Enhancement Process, DEP for short).

[0123] By way of example, the material of the first electrode material layer 210 includes, but is not limited to, a conductive metal; the material of the second connection structure 52 may be, for example, tungsten (W).

[0124] In step S320, refer to Fig.11, etching the first electrode material layer 210 to form at least one receiving groove 211 .

[0125] For example, the etching process of the first electrode material layer 210 includes but is not limited to a dry etching process (Dry Etch); the etching process of the first dielectric layer 3 may be, for example, a photolithography process.

[0126] In some embodiments, see Fig.12 There are multiple containing grooves 211 , and the containing grooves 211 are distributed in an array on the first electrode structure 21 .

[0127] In step S330, refer to Fig.13 A capacitor dielectric material layer 220 is formed on the side of the first electrode material layer 210 away from the first dielectric layer 3 ; the capacitor dielectric material layer 220 conformally covers the first electrode material layer 210 and each receiving groove 211 .

[0128] For example, the material of the capacitor dielectric material layer 220 includes a ferroelectric material or a high dielectric (Hight-K, HK for short) material.

[0129] For example, the formation process of the capacitor dielectric layer 22 includes but is not limited to a deposition process (Dielectric Enhancement Process, DEP for short).

[0130] In some embodiments, see Fig.14 When there are multiple accommodating grooves 211, the capacitor dielectric material layer 220 conformally covers the bottom and side walls of each accommodating groove 211; in this way, the embodiment of the present application can effectively increase the contact area between the capacitor dielectric layer 22 and the first electrode structure 21 in the capacitor structure 2, increase the effective area of ​​the capacitor dielectric layer 22, that is, increase the polarization area of ​​the capacitor dielectric layer 22, thereby increasing the polarization ability of the capacitor dielectric layer 22.

[0131] In step S340, refer to Fig.15 , a second electrode material layer 230 is formed on a side of the capacitor dielectric material layer 220 away from the first electrode material layer 210 ; at least a portion of the second electrode material layer 230 is filled in each receiving groove 211 to form at least one conductive column 231 .

[0132] By way of example, the material of the second electrode material layer 230 includes, but is not limited to, a conductive metal; the material of the second electrode material layer 230 may be, for example, tungsten (W).

[0133] For example, the formation process of the second electrode material layer 230 includes but is not limited to a deposition process (Dielectric Enhancement Process, DEP for short).

[0134] In some embodiments, see Fig.16 In the case where there are multiple accommodating grooves 211 and multiple conductive pillars 231, multiple conductive pillars 231 are correspondingly embedded in each accommodating groove 211 and contact the bottom and side wall of the capacitor dielectric material layer 220 in each accommodating groove 211; in this way, the embodiment of the present application can effectively increase the contact area between the second electrode structure 23 and the capacitor dielectric layer 22 in the capacitor structure 2, increase the effective area of ​​the capacitor dielectric layer 22, that is, increase the polarization area of ​​the capacitor dielectric layer 22, thereby increasing the polarization ability of the capacitor dielectric layer 22.

[0135] In some embodiments, the formation process of the second electrode material layer 230 includes a thin film nucleation (NUC) process.

[0136] It should be noted that the thin film nucleation (NUC) process refers to the process in which atoms, molecules or ions of the deposited material gather on the surface of the target material to form tiny nuclei or starting points during the coating process of the semiconductor layer structure. During the deposition process of the thin film nucleation process, the reaction activity of the precursor of the target material is high, which can effectively reduce the surface protrusions of the deposited material (such as tungsten). In the embodiment of the present application, by adopting the thin film nucleation process to prepare the electrode structure, the problem of uneven deposition of the conductive pillar 231 in the receiving groove 211 can be effectively prevented, and when the receiving groove 211 is densely distributed, a high-quality conductive pillar 231 can also be formed, avoiding the defect (Seam) problem of the conductive pillar 231 in the electrode structure, and effectively improving the stability of the capacitor structure 2, thereby effectively improving the storage capacity and operation stability of the storage device structure.

[0137] Illustratively, the process of forming the first electrode material layer 210 includes a thin film nucleation (NUC) process.

[0138] It should be noted that, in the thin film nucleation process, the growth thickness of the first electrode material layer 210 and / or the second electrode material layer 230 can be controlled by controlling the flow rate of the reaction gas and the number of cycles of the precursor.

[0139] In step S350, refer to Fig.17 , the first electrode material layer 210 , the capacitor dielectric material layer 220 and the second electrode material layer 230 are etched to form a capacitor structure 2 .

[0140] For example, in this step, the etching process of the first electrode material layer 210 , the capacitor dielectric material layer 220 , and the second electrode material layer 230 includes but is not limited to a dry etching process (Dry Etch); for example, it may be a photolithography process.

[0141] It should be added that during the etching process of the second electrode material layer 230 , a pre-etching process may be performed first to etch the second electrode material layer 230 to a target thickness before etching the first electrode material layer 210 , the capacitor dielectric material layer 220 and the second electrode material layer 230 as a whole.

[0142] For example, the pre-etching process includes: see Fig.18 , etching the second electrode material layer 230 above the receiving groove 211 and the conductive pillar 231 to form an etching opening; see Fig.19 According to the etching opening, grind the remaining portion of the second electrode material layer 230 so that the surface of the second electrode material layer 230 away from the capacitor dielectric material layer 220 in the second direction (eg, the Y direction) is flush with the bottom of the etching opening, so that the second electrode material layer 230 reaches the target thickness.

[0143] For example, the polishing process of the first electrode material layer 210 includes but is not limited to a chemical mechanical polishing (CMP) process.

[0144] It should be noted that the first electrode material layer 210, the capacitor dielectric material layer 220 and the second electrode material layer 230 are etched so that the retained portion of the first electrode material layer 210 serves as the first electrode structure 21, the retained portion of the capacitor dielectric material layer 220 serves as the capacitor dielectric layer 22, and the retained portion of the second electrode material layer 230 serves as the second electrode structure 23, and the first electrode structure 21, the capacitor dielectric layer 22 and the second electrode structure 23 constitute a capacitor structure 2; wherein the positive projection of the capacitor structure 2 on the substrate 1 is located on one side of the gate structure G of the transistor T.

[0145] In some embodiments, after step S300, the manufacturing method further includes the following steps S510 to S530.

[0146] In step S510, refer to Fig. 20 , a second dielectric layer 4 is formed on a side of the capacitor structure 2 away from the first dielectric layer 3 .

[0147] By way of example, the material of the second dielectric layer 4 includes, but is not limited to, an insulating material; the insulating material may be, for example, oxide (OX).

[0148] In some examples, the first dielectric layer 3 and the second dielectric layer 4 are made of the same material; the first dielectric layer 3 and the second dielectric layer 4 may be an integral structure.

[0149] In step S520, refer to Fig.21 , the second dielectric layer 4 is etched to form a third contact hole H3 and a fourth contact hole H4.

[0150] It is worth mentioning that in some embodiments of the present application, the material of the second electrode structure 23 includes tungsten (W). During the etching process of the third contact hole H3, the second electrode material can be reused as an etching stop layer of the third contact hole H3. In this way, the capacitor dielectric layer 22 can be protected during the etching process of the third contact hole H3 of the storage unit structure (for example, a three-dimensional ferroelectric memory), thereby effectively preventing the damage of the capacitor structure 2 caused by the deep hole etching process, and effectively improving the storage capacity and operation stability of the storage device structure.

[0151] For example, the etching process of the second dielectric layer 4 includes but is not limited to a dry etching process (Dry Etch); the etching process of the first dielectric layer 3 may be, for example, a photolithography process.

[0152] Please refer to Fig.21 The third contact hole H3 exposes the surface of the second electrode structure 23 away from the capacitor dielectric layer 22 in the second direction (eg, Y direction); the fourth contact hole H4 exposes the surface of the initial third connection structure 530 away from the gate structure G in the second direction (eg, Y direction).

[0153] By way of example, the shapes of the third contact hole H3 and / or the fourth contact hole H4 include but are not limited to a circular hole, a rectangular hole, a prismatic hole or a special-shaped hole.

[0154] Illustratively, a size of the fourth contact hole H4 in the first direction (eg, X direction) is the same as a size of the initial third connection structure 530 in the first direction (eg, X direction).

[0155] Illustratively, the fourth contact hole H4 has the same shape as the initial third connection structure 530 .

[0156] In step S530, refer to Figure 1 , a second connection structure 52 is formed in the third contact hole H3, and material is continuously filled in the fourth contact hole H4 to form a third connection structure 53; the second connection structure 52 is connected to the second electrode structure 23; and the third connection structure 53 is connected to the gate structure G.

[0157] By way of example, the forming process of the second connection structure 52 and / or the third connection structure 53 includes but is not limited to a filling process.

[0158] For example, the second connection structure 52 is electrically connected to the second electrode structure 23; the third connection structure 53 is electrically connected to the gate structure G. For example, the memory cell structure includes but is not limited to a three-dimensional (3D) memory; the memory cell structure may be, for example, a three-dimensional ferroelectric random access memory (FRAM) or a three-dimensional phase change memory.

[0159] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0160] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A storage unit structure, characterized in that: include: substrate; A capacitor structure, located above the substrate, comprising a first electrode structure, a capacitor dielectric layer, and a second electrode structure arranged in sequence from bottom to top; The first electrode structure has at least one receiving groove, and the second electrode structure has at least one conductive column; each conductive column is correspondingly embedded in each receiving groove.

2. The storage unit structure according to claim 1, characterized in that: The number of the receiving grooves and the number of the conductive pillars are both multiple; the receiving grooves are distributed in an array on the first electrode structure; the conductive pillars are distributed in an array on the second electrode structure; wherein the receiving grooves correspond to the conductive pillars one by one.

3. The storage unit structure according to claim 1, characterized in that: The materials of the first electrode structure and the second electrode structure both include tungsten.

4. The storage unit structure according to any one of claims 1 to 3, characterized in that: The substrate includes a transistor; the memory cell structure also includes: A first dielectric layer, located between the capacitor structure and the substrate, covering each of the transistors; A first connecting structure, located in the first dielectric layer between the capacitor structure and the substrate, connecting the transistor and the first electrode structure; A second dielectric layer, located on a side of the first dielectric layer away from the substrate, covering the capacitor structure; The second connecting structure is located in the second dielectric layer on a side of the capacitor structure away from the substrate and is connected to the second electrode structure.

5. The storage unit structure according to claim 4, characterized in that: The second connection structure and the second electrode structure are made of the same material.

6. A method for manufacturing a memory cell structure, characterized in that: include: providing a substrate; forming a first dielectric layer on one side of the substrate; A capacitor structure is formed on the side of the first dielectric layer away from the substrate; the capacitor structure includes a first electrode structure, a capacitor dielectric layer and a second electrode structure arranged in sequence from bottom to top; wherein the first electrode structure has a receiving groove, and the second electrode structure has a conductive column; each of the conductive columns is correspondingly embedded in each of the receiving grooves.

7. The method for manufacturing a memory cell structure according to claim 6, characterized in that: The capacitor structure is formed on a side of the first dielectric layer away from the substrate, comprising: forming a first electrode material layer on a side of the first dielectric layer facing away from the substrate; Etching the first electrode material layer to form at least one containing groove; forming a capacitor dielectric material layer on a side of the first electrode material layer away from the first dielectric layer; the capacitor dielectric material layer conformally covers the first electrode material layer and each of the containing grooves; forming a second electrode material layer on a side of the capacitor dielectric material layer away from the first electrode material layer; at least a portion of the second electrode material layer is filled in each of the receiving grooves to form at least one conductive column; The first electrode material layer, the capacitor dielectric material layer and the second electrode material layer are etched to form a capacitor structure.

8. The method for manufacturing a memory cell structure according to claim 7, characterized in that: The formation process of the second electrode material layer includes a thin film nucleation process.

9. The method for manufacturing a memory cell structure according to claim 6, wherein: The substrate includes a transistor; the transistor includes a gate structure and an active region; Before forming the capacitor structure on the side of the first dielectric layer facing away from the substrate, the manufacturing method further includes: Etching the first dielectric layer to form a first contact hole and a second contact hole; A first connection structure is formed in the first contact hole, and an initial third connection structure is formed in the second contact hole; the first connection structure is connected to the active area, and the initial third connection structure is connected to the gate structure; Wherein, the first electrode structure is connected to the first connecting structure.

10. The method for manufacturing a memory cell structure according to claim 9, characterized in that: After forming the capacitor structure on the side of the first dielectric layer facing away from the substrate, the manufacturing method further includes: forming a second dielectric layer on a side of the capacitor structure away from the first dielectric layer; Etching the second dielectric layer to form a third contact hole and a fourth contact hole; A second connection structure is formed in the third contact hole, and material is continuously filled in the fourth contact hole to form a third connection structure; the second connection structure is connected to the second electrode structure; and the third connection structure is connected to the gate structure.

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