Structure for prolonging transient turn-off non-breakdown time of SOI LDMOS (silicon on insulator laterally diffused metal oxide semiconductor) power device and preparation method
By introducing buried oxygen layer thickening areas into SOI LDMOS devices, the longitudinal electric field distribution is optimized, and the problem of short device transient shutdown without breakdown time is solved, and a wider operating frequency range and lower cost are achieved, while alleviating the autothermal effect.
Patent Information
- Application Number
- CN202411542816.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-14
AI Technical Summary
The non-breakdown time of existing SOI LDMOS devices is short when they are turned off in a transient manner, resulting in limited frequency range in which the device operates at high frequencies, and the process is difficult and costly.
By introducing the top silicon concave area below the drift area and drain end of the SOI LDMOS device and forming a thickened area on the corresponding buried oxygen layer, the longitudinal electric field distribution of the device is optimized, thereby improving the transient withstand voltage and shutdown of the device No breakdown time.
It effectively improves the device's shutdown and breakdown time, makes the device's frequency range of operation at high frequencies, and at the same time reduces the difficulty and cost of process implementation, alleviates the self-heating effect and maintains a low specific on-resistance.
Smart Images
Figure CN119451175A_ABST
Abstract
Description
Technical Field
[0001] The invention provides a structure for improving the transient turn-off non-breakdown time of a SOI LDMOS power device and a preparation method thereof, belonging to the technical field of semiconductors. Background Art
[0002] SOI LDMOS is Silicon-On-Insulator (SOI), Lateral Double-diffused MOS (LDMOS).
[0003] SOI LDMOS withstand voltage is divided into two types: static and transient (also known as dynamic). Most of the existing research results are static withstand voltage. When SOI LDMOS is used as a switching device in an application, a deep depletion effect will appear in the substrate, and the shorter the device is turned off and the lower the temperature, the longer this effect will last. The withstand voltage of the device in the switching state is the transient withstand voltage, which is very different from the static withstand voltage. The main reason is the appearance of the substrate deep depletion effect. Unlike the static withstand voltage, the transient withstand voltage is greatly affected by the substrate doping concentration distribution.
[0004] Transient withstand voltage is the withstand voltage when the device is just turned off. After the device is turned off, the deep depletion layer of the substrate will decrease with the increase of time, and the withstand voltage of the device will also decrease accordingly and will be broken down immediately. Therefore, transient withstand voltage can only be used as a reference for the withstand voltage performance of SOI LDMOS switch devices. Define a turn-off non-breakdown time: when the device is turned off, a DC voltage value less than the transient withstand voltage is applied to the drain terminal, and the time the device remains unbroken. Its significance lies in the frequency range in which the device can operate under a certain high voltage. For example, at a drain voltage of 400V, the turn-off non-breakdown time is 100us. If the duty cycle of the device switching time is 50%, then the minimum operating frequency of the device is 5kHz. Obviously, the longer the turn-off non-breakdown time, the lower the lower limit of the switching frequency of the device, and the wider the operating frequency range.
[0005] The structure of improving the transient withstand voltage of SOI LDMOS is generally to optimize the substrate doping concentration distribution, and then optimize the substrate depletion layer charge distribution, and finally achieve a beneficial modulation of the drift region electric field, so that the transient withstand voltage can be improved. Since the substrate doping concentration distribution needs to be changed, the process of implementing this type of device is difficult and costly, and there has been no report on the manufacture and experiment of the device so far. As for the research on improving the turn-off non-breakdown time alone, there is even less research.
[0006] Figure 1The structure of one of the improved devices provided by "Substrate Engineering for Improved Transient Breakdown Voltage in SOI Lateral Power MOS" is shown. The top part is a conventional SOI LDMOS. The innovation lies in the substrate region, which is laterally divided into a high-doped region under the source and gate and a low-doped region under the drain contact side. The high-doped region can effectively reduce the electric field on the source surface and improve the lateral withstand voltage of the device. The low-doped region is conducive to the downward expansion of the depletion layer and improves the longitudinal withstand voltage of the device. However, this technology has the following disadvantages: the substrate region is divided into two high- and low-doped regions, which is difficult to implement in device technology. Document 1 does not give the specific implementation process of the device, and there is no subsequent experimental report. The document also does not analyze whether the new structure is beneficial to improving the turn-off non-breakdown time.
[0007] Figure 2 The figure shows another structure of the improved device (SPBL SOI LDMOS) proposed in "Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer". Its top part is also a conventional SOI LDMOS. The innovation is the introduction of a step-doped P-type buried layer (SPBL) in its substrate region, which is located below the buried oxide layer. SPBL can effectively enhance the RESURF effect, and can weaken the surface electric field of the source end and modulate the lateral electric field of the drift region without reducing the doping concentration of the drift region, thereby improving the lateral withstand voltage of the device. It can also enable the device to use a low substrate doping concentration, allowing the substrate depletion layer to extend deeper to improve the longitudinal withstand voltage. Disadvantages: SPBL is located in the substrate and multi-step P-type doping is required. Therefore, the device implementation process must be strictly aligned, and multiple boron ion implants are required, making it very difficult to implement. Similarly, there is no subsequent experimental report on this device structure. Although the new structure has a certain improvement in the turn-off non-breakdown time, it is not obvious enough. Summary of the invention
[0008] The present invention provides a structure and a preparation method for improving the transient turn-off non-breakdown time of a SOI LDMOS power device, to achieve the following objectives:
[0009] 1. Effectively improve the device's turn-off non-breakdown time, making the device's switching operating frequency range wider.
[0010] 2. Improve the device turn-off non-breakdown time without changing the uniform doping of the conventional SOI LDMOS device substrate, thereby reducing the process difficulty and cost of the new structure.
[0011] 3. Under the premise of increasing the device's off-state time without breakdown, maintain the device's low on-resistance and alleviate the self-heating effect.
[0012] The specific technical solution is:
[0013] The structure for improving the transient turn-off non-breakdown time of SOI LDMOS power devices comprises top silicon, a drift region, a buried oxide layer and a P-type substrate; an upwardly concave region of the top silicon is provided at a part of the drift region and below the drain end; at a position corresponding to the concave region of the top silicon, a part of the upper surface of the buried oxide layer is convex to form a thickened region of the buried oxide layer.
[0014] A method for preparing a structure for improving the transient turn-off non-breakdown time of a SOI LDMOS power device comprises the following steps:
[0015] S1, photolithography alignment marks to control the position of the buried oxide layer thickening area in the device, and then etching away part of the silicon material on the top silicon;
[0016] S2, growing silicon dioxide on the surface of the etched silicon material;
[0017] S3, flat silicon dioxide is prepared for subsequent bonding;
[0018] S4, growing and flattening silicon dioxide on a P-type substrate;
[0019] S5. Bond the two parts in S3 and S4 together through silicon dioxide to obtain the main structure of the SOI device with a buried oxide layer thickened region.
[0020] The technical effects of the present invention are as follows:
[0021] (1) To improve the transient withstand voltage and shutdown time of the device at a low cost.
[0022] The introduction of the buried oxide layer thickening area optimizes the device's longitudinal electric field and can effectively increase the device's turn-off time without breakdown. The length and thickness of the buried oxide layer thickening area can be flexibly designed according to the performance indicators to be achieved by the device, and the device performance is not greatly affected by the alignment accuracy. The process of thickening the buried oxide layer is mature and low-cost.
[0023] (2) Under the same transient withstand voltage, the present invention can greatly alleviate the self-heating effect of the SOI LDMOS device and maintain a low specific on-resistance.
[0024] The thickened area of the buried oxide layer reduces the drift region area, and the device is easy to be depleted, so a higher drift region doping concentration can be used to reduce the specific on-resistance; compared with a conventional buried oxide layer with uniform thickness, under the same transient withstand voltage, the source end of the present invention can use a thinner buried oxide layer, which greatly alleviates the self-heating effect of the SOI LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 The structure is one of the improved devices of the prior art;
[0026] Figure 2 It is a SPBL SOI LDMOS device structure of the prior art;
[0027] Figure 3 The structure of the novel device for improving the transient shutdown non-breakdown time of the present invention;
[0028] Figure 4 The present invention provides a process flow for implementing the buried oxide layer thickening region. DETAILED DESCRIPTION
[0029] The specific technical solution of the present invention is explained in conjunction with embodiments.
[0030] The present invention improves the uniform thickness of the buried oxide layer of the conventional SOI LDMOS device, such as Figure 3 As shown. A buried oxide layer thickening area is introduced in part of the drift region and the lower part of the drain. Its function is to optimize the longitudinal electric field distribution at the drain end. When the device is turned off instantaneously, there are electric fields in the top silicon, buried oxide layer and substrate in the vertical direction, and the electric field of the buried oxide layer is the highest. As the off-state time increases, the electric field in the substrate continues to decrease, while the electric fields of the top silicon and buried oxide layer continue to increase until the surface or bottom of the top silicon at the drain end is broken down. Therefore, under the premise that the total thickness of the top silicon and buried oxide layer remains unchanged, increasing the thickness of the buried oxide layer and reducing the thickness of the top silicon is beneficial to improving the transient withstand voltage and shutdown non-breakdown time of the device. The length and thickness of the buried oxide layer thickening area can be flexibly designed according to the performance indicators to be achieved by the device, and the device performance is not greatly affected by the alignment accuracy. The process of thickening the buried oxide layer is mature and low-cost.
[0031] The introduction of the thickened buried oxide layer has other benefits, specifically: the drift region area is reduced, the device is easy to be depleted, so a higher drift region doping concentration can be used to reduce the specific on-resistance; compared with a conventional buried oxide layer of uniform thickness, under the same transient withstand voltage, the turn-off non-breakdown time of the present invention is longer, and a thinner buried oxide layer can be used at the source end, which can greatly alleviate the self-heating effect of the SOI LDMOS device.
[0032] Comparison of simulation performance of the present invention:
[0033] Simulation conditions:
[0034] (1) The device provided in this embodiment has the same main device parameters as the conventional device: the drift region length is 40 μm, the total thickness of the top silicon layer and the buried oxide layer is 7 μm, and the drift region doping concentration is 2×10 15 cm -3 , substrate doping concentration 4×10 14 cm -3 .
[0035] (2) When the transient withstand voltage is 518V, the buried oxide layer thickness of the device provided in this embodiment is 1μm, the thickness of the thickened area is 2μm, the thickness of the top silicon layer near the drain end is 4μm, and the length of the thickened area below the drift region near the drain end is 30μm. The buried oxide layer thickness of conventional devices is 2μm, and the thickness of the top silicon layer is 5μm.
[0036] Performance comparison:
[0037] (3) In the off state, when the drain voltage of both devices is 460V, the shutdown non-breakdown time of the device provided by this embodiment is 1.69ms, and that of the conventional device is 1.24ms. The device provided by this embodiment is 36.29% longer than that of the conventional device. This shows that the device provided by this embodiment can operate at a lower switching frequency and has a wider operating range. In the on state, when the gate voltage of both devices is 15V and the drain voltage is increased to make the device power reach 3mW / μm, the minimum temperature of the device provided by this embodiment is 345K and that of the conventional device is 365K. The minimum temperature of the device provided by this embodiment is 20K lower than that of the conventional device, which significantly alleviates the self-heating effect of the SOI LDMOS device.
[0038] The process flow of implementing the thickening area of the buried oxide layer in this embodiment is as follows: Figure 4 As shown. First, Figure 4 As shown in (a), the photolithography alignment marks are used to control the position of the buried oxide layer thickening area in the device, and then part of the silicon material is etched away on the N-type top silicon. Figure 4 As shown in (b), silicon dioxide is grown on the surface of the etched silicon material. Figure 4 As shown in (c), the flat silicon dioxide is ready for subsequent bonding. Figure 4 As shown in (d), silicon dioxide is grown and flattened on a P-type substrate. Figure 4 As shown in (e), Figure 4 The two parts in (c) and (d) are bonded together by silicon dioxide to obtain the main structure of the SOI device with a buried oxide layer thickened region. The other structural implementation processes of the device provided in this embodiment are consistent with those of conventional SOI, so they will not be repeated.
[0039] The present invention can be used not only for SOI LDMOS but also for other lateral devices of SOI, such as SOI IGBT, SOIDIODE and the like.
[0040] The buried oxide layer thickening area is not limited to a rectangle, but may also be other geometric shapes, such as a triangle, etc. Its material is not limited to SiO2, but may also be other insulating materials.
Claims
1. A structure for improving the transient turn-off non-breakdown time of a SOI LDMOS power device, comprising a top silicon layer, a drift region, a buried oxide layer and a P-type substrate; characterized in that: In part of the drift region and below the drain end, there is an upwardly concave region of the top silicon; at a position corresponding to the concave region of the top silicon, part of the upper surface of the buried oxide layer is convex to form a thickened region of the buried oxide layer.
2. The method for preparing the structure for improving the transient turn-off non-breakdown time of SOI LDMOS power device according to claim 1, characterized in that: The following steps are involved: S1, photolithography alignment marks to control the position of the buried oxide layer thickening area in the device, and then etching away part of the silicon material on the top silicon; S2, growing silicon dioxide on the surface of the etched silicon material; S3, flat silicon dioxide is prepared for subsequent bonding; S4, growing and flattening silicon dioxide on a P-type substrate; S5. Bond the two parts in S3 and S4 together through silicon dioxide to obtain the main structure of the SOI device with a buried oxide layer thickened region.