Epitaxial silicon wafer, preparation method thereof and solar cell

Abstract

The invention provides an epitaxial silicon wafer and a preparation method thereof, and a solar cell, and the epitaxial silicon wafer is obtained on one side of a silicon substrate through epitaxy after gettering is carried out on the silicon substrate through a gettering layer. Wherein the doping concentration of the epitaxial silicon wafer is smaller than that of the silicon substrate. And the metal impurity content of the silicon wafer is less than 1E + 8 atom / cm < 2 >. The content of metal impurities in the silicon wafer is low, and the silicon wafer is suitable for serving as a substrate of a solar cell.

Description

Technical Field

[0001] The present application relates to the technical field of silicon wafer preparation, and in particular to an epitaxial silicon wafer and a preparation method thereof, and a solar cell. Background Art

[0002] The current epitaxial silicon wafers have high metal impurity content (generally 1E12 cm -3 ), metal impurities can easily form deep energy level defects and recombination centers in silicon wafers, greatly affecting the minority carrier lifetime and carrier diffusion length of silicon wafers. When silicon wafers are used in the preparation of solar cells, metal impurities in silicon wafers will have a certain impact on the efficiency of solar cells.

[0003] Therefore, how to reduce the metal impurity content in epitaxial silicon wafers has become a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the problem that the metal impurity content in epitaxial silicon wafers cannot be further reduced in the prior art, the present application provides an epitaxial silicon wafer and a preparation method thereof, and a solar cell. By providing a gettering layer on a silicon substrate to getter the silicon substrate, and growing an epitaxial silicon wafer on the gettered silicon substrate, a high-purity epitaxial silicon wafer with a low metal impurity content can be obtained.

[0005] One aspect of the present application provides an epitaxial silicon wafer, wherein the metal impurity content of the epitaxial silicon wafer is less than 1E+8atom / cm 3 .

[0006] As a possible implementation scheme, the present application provides an epitaxial silicon wafer, wherein the thickness of the epitaxial silicon wafer is 70-150 μm, and the flatness of the epitaxial silicon wafer is less than 10 μm.

[0007] As a possible implementation scheme, the present application provides an epitaxial silicon wafer, wherein the oxygen content of the epitaxial silicon wafer is less than 7E+15 atom / cm 3 , the carbon content of epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

[0008] Another aspect of the present application provides a method for preparing an epitaxial silicon wafer, comprising: growing a gettering layer on the epitaxial side of a silicon substrate, removing the gettering layer, and then growing a doped epitaxial layer on the epitaxial side of the silicon substrate, and separating the doped epitaxial layer to obtain an epitaxial silicon wafer.

[0009] According to an embodiment of the present application, after removing the gettering layer and before growing the doped epitaxial layer, the epitaxial silicon wafer preparation method further includes: growing a transition layer on the epitaxial side of the silicon substrate.

[0010] According to an embodiment of the present application, the transition layer grown on the epitaxial side of the silicon substrate includes at least a first sub-transition layer and a second sub-transition layer, wherein the thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

[0011] According to an embodiment of the present application, after the gettering layer is removed, an intrinsic epitaxial layer is grown on the surface of the silicon substrate after the gettering layer is removed, wherein the growth temperature of the intrinsic epitaxial layer is 1120-1150° C. Hydrogen is used to transport gaseous trichlorosilane to grow the intrinsic epitaxial layer. The hydrogen flow rate is 120-140 L / min, and the trichlorosilane flow rate is 15-20 slm.

[0012] Another aspect of the present application provides a solar cell, comprising: a silicon substrate, where the silicon substrate is an epitaxial silicon wafer according to any embodiment of the present application.

[0013] The core concept of the present application is to provide a high-purity silicon substrate on which an epitaxial layer is grown. Since epitaxial growth does not affect the metal impurity content in the epitaxial layer, the higher the purity of the silicon substrate, the higher the purity of the epitaxial silicon wafer grown on the silicon substrate, and the better the quality of the epitaxial silicon wafer.

[0014] The present application achieves the removal of metal impurities in the silicon substrate by growing a gettering layer on the silicon substrate to absorb and solidify the metal impurities in the silicon substrate, and then removing the gettering layer. The doped epitaxial layer is grown on the side of the silicon substrate from which the gettering layer has been removed. Since the metal impurities migrate into the gettering layer during gettering, after the gettering layer is removed, the concentration of metal impurities in the area near the side of the silicon substrate where the gettering layer is grown is lower than that in other areas of the silicon substrate. When epitaxial growth is performed on this side, the silicon substrate close to the epitaxial part is purer. Even if the metal impurities far away from the epitaxial part migrate, they are not easy to migrate to the doped epitaxial layer due to the long path, so that the metal impurity content in the epitaxial silicon wafer is lower, thereby obtaining a high-quality epitaxial silicon wafer (metal impurity content is less than 1E+8 atom / cm 3 ), overcame the technical problem of high metal impurity content in epitaxial silicon wafers, and achieved the technical effect of preparing high-quality epitaxial silicon wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above contents and other purposes, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0016] Figure 1 A flow chart schematically shows a method for preparing an epitaxial silicon wafer according to an embodiment of the present application;

[0017] Figure 2 A flow chart of adding a growth transition layer according to a method of an embodiment of the present application is schematically shown;

[0018] Figure 3 The silicon wafer epitaxial structure according to an embodiment of the present application is schematically shown.

[0019] [Description of Reference Numerals]

[0020] 1-silicon substrate; 2-first sub-transition layer; 3-second sub-transition layer; 4-doped epitaxial layer. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form a new solution without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to a person of ordinary skill in the art. In addition, although demonstrations of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0023] Unless there are technical obstacles or contradictions, the above-mentioned various implementation modes of the present application can be freely combined to form other embodiments, and these other embodiments are all within the protection scope of the present application.

[0024] Although the present application is described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the preferred embodiments of the present application and should not be construed as limiting the present application. The size ratios in the accompanying drawings are merely illustrative and should not be construed as limiting the present application.

[0025] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

[0026] The present application provides an epitaxial silicon wafer having a metal impurity content of less than 1E+8 atom / cm 3 Compared with conventional epitaxial silicon wafers, the metal impurity content is lower and the minority carrier lifetime of the silicon wafer is improved to a certain extent. The photoelectric conversion efficiency of solar cells prepared using this silicon wafer is significantly improved.

[0027] It should be noted that the metal impurities in the present application refer to metal impurities other than doping elements in the epitaxial silicon wafer that may cause deep energy level defects.

[0028] The metal impurities in the silicon wafer can be detected by SIMS, ICP-MS, GDMS and the like, preferably by ICP-MS. The metal impurities in the silicon wafer of the present application include, for example, Fe, Cu, Ni, Co, Au and the like.

[0029] In a specific embodiment, the thickness of the epitaxial silicon wafer is 70-150 μm, and the flatness of the epitaxial silicon wafer is less than 10 μm.

[0030] Optionally, when the thickness of the epitaxial silicon wafer is 100 μm, the flatness of the epitaxial silicon wafer is less than 10 μm, the surface defects of the epitaxial silicon wafer are few, and the product quality is high.

[0031] It should be noted that the surface flatness of silicon wafers refers to the degree of deviation between the surface of the silicon wafer and the sample plane, which is usually expressed as RMS (Root Mean Square). The RMS value is obtained by taking the square root of the sum of the squares of a series of measured values ​​divided by the total number of data. The calculation formula is: RMS = sqrt((Δh 1 2 + Δh 2 2 + ··· + Δh n 2 ) / n), where Δh represents the deviation of the measured value from the sample plane, and n represents the number of measurement points. The lower the value of silicon wafer flatness, the flatter the surface of the silicon wafer.

[0032] The thickness and flatness of epitaxial silicon wafers are measured using AFM (Atomic Force Microscope), SEM (Scanning Electron Microscope), stepping interferometer, etc.

[0033] In one embodiment, the oxygen content of the epitaxial silicon wafer is less than 7E+15 atom / cm 3 , the carbon content of epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

[0034] The use of this epitaxial silicon wafer has a lower oxygen content than conventional epitaxial silicon wafers, fewer defects in the silicon wafer, and higher quality silicon wafers. The carbon content of the present application is less than 8E+15 atom / cm 3The silicon wafers have less lattice defects and higher quality due to the low substitutional carbon content.

[0035] The oxygen content and carbon content in the silicon wafer may be detected by any method known to those skilled in the art, and those skilled in the art may select a method based on their needs. For example, the oxygen content and carbon content in the silicon wafer may be detected by secondary ion mass spectrometry (SIMS).

[0036] In a specific embodiment, the epitaxial silicon wafer is rectangular, one side of the rectangle is 156 mm to 300 mm, and the other side of the rectangle is 83 mm to 300 mm.

[0037] It is understandable that the rectangle here can be a rectangle with unequal length and width, or a square with equal length and width. It is also understandable that the rectangle here is not necessarily a rectangle with strict geometric definition, and some chamfering or rounding is allowed as long as it is roughly rectangular.

[0038] In a specific embodiment, it also includes a chamfer connecting two adjacent sides of the silicon wafer, the projection length of the chamfer is 1 mm to 10 mm, and the chamfer can be an arc edge or a straight edge.

[0039] The epitaxial silicon wafer preparation method of the present application is further described below in conjunction with the accompanying drawings:

[0040] The present application provides a method for preparing an epitaxial silicon wafer, which is used to prepare the epitaxial silicon wafer of the present application. By growing a gettering layer on an original silicon substrate containing metal impurities, the metal impurities in the silicon substrate can be absorbed and solidified, and then the gettering layer is removed, thereby achieving the removal of metal impurities in the silicon substrate, obtaining a high-purity silicon substrate, growing an epitaxial layer on the substrate, and finally peeling off the epitaxial silicon wafer. The epitaxial silicon wafer has a low metal impurity content and a high quality silicon wafer, and the metal impurity content is less than 1E+8 atom / cm 3 The solar cell prepared with the epitaxial silicon wafer has high photoelectric conversion efficiency.

[0041] Figure 1 The flowchart of the method for preparing an epitaxial silicon wafer according to an embodiment of the present application is schematically shown.

[0042] like Figure 1 As shown, the epitaxial silicon wafer preparation method of the present application includes operation S110 to operation S130.

[0043] In operation S110 , a gettering layer is grown on the epitaxial side of the silicon substrate.

[0044] In operation S120 , the gettering layer is removed, and then a doped epitaxial layer is grown on the epitaxial side of the silicon substrate.

[0045] In operation S130 , the doped epitaxial layer is separated to obtain an epitaxial silicon wafer.

[0046] In operation S110, the silicon substrate is the basis for epitaxial growth. This application has no special requirements for the silicon substrate. For example, a silicon substrate with a diameter of 200 mm, a thickness of 625 μm, a resistivity of 0.1 Ω·cm, and a surface crystal orientation of 100 μm can be selected. <100> A silicon wafer is used as a silicon substrate, and the silicon substrate can be, for example, a silicon wafer obtained by a single crystal pulling method, a direct silicon wafer, etc.

[0047] It should be noted that the epitaxial side of the silicon substrate refers to the surface where the epitaxial layer is to be grown, usually the front side of the silicon wafer.

[0048] The function of the gettering layer is to absorb, enrich and fix the metal impurities (such as Fe, Cu, Ni, Co, Au, etc.) contained in the silicon substrate itself. This reduces the content of metal impurities in the silicon substrate; and when the gettering layer is removed, the purity of the entire silicon substrate is high, especially the purity near the gettering layer, which improves the quality of the silicon wafer grown on the silicon substrate.

[0049] In a specific embodiment, the material of the gettering layer may be, for example, a silicon-germanium alloy (SiGe) or doped silicate glass. Furthermore, the doped silicate glass may be a borosilicate glass layer, a phosphosilicate glass layer or a borophosphosilicate glass layer.

[0050] It is understandable that the present application has no special requirements for the thickness of the gettering layer, which is generally about 2 μm. When the gettering layer is a borosilicate glass layer, it can be prepared in the following manner:

[0051] At 1100°C, silicon tetrachloride (SiCl 4 ) and trimethylboron (TMB) as precursor gases, a borosilicate glass layer (BSG) with a thickness of about 2μm is grown on the epitaxial side of the silicon substrate (usually the front side of the silicon wafer).

[0052] When the gettering layer is a phosphosilicate glass layer, it can be prepared and formed in the following manner:

[0053] At 1110°C, silicon tetrachloride and phosphine (PH 3 ) as a precursor gas to grow a phosphorus silicon glass (PSG) layer with a thickness of about 2μm on the epitaxial side of the silicon substrate.

[0054] When the gettering layer is a borophosphosilicate glass layer, it can be prepared and formed in the following manner:

[0055] Boron diffusion is performed first, followed by phosphorus diffusion, to obtain a borophosphosilicate glass layer.

[0056] For example: At a temperature of 1120°C, using silicon tetrachloride, trimethylboron and phosphine as precursor gases, a layer of borophosphosilicate glass (BPSG) with a thickness of about 2μm is grown on the epitaxial side of a silicon substrate.

[0057] The use of BPSG can provide better dielectric properties due to its combination of diffusion depth into epitaxial silicon wafers and its ability to dissolve metal impurities, and is more conducive to the removal of metal impurities in the silicon substrate, thereby achieving a better impurity gettering effect.

[0058] It is understandable that, under the same temperature conditions, only borane or phosphine diffusion may be performed to obtain a borosilicate glass layer or a phosphosilicate glass layer as a doping layer to save raw materials or simplify the process.

[0059] The present application can effectively reduce the metal impurity content in the silicon wafer by growing a gettering layer to getter the silicon substrate. For those skilled in the art, based on the scheme of the present application, the properties of the material can be adjusted according to specific needs, and different types of gettering layers can be used to getter the silicon substrate, and the present application does not limit this.

[0060] In operation S120, the purpose of removing the gettering layer is to remove the metal impurities accumulated in the gettering layer together with the gettering layer, thereby making the epitaxial side of the silicon substrate cleaner. The present application may use dry etching technology to remove the gettering layer, such as plasma etching or gas etching.

[0061] Then, after removing the gettering layer, a doped epitaxial layer is grown on the epitaxial side of the silicon substrate. The doped epitaxial layer can be grown on the surface of the silicon substrate after removing the gettering layer. The material of the doped epitaxial layer is also silicon (Si). In a specific embodiment, the thickness of the doped epitaxial layer is 150 μm and the doping concentration is 1E16 cm -3 The doping element may be P-type boron, gallium, etc., or N-type phosphorus, arsenic, etc.

[0062] In operation S130, the doped epitaxial layer is separated, and laser lift-off or other suitable separation techniques are used to separate the doped epitaxial layer from the silicon substrate, and the separated doped epitaxial layer is an epitaxial silicon wafer. The epitaxial silicon wafer has a lower doping concentration and better electrical properties, and can be used as a substrate for other semiconductor devices, solar cells, etc.

[0063] The method for preparing an epitaxial silicon wafer provided by the present application grows a gettering layer on the side of the silicon substrate where epitaxial growth is performed, and utilizes the diffusion coefficient of metal impurity elements in the silicon substrate to be generally greater than the self-diffusion coefficient of silicon. Especially under high temperature conditions, the gettering layer on the silicon substrate is used to solidify the metal impurities in the silicon substrate, and then the gettering layer is removed, thereby achieving the purpose of removing the metal impurities in the silicon substrate. The epitaxial layer is grown on the silicon substrate after gettering, and the obtained epitaxial silicon wafer has less metal impurity content and high quality.

[0064] In order to further improve the doping effect on the silicon substrate, the present application also provides a feasible technical solution. On the basis of the above-mentioned preparation method, after removing the doping layer, before growing the doped epitaxial layer on the epitaxial side of the silicon substrate, an intrinsic epitaxial layer is grown on the surface of the silicon substrate after removing the doping layer, and the intrinsic epitaxial layer is removed.

[0065] Specifically, after the gettering layer is removed by dry etching technology, a layer of intrinsic epitaxial layer is grown on the epitaxial side of the silicon substrate by chemical vapor deposition technology. The intrinsic epitaxial layer is composed of undoped silicon and has a thickness of about 1 μm.

[0066] The present application grows an intrinsic layer after doping, and the intrinsic epitaxial layer can wrap the epitaxial growth chamber and the entire silicon substrate, solidify metal impurities, and prevent impurities and dopants from overflowing. After the doping layer is removed, the grown intrinsic epitaxial layer can further capture metal impurities that may exist inside the silicon wafer, achieve further doping of the silicon substrate, and further improve the purity of the silicon substrate, thereby improving the purity of the epitaxial wafer grown on the silicon substrate after doping.

[0067] Optionally, the growth temperature of the intrinsic epitaxial layer is 1120-1150° C., and the intrinsic epitaxial layer can be grown by using hydrogen to transport gaseous trichlorosilane, wherein the hydrogen flow rate is 120-140 L / min, and the trichlorosilane flow rate is 15-20 slm.

[0068] Then, dry etching techniques are used to remove the intrinsic epitaxial layer, such as plasma etching or etching with hydrogen chloride gas. After etching, the surface of the silicon substrate should be clean and free of impurities. After the initial silicon wafer is processed, most of the metal impurities in it have been removed, and when epitaxial growth is performed on it, the epitaxial wafer grown is of higher purity.

[0069] Finally, a doped epitaxial layer is grown and peeled off to obtain an epitaxial silicon wafer.

[0070] In the preparation method of the epitaxial silicon wafer, an intrinsic epitaxial layer is added as a secondary impurity gettering layer. Since the intrinsic epitaxial layer can quickly encapsulate the entire reaction chamber, the surface and edge of the silicon wafer, thereby further solidifying the impurities and preventing the overflow of impurities and dopants, the purity of the silicon wafer can be further improved after the first impurity gettering treatment. This method helps to improve the reliability and consistency of the final product. Through two impurity gettering treatments, the metal impurity content in the silicon wafer can be significantly reduced, thereby improving the performance of the final device.

[0071] Figure 2 The flowchart of adding a growth transition layer according to the method of an embodiment of the present application is schematically shown.

[0072] The difference from the above technical solution is that according to this technical solution, if Figure 2 As shown, after removing the gettering layer and before growing the doped epitaxial layer, the epitaxial silicon wafer preparation method further includes, for example, operation S210.

[0073] In operation S210 , a transition layer is grown on the epitaxial side of a silicon substrate.

[0074] It should be noted that a transition layer is formed on the silicon substrate. Since the lattice parameters of the doped epitaxial layer are not exactly the same as those of the silicon substrate, the transition layer is mainly used to adjust the arrangement of the silicon substrate lattice and reduce the stress distribution in the silicon substrate. At the same time, it can further reduce the metal impurity content in the silicon substrate, thereby improving the flatness of the epitaxial doped silicon wafer grown on the silicon substrate with adjusted lattice arrangement.

[0075] In operation S210, after removing the gettering layer, for example, a transition layer is first grown on the surface of the silicon substrate after removing the gettering layer. The transition layer is made of silicon (Si) material, has a thickness range of 0.5-2 μm, and can be lightly doped to achieve a doping concentration transition, for example, a doping concentration of 1E17 cm -3 of phosphorus (P).

[0076] In an optional implementation, after removing the gettering layer and before growing the doped epitaxial layer, part of the thickness of the transition layer is removed along the thickness direction of the transition layer. For example, dry etching technology is used to remove part of the thickness of the transition layer, for example, about 0.5 μm is removed, leaving a 0.5 μm transition layer. Then, a doped epitaxial layer is grown on the thinned transition layer. Since defects in the silicon substrate migrate to the transition layer, the purity of the silicon substrate is higher; the transition layer is then partially removed to reduce the defects of the transition layer and prevent them from entering the epitaxial doped layer. This step helps to adjust the flatness of the final silicon wafer.

[0077] In an optional implementation, the present application discloses that the doping concentration of the epitaxial silicon wafer is lower than the doping concentration of the silicon substrate, and the doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer.

[0078] The doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer, which can form a gradient change in doping concentration in the direction from the silicon substrate to the epitaxial silicon wafer, and can adjust the arrangement between atoms in a gradient manner, thereby forming a stress gradient change along the direction from the silicon substrate to the epitaxial layer, thereby buffering these stress mismatches. Through the design of the transition layer, the gradient change in doping concentration formed between the epitaxial silicon wafer and the silicon substrate alleviates the stress distribution of the silicon substrate, which helps to further improve the flatness of the epitaxial silicon wafer surface, thereby forming a higher quality epitaxial silicon wafer.

[0079] Figure 3The silicon wafer epitaxial structure according to an embodiment of the present disclosure is schematically shown.

[0080] Combined with Figure 3 The steps of growing the transition layer in the present application include, for example: growing a first sub-transition layer 2 on the epitaxial side of the silicon substrate 1; at least partially removing the first sub-transition layer 2; growing a second sub-transition layer 3 on the surface after at least partially removing the first sub-transition layer 2; the doping concentration of the first sub-transition layer 2 is between the doping concentration of the silicon substrate 1 and the doping concentration of the second sub-transition layer 3.

[0081] In some optional implementations, the transition layer may include at least one sub-transition layer. For example, before growing the second sub-transition layer, a first sub-transition layer may be grown on the epitaxial side of the silicon substrate and partially or completely etched away.

[0082] In addition, the present application also provides a solution for adding multiple transition layers and partially etching each layer of the multiple transition layers. After the transition layer is formed, defects in the silicon substrate migrate to the transition layer, and partially removing the transition layer can reduce the defects in the transition layer. Therefore, by adding multiple transition layers and performing multiple gradient etching on the multiple transition layers, the defects in the transition layer can be reduced and prevented from entering the epitaxial doping layer, thereby improving the flatness of the epitaxial wafer and obtaining a high-quality epitaxial wafer.

[0083] Optionally, after removing the gettering layer, a first sub-transition layer is grown on the epitaxial side of the silicon substrate. Furthermore, the first sub-transition layer can be made of silicon material with a thickness ranging from 1 to 3 μm, and can be lightly doped to reduce the resistivity, for example, the doping concentration is 1E18 cm -3 The doping concentration of the first transition sub-layer is between the doping concentration of the silicon substrate and the doping concentration of the second transition sub-layer.

[0084] Since the doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer, a gradient change in doping concentration can be formed in the direction from the silicon substrate to the epitaxial silicon wafer, and the arrangement between atoms can be adjusted in a gradient manner, so that the stress gradient changes along the direction from the silicon substrate to the epitaxial layer, and the mismatch of these stresses is buffered. Through the design of the gradient change of doping concentration of multiple transition layers, the purity of the silicon substrate is higher, and the gradient change of doping concentration formed between the epitaxial silicon wafer and the silicon substrate further relieves the stress in the silicon substrate, which helps to further improve the flatness of the surface of the epitaxial silicon wafer, thereby forming a higher quality epitaxial silicon wafer.

[0085] The thickness of the first sub-transition layer is, for example, 1 μm. Dry etching technology is used to remove part of the thickness of the first sub-transition layer, for example, about 0.5 μm is removed, leaving a 0.5 μm transition layer. The 1 μm first sub-transition layer can also be completely removed. In this step, since defects in the silicon substrate migrate to the transition layer after the transition layer is formed, partial removal of the transition layer can reduce defects in the transition layer, improve the purity of the silicon substrate, and help adjust the flatness of the silicon wafer, and ensure that the second sub-transition layer grown subsequently has a good contact interface.

[0086] After at least part of the first transition layer is removed, a second sub-transition layer is grown on the silicon substrate after the first sub-transition layer is removed using CVD technology.

[0087] Optionally, the second sub-transition layer may be made of silicon material with a thickness of about 1 μm, and may be slightly doped to reduce the resistivity, for example, the doping concentration is 1E17 cm -3 of phosphorus.

[0088] A dry etching technique is used to remove part of the thickness of the second sub-transition layer, for example, about 0.5 μm is removed, leaving a 0.5 μm transition layer. This step helps to further adjust the flatness of the final silicon wafer.

[0089] Then, a doped epitaxial layer is grown on the partially etched second sub-transition layer to obtain Figure 3 The epitaxial structure shown is finally peeled off to obtain an epitaxial silicon wafer.

[0090] This preparation method can further optimize the doping concentration and flatness before growing the second sub-transition layer by adding a first sub-transition layer, which helps to improve the reliability and consistency of the final product. Through two impurity gettering processes and two transition layer growth and etching, the metal impurity content in the silicon wafer can be significantly reduced, thereby improving the quality of the epitaxial silicon wafer grown on the silicon substrate.

[0091] For those skilled in the art, it is also possible to prepare high-quality epitaxial silicon wafers by multiple doping steps and multiple transition layers in combination with different requirements, and this application does not limit this.

[0092] It is understandable that the silicon wafer preparation method of the present application can also directly grow the second sub-transition layer on the epitaxial side of the silicon substrate under different demand scenarios to simplify the production process and improve production efficiency.

[0093] Optionally, in order to further improve the flatness of the epitaxial silicon wafer, more sub-transition layers may be grown to further improve the flatness.

[0094] Optionally, the thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

[0095] According to the technical solution of the present application, the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, and the growth temperature of the doped epitaxial layer is 1080-1100°C.

[0096] In some optional technical solutions, the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer. After the second sub-transition layer is grown at a temperature of 1120°C, a dry etching technique is used to remove part of the thickness of the second sub-transition layer to adjust the flatness of the final silicon wafer, for example, removing about 0.5 μm and leaving a 0.5 μm transition layer. A doped epitaxial layer is grown on the surface of the silicon substrate from which the second sub-transition layer has been removed, and the growth temperature of the doped epitaxial layer is 1080-1100°C. Furthermore, in order to ensure that the growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, the growth temperature can be selected to be 1090°C.

[0097] Finally, the doped epitaxial layer is peeled off to obtain an epitaxial silicon wafer.

[0098] It should be noted that, in this embodiment, by controlling the growth temperature of the doped epitaxial layer to be lower than the growth temperature of the second sub-transition layer, the back diffusion rate of impurities in the phosphorus-doped silicon wafer can be reduced, and the performance and reliability of the doped epitaxial layer can be further optimized. Through two impurity gettering processes and two transition layer growth and etching, the metal impurity content in the silicon substrate can be significantly reduced, thereby improving the performance of the final device.

[0099] In order to reduce the impurity content in the epitaxial silicon wafer, hydrogen gas may be used to purge the silicon substrate and / or the reaction chamber of the epitaxial furnace before or after at least one step of the epitaxial silicon wafer preparation method.

[0100] Before starting any epitaxial growth, use hydrogen gas (H 2 ) Purge the silicon substrate to remove pollutants and oxide layers on the surface. The hydrogen purge lasts for about 1 to 2 minutes. After the purge is completed, the surface of the silicon substrate should be clean and free of impurities.

[0101] For those skilled in the art, before growing the intrinsic epitaxial layer, the first sub-transition layer, the second sub-transition layer, and the doped epitaxial layer, the silicon substrate can be purged with hydrogen to remove possible surface contamination. The hydrogen purging lasts for about 8 to 10 minutes. After the purging is completed, the surface of the silicon substrate should be clean and free of impurities.

[0102] It is understandable that by using hydrogen purge, the cleanliness of the silicon wafer surface can be further improved, the impact of pollutants can be reduced, and the reliability and consistency of the final product can be improved. Through two impurity treatments and two transition layer growth and etching, plus multiple hydrogen purges, the metal impurity content in the epitaxial silicon wafer can be significantly reduced, thereby improving the performance of the final device.

[0103] Optionally, the epitaxial furnace is a normal pressure flat-plate epitaxial furnace. The normal pressure flat-plate epitaxial furnace is simple to operate, relatively low in cost, and suitable for large-scale production.

[0104] Optionally, the silicon substrate of the present application is an N-type single crystal silicon wafer or a P-type single crystal silicon wafer. For those skilled in the art, a silicon substrate, a transition layer and an epitaxial silicon wafer with the same doping type can be selected to ensure the electrical characteristics and performance consistency of the final product.

[0105] The epitaxial silicon wafer growth method of the present invention is used to perform a gettering treatment on the silicon substrate, so that the purity of the silicon substrate is high and the metal impurity content is less than 1E+8 atom / cm 3 Compared with the metal impurity content of conventional epitaxial silicon wafers at 1E+10 atom / cm 3 , its metal impurity content is significantly reduced, the purity of the silicon wafer is high, and it is more conducive to the preparation of high-quality epitaxial silicon wafers.

[0106] In an optional technical solution of the present application, a transition layer is grown on a silicon substrate after the gettering layer is removed, and the lattice arrangement of the silicon substrate can be adjusted to obtain a silicon substrate with good flatness, which can reduce the metal impurity content in the epitaxial silicon wafer while reducing the flatness of the surface of the epitaxial silicon wafer. Compared with the conventional silicon wafer flatness of more than 10 μm, the method of the present application can make the flatness of the silicon wafer surface less than 10 μm. It can be seen that the epitaxial silicon wafer grown by the method of the present application can reduce the metal impurity content and reduce the flatness of the surface of the epitaxial silicon wafer.

[0107] It should be noted that the doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer, and a gradient change of doping concentration can be formed in the direction from the silicon substrate to the epitaxial silicon wafer, which can adjust the arrangement of atoms in a gradient manner, thereby forming a stress gradient change along the direction from the silicon substrate to the epitaxial layer, thereby buffering the mismatch of these stresses. Through the design of the transition layer, the gradient change of doping concentration formed between the epitaxial silicon wafer and the silicon substrate alleviates the stress distribution of the silicon substrate, further reduces the metal impurity content in the silicon substrate, and thus forms a higher quality epitaxial silicon wafer.

[0108] The present application also provides the following four specific embodiments and comparative example 1 for specifically illustrating the product performance of the epitaxial silicon wafer provided by the embodiments of the present invention:

[0109] Example 1

[0110] The specific steps of preparing an epitaxial silicon wafer using the epitaxial silicon wafer preparation method of the present application are as follows:

[0111] A phosphorus-doped single crystal silicon wafer with a thickness of 150 μm was loaded into the carrier of the epitaxial furnace. The reaction chamber of the epitaxial furnace was purged with hydrogen with a purity of ≥99.9999% to exhaust and replace the gas in the reaction chamber. The temperature was 1150 °C, the flow rate of hydrogen was set to 100 L / min, and the purging time was set to 2 min.

[0112] Then, hydrogen was used as a carrier gas to carry BH 3 gas, diffuses borane at high temperature, and then hydrogen carries PH 3 Gas, through high temperature diffusion of phosphine, together with silicon oxide on the surface of silicon wafer, induces doping to form borophosphosilicate glass to solidify metal impurities. The temperature is 1150 ℃, the flow rate of hydrogen is set to 120 L / min, the flow rate of phosphine is set to 250 sccm, the flow rate of borane is set to 250 sccm, and the growth time is set to 15 min.

[0113] The epitaxial furnace reaction chamber and silicon wafer are subjected to gas etching and polishing at high temperature using hydrogen chloride with a purity of ≥99.9999%, so as to completely remove the borophosphosilicate glass impurities on the surface of the silicon wafer. For example, the temperature is 1150°C, the hydrogen chloride gas flow rate is 8 L / min, and the etching time is 20 min.

[0114] A large flow of hydrogen was used to continuously purge the surface of the silicon wafer to completely remove the byproduct of borophosphosilicate glass produced during hydrogen chloride polishing and the impurities adsorbed on the surface of the silicon wafer and the surface of the base. The hydrogen flow rate was 280 L / min and the time was 10 min.

[0115] The required doped epitaxial layer is grown at a growth temperature of 1100 °C. A relatively low growth temperature can reduce the back diffusion rate of impurities in phosphorus-doped silicon wafers, which is conducive to obtaining better thickness uniformity and resistivity uniformity. Hydrogen is used to transport trichlorosilane and phosphine dopants into the reaction chamber, with a hydrogen flow rate of 350 L / min, a trichlorosilane flow rate of 25 slm, a phosphine flow rate of 120 sccm, and an epitaxial layer growth rate of 6.5 μm / min.

[0116] When the epitaxial silicon wafer grows to a thickness of 150 μm, it begins to cool down. The reaction chamber is purged with hydrogen at a flow rate of 370 L / min. The purging time is set to 15 min to remove the reaction byproducts of the growth process from the reaction chamber. After the temperature of the silicon epitaxial wafer drops to room temperature, it is taken out from the carrier.

[0117] Finally, the silicon substrate is cut implicitly by laser to separate the silicon substrate and the epitaxial silicon wafer.

[0118] Example 2

[0119] The difference from Embodiment 1 is that after the gettering layer is removed and before the doped epitaxial layer is grown, an intrinsic epitaxial layer is grown on the surface of the silicon substrate from which the gettering layer is removed, which specifically includes:

[0120] Undoped trichlorosilane is used to grow an intrinsic epitaxial layer on a silicon substrate, and the entire reaction chamber, silicon wafer surface and edge are quickly encapsulated to solidify impurities to prevent the overflow of impurities and dopants. The growth temperature of the intrinsic epitaxial layer is 1150 ℃, and the encapsulation is quickly completed using a high-temperature rapid intrinsic growth method. Hydrogen is used to transport gaseous trichlorosilane into the reaction chamber, the hydrogen flow rate is controlled at 140 L / min, the trichlorosilane flow rate is set to 20 slm, the intrinsic layer growth rate is controlled at 5.5μm / min, and the growth time is controlled at 60 s.

[0121] The reaction chamber and the silicon wafer surface are continuously etched and purged with a large flow of hydrogen, so that the impurities volatilized from the reaction chamber and the silicon wafer are taken out of the reaction chamber by the large flow of hydrogen, effectively suppressing the influence of the inactive doping effect. The hydrogen flow rate is 280 L / min and the time is 10 min.

[0122] Example 3

[0123] The difference from Embodiment 1 is that after the gettering layer is removed and before the doped epitaxial layer is grown, a transition layer is grown on the surface of the silicon substrate from which the gettering layer is removed, which specifically includes:

[0124] Hydrogen is introduced into the reaction chamber to carry trichlorosilane and phosphine as dopants, and a transition layer is grown on the silicon substrate to prevent surface defects (dislocations, stacking faults, and scratches) of the silicon substrate from extending to the doped epitaxial layer. The hydrogen flow rate is set to 140 L / min, the trichlorosilane flow rate is set to 20 slm, the phosphine flow rate is set to 180 sccm, the growth time is set to 30 s, and the growth temperature is set to 1130 °C.

[0125] Example 4

[0126] The difference from Example 1 is that after the gettering layer is removed, before the doped epitaxial layer is grown on the epitaxial side of the silicon substrate, an intrinsic epitaxial layer is grown, the intrinsic epitaxial layer is removed, and a transition layer is grown in sequence on the surface of the silicon substrate from which the gettering layer is removed, which specifically includes:

[0127] Growing intrinsic epitaxial layer: Undoped trichlorosilane is used to grow an intrinsic epitaxial layer on a silicon substrate, and the entire reaction chamber, the surface and edge of the silicon substrate are quickly encapsulated to solidify impurities to prevent the overflow of impurities and dopants. The growth temperature of the intrinsic epitaxial layer is 1150 °C, and the encapsulation is quickly completed using a high-temperature rapid intrinsic growth method. Hydrogen is used to transport gaseous trichlorosilane into the reaction chamber, the hydrogen flow rate is controlled at 140 L / min, the trichlorosilane flow rate is set to 20 slm, the intrinsic epitaxial layer growth rate is controlled at 5.5 μm / min, and the growth time is controlled at 60 s.

[0128] Removal of intrinsic epitaxial layer: Use a large flow of hydrogen to continuously etch and purge the reaction chamber and silicon wafer surface, so that the impurities volatilized from the reaction chamber and silicon wafer are taken out of the reaction chamber by the large flow of hydrogen, effectively suppressing the influence of the inactive doping effect. The hydrogen flow rate is 280 L / min and the time is 10 min.

[0129] Transition layer growth: Hydrogen is introduced into the reaction chamber to carry trichlorosilane and phosphine as dopants, and a transition layer is grown on the silicon substrate to prevent surface defects (dislocations, stacking faults, and scratches, etc.) of the silicon substrate from extending to the doped epitaxial layer. The hydrogen flow rate is set to 140 L / min, the trichlorosilane flow rate is set to 20 slm, the phosphine flow rate is set to 180 sccm, the growth time is set to 30 s, and the growth temperature is set to 1130 °C.

[0130] Comparative Example 1

[0131] Different from Example 1, no gettering treatment is performed, and an epitaxial layer is directly grown on the silicon substrate. The growth process of the epitaxial layer is the same as that of Example 1, and an epitaxial silicon wafer is obtained.

[0132] By testing the metal impurity content and flatness of 300 pcs epitaxial silicon wafers prepared in Examples 1 to 4 with a thickness of 100 μm, the average values ​​are taken and recorded in the following table:

[0133]

[0134] By comparing the above data, it is found that by using the silicon wafer preparation method of Examples 1-4, growing a doping layer on a silicon substrate, subjecting the silicon substrate to doping treatment, and then epitaxial growth, the finally obtained epitaxial silicon wafer has a significantly lower metal impurity content than the epitaxial silicon wafer obtained in Comparative Example 1 without subjecting the silicon substrate to doping treatment.

[0135] Compared with the epitaxial silicon wafers of Example 1 and Example 2, the metal impurity content of the silicon wafer is greatly reduced after the intrinsic layer is added in Example 2. This shows that further gettering through the intrinsic epitaxial layer can effectively and significantly reduce the metal impurity content.

[0136] The flatness values ​​of the epitaxial silicon wafers of Examples 3 and 4 are significantly reduced compared with those of Examples 1, 2, and Comparative Example 1. This indicates that after the silicon substrate is gettered, the transition layer is grown again, which can effectively improve the flatness of the epitaxial silicon wafer.

[0137] In summary, the silicon substrate of the present application has a low metal impurity content, and the epitaxial silicon wafer prepared on the silicon substrate after doping has a low metal impurity content, which reduces minority carrier recombination and improves the minority carrier lifetime of the epitaxial silicon wafer. The solar cell prepared using the epitaxial silicon wafer has the characteristics of high photoelectric conversion efficiency, good electrical properties, etc., and is suitable for manufacturing various high-performance solar panels.

[0138] The unfinished details in the product example section are similar to those in the method example section. Please refer to the method example section and will not be repeated here.

[0139] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present application. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0140] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present application. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present application. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.

[0141] In the above detailed description, various features are grouped together in a single embodiment to simplify the present application. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than those clearly stated in each claim. On the contrary, as reflected in the attached claims, the present application is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim acting alone as a separate preferred embodiment of the present application.

[0142] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0143] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An epitaxial silicon wafer, characterized in that: The metal impurity content of the epitaxial silicon wafer is less than 1E+8 atom / cm 3 .

2. The epitaxial silicon wafer according to claim 1, characterized in that: The thickness of the epitaxial silicon wafer is 70-150 μm, and the flatness of the epitaxial silicon wafer is less than 10 μm.

3. The epitaxial silicon wafer according to claim 1, characterized in that: The oxygen content of the epitaxial silicon wafer is less than 7E+15atom / cm 3 The carbon content of the epitaxial silicon wafer is less than 8E+15 atom / cm 3 .

4. The epitaxial silicon wafer according to any one of claims 1 to 3, characterized in that: The epitaxial silicon wafer is rectangular, and has a first side and a second side, wherein the first side and the second side are adjacent sides; The length of the first side is 156 mm to 300 mm, and the length of the second side is 83 mm to 300 mm.

5. The epitaxial silicon wafer according to claim 4, characterized in that: The epitaxial silicon wafer is provided with a chamfer connecting the first edge and the second edge, and the projection length of the chamfer is 1 mm to 10 mm.

6. A method for preparing an epitaxial silicon wafer, characterized in that: include: growing a gettering layer on the epitaxial side of the silicon substrate; removing the gettering layer, and then growing a doped epitaxial layer on the epitaxial side of the silicon substrate; The doped epitaxial layer is separated to obtain an epitaxial silicon wafer.

7. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: The gettering layer is made of a borosilicate glass layer, a phosphosilicate glass layer or a borophosphosilicate glass layer.

8. The method for preparing an epitaxial silicon wafer according to claim 7, characterized in that: The step of growing the borophosphosilicate glass layer comprises: Boron diffusion is performed first, and then phosphorus diffusion is performed to obtain the borophosphosilicate glass layer.

9. The method for preparing an epitaxial silicon wafer according to any one of claims 6 to 8, characterized in that: After removing the gettering layer and before growing the doped epitaxial layer, the method further comprises: An intrinsic epitaxial layer is grown on the surface of the silicon substrate after the gettering layer is removed.

10. The method for preparing an epitaxial silicon wafer according to claim 9, characterized in that: The growth temperature of the intrinsic epitaxial layer is 1120-1150°C; Using hydrogen to transport gaseous trichlorosilane to grow the intrinsic epitaxial layer; Among them, the hydrogen flow rate is 120~140 L / min, and the trichlorosilane flow rate is 15~20 slm.

11. The method for preparing an epitaxial silicon wafer according to claim 6, characterized in that: After removing the gettering layer and before growing the doped epitaxial layer, the method further includes: A transition layer is grown on the epitaxial side of the silicon substrate.

12. The method for preparing an epitaxial silicon wafer according to claim 11, characterized in that: Also includes: Partially removing the transition layer along the thickness direction of the transition layer; The doping concentration of the epitaxial silicon wafer is less than the doping concentration of the silicon substrate; The doping concentration of the transition layer is between the doping concentration of the silicon substrate and the doping concentration of the epitaxial silicon wafer.

13. The method for preparing an epitaxial silicon wafer according to claim 11, characterized in that: Growing a transition layer on the epitaxial side of the silicon substrate comprises: Growing a first sub-transition layer on the epitaxial side of the silicon substrate; at least partially removing the first transition sub-layer; A second sub-transition layer is grown on the surface after at least a portion of the first sub-transition layer is removed, and the doping concentration of the first sub-transition layer is between the doping concentration of the silicon substrate and the doping concentration of the second sub-transition layer.

14. The method for preparing an epitaxial silicon wafer according to claim 13, characterized in that: The thickness of the first sub-transition layer is 1-3 μm, and the thickness of the second sub-transition layer is 0.5-2 μm.

15. The method for preparing an epitaxial silicon wafer according to claim 13 or 14, characterized in that: The growth temperature of the doped epitaxial layer is lower than the growth temperature of the second sub-transition layer, and the growth temperature of the doped epitaxial layer is 1080-1100°C.

16. A solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate is the epitaxial silicon wafer according to any one of claims 1 to 5.

Images