Light emitting diode with improved reliability and preparation method thereof

Abstract

The embodiment of the invention provides a light emitting diode with improved reliability and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode comprises a light-emitting structure and a first passivation layer, the first passivation layer is located on the surface of the light-emitting structure, the first passivation layer is provided with a through hole, the outer contour of the orthographic projection of the through hole on the light-emitting structure comprises a first side edge, a second side edge, a third side edge and a fourth side edge which are sequentially connected end to end, and the first side edge is opposite to the third side edge. The length of the first side edge and the length of the third side edge are smaller than the length of the second side edge, and the length of the first side edge and the length of the third side edge are smaller than the length of the fourth side edge. According to the embodiment of the invention, the reliability of the LED can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode with improved reliability and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscaping due to its small size, long service life, rich colors, and low energy consumption.

[0003] In the related art, an LED includes a light-emitting structure and a passivation layer, wherein the passivation layer is located on the surface of the light-emitting structure. The passivation layer has a circular through hole. The passivation layer is usually formed on the light-emitting structure by a photolithography process.

[0004] However, as the size of LEDs is gradually miniaturized and the thickness of the passivation layer is relatively large, when the passivation layer is formed by photolithography, the sidewalls of the circular through holes are relatively steep, and the inclination angle of the sidewalls of the circular through holes (i.e., the angle between the sidewalls and the normal of the bearing surface) is relatively small. When a pad electrode layer is subsequently formed on the passivation layer, the pad electrode layer needs to fill the circular through holes and be electrically connected to the light-emitting structure through the circular through holes. The steep sidewalls of the circular through holes make it difficult for the pad electrode layer to evenly fill the circular through holes, so the pad electrode layer is prone to breakage or falling off, thereby affecting the reliability of the LED. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode with improved reliability and a method for manufacturing the same, which can improve the reliability of the LED. The technical solution is as follows:

[0006] On the one hand, a light-emitting diode is provided, comprising a light-emitting structure and a first passivation layer, wherein the first passivation layer is located on the surface of the light-emitting structure, the first passivation layer has a through hole, and the outer contour of the positive projection of the through hole on the light-emitting structure comprises a first side, a second side, a third side and a fourth side connected in sequence end to end, the first side and the third side are opposite, the length of the first side and the length of the third side are smaller than the length of the second side, and the length of the first side and the length of the third side are smaller than the length of the fourth side.

[0007] Optionally, the orthographic projection of the opening of the through hole close to the light-emitting structure on the light-emitting structure is located inside the orthographic projection of the opening of the through hole away from the light-emitting structure on the light-emitting structure; the angle between the side wall of the through hole located on the second side and the fourth side and the normal to the surface of the light-emitting structure is greater than the angle between the side wall of the through hole located on the first side and the normal to the surface of the light-emitting structure; the angle between the side wall of the through hole located on the second side and the fourth side and the normal to the surface of the light-emitting structure is greater than the angle between the side wall of the through hole located on the third side and the normal to the surface of the light-emitting structure.

[0008] Optionally, a maximum angle between a side wall of the through hole and a normal line of a surface of the light emitting structure is 65° to 70°.

[0009] Optionally, the outer contour of the orthographic projection of the through hole on the light-emitting structure is a rectangle, a fan ring or a trapezoid.

[0010] Optionally, an outer contour of an orthographic projection of the through hole on the light-emitting structure is a rectangle, and a ratio of a length of a long side of the rectangle to a length of a short side of the rectangle is greater than 3 and less than or equal to 5.

[0011] Optionally, the light-emitting structure includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence, the light-emitting structure having a table extending from a surface of the second semiconductor layer away from the light-emitting layer to the first semiconductor layer; the light-emitting diode also includes a connecting electrode layer, the connecting electrode layer is located between the light-emitting structure and the first passivation layer, the connecting electrode layer includes a first connecting electrode and a second connecting electrode, the first connecting electrode is located on the table and connected to the first semiconductor layer, the second connecting electrode is located on a surface of the second semiconductor layer away from the light-emitting layer and connected to the second semiconductor layer; the through hole includes a first through hole and a second through hole, the first through hole is located on the first connecting electrode, and the second through hole is located on the second connecting electrode.

[0012] On the other hand, a method for preparing a light-emitting diode is provided, comprising: forming a passivation material layer on a light-emitting structure; forming a first photoresist layer on the passivation material layer, the first photoresist layer having a photolithography hole exposing the passivation material layer, the outer contour of the orthographic projection of the photolithography hole on the passivation material layer comprising a first side, a second side, a third side and a fourth side connected in sequence end to end, the first side and the third side are opposite to each other, the length of the first side and the length of the third side are smaller than the length of the second side, and the length of the first side and the length of the third side are smaller than the length of the fourth side; etching the passivation material layer under the cover of the first photoresist layer to form a first passivation layer having a through hole, the outer contour of the orthographic projection of the through hole on the light-emitting structure being the same in shape as the outer contour of the orthographic projection of the photolithography hole on the passivation material layer.

[0013] Optionally, forming a first photoresist layer on the passivation material layer includes: forming a second photoresist layer on the passivation material layer, the second photoresist layer having an initial photolithography hole exposing the passivation material layer; physically bombarding the second photoresist layer and the initial photolithography hole to obtain the first photoresist layer having the photolithography hole, the orthographic projection of the opening of the photolithography hole close to the passivation material layer on the passivation material layer, the interior of the orthographic projection of the opening of the photolithography hole away from the passivation material layer on the passivation material layer, and the sidewall of the photolithography hole is arc-shaped and bulges toward the center of the photolithography hole.

[0014] Optionally, the gas used for the physical bombardment is Ar.

[0015] Optionally, the upper radio frequency power of the physical bombardment is 50W to 150W, and the lower radio frequency power of the physical bombardment is 150W to 250W.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, the first passivation layer has a through hole, and the outer contour of the orthographic projection of the through hole on the light-emitting structure includes a first side, a second side, a third side and a fourth side connected in sequence from end to end, the first side and the third side are opposite, the length of the first side and the length of the third side are less than the length of the second side, and the length of the first side and the length of the third side are less than the length of the fourth side. In this way, when the first passivation layer is formed by a photolithography process, the ability of the corresponding photoresist layer to resist stress during baking in the second side and the fourth side region with a longer length can be reduced, and the photoresist material in this region is more likely to deform and shrink, thereby effectively improving the inclination angle of the side wall of the through hole of the first passivation layer, and the slope of the side wall of the through hole relative to the surface of the light-emitting structure is more gentle. When the pad electrode layer is subsequently formed on the first passivation layer, the pad electrode layer can fill the through hole more evenly, and achieve reliable electrical connection with the light-emitting structure through the through hole, thereby reducing the probability of the pad electrode layer breaking or falling off, and improving the reliability of the LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a schematic diagram of the structure of an LED provided by an embodiment of the present disclosure;

[0020] Figure 2 is a top view of an LED provided by an embodiment of the present disclosure;

[0021] Figure 3 is a top view of another LED provided by an embodiment of the present disclosure;

[0022] Figure 4 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure;

[0023] Figure 5 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a schematic diagram of a local structure in the LED manufacturing process provided by an embodiment of the present disclosure;

[0025] Figure 7 It is a schematic diagram of the local structure of the LED manufacturing process provided by the embodiment of the present disclosure.

[0026] Reference numerals:

[0027] 10: light-emitting structure; 11: first semiconductor layer; 12: light-emitting layer; 13: second semiconductor layer; 14: table; 20: first passivation layer; 201: passivation material layer; 21: through hole; 21a: first side; 21b: second side; 21c: third side; 21d: fourth side; 211: first through hole; 212: second through hole; 30: first photoresist layer; 31: photolithography hole; 40: second photoresist layer; 41: initial photolithography hole; 50: substrate; 51: bonding layer; 60: first connecting electrode; 61: second connecting electrode; 70: first pad electrode; 71: second pad electrode; 80: second passivation layer. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0029] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate that there is at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] Figure 1 Schematic diagram of the structure of an LED provided by an embodiment of the present disclosure. Figure 1 As shown, the LED includes a light emitting structure 10 and a first passivation layer 20 . The first passivation layer 20 is located on the surface of the light emitting structure 10 , and the first passivation layer 20 has a through hole 21 .

[0031] Figure 2 is a top view of an LED provided by an embodiment of the present disclosure. Figure 1 and Figure 2The outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 includes a first side 21a, a second side 21b, a third side 21c and a fourth side 21d connected in sequence end to end. The first side 21a and the third side 21c are opposite to each other, the length of the first side 21a and the length of the third side 21c are less than the length of the second side 21b, and the length of the first side 21a and the length of the third side 21c are less than the length of the fourth side 21d.

[0032] In the embodiment of the present disclosure, the outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 has a second side 21b and a fourth side 21d with a relatively long length. In this way, when the first passivation layer 20 is formed by a photolithography process, the ability of the corresponding photoresist layer to resist the stress during baking in the second side 21b and the fourth side 21d region with a relatively long length can be reduced, and the photoresist material in this region is more likely to deform and shrink, thereby effectively increasing the inclination angle of the side wall of the through hole 21 of the first passivation layer 20, that is, increasing the angle between the side wall of the through hole 21 and the normal line of the surface of the light emitting structure 10, and the side wall of the through hole 21 has a gentler slope relative to the surface of the light emitting structure 10. When the pad electrode layer is subsequently formed on the first passivation layer 20, the pad electrode layer can fill the through hole 21 more evenly, and achieve reliable electrical connection with the light emitting structure 10 through the through hole 21, thereby reducing the probability of the pad electrode layer breaking or falling off, and improving the reliability of the LED.

[0033] Exemplarily, the orthographic projection of the opening of the through hole 21 close to the light emitting structure 10 on the light emitting structure 10 is located inside the orthographic projection of the opening of the through hole 21 far from the light emitting structure 10 on the light emitting structure 10 .

[0034] Optionally, the angle between the side wall of the through hole 21 located at the second side 21b and the fourth side 21d and the normal to the surface of the light emitting structure 10 is greater than the angle between the side wall of the through hole 21 located at the first side 21a and the normal to the surface of the light emitting structure 10. The angle between the side wall of the through hole 21 located at the second side 21b and the fourth side 21d and the normal to the surface of the light emitting structure 10 is greater than the angle between the side wall of the through hole 21 located at the third side 21c and the normal to the surface of the light emitting structure 10. In this way, the inclination angle of the side wall of the through hole 21 located at the second side 21b and the fourth side 21d with a longer length is larger, which can effectively increase the area of ​​the side wall with a gentle slope in the through hole 21, which is conducive to more uniform filling of the through hole by the subsequent pad electrode layer, thereby effectively improving the reliability of the LED.

[0035] Optionally, the maximum angle α between the side wall of the through hole 21 and the normal to the surface of the light emitting structure 10 is 65° to 70°. If α is too small, the side wall of the through hole 21 is steeper, and when the pad electrode layer is subsequently formed on the first passivation layer 20, it is difficult for the pad electrode layer to uniformly fill the through hole 21. If α is too large, it is not conducive to the miniaturization of the LED size. When α is within this range, when the pad electrode layer is subsequently formed on the first passivation layer 20, the pad electrode layer can more uniformly fill the through hole 21, and achieve reliable electrical connection with the light emitting structure 10 through the through hole 21, thereby improving the reliability of the LED, and at the same time, the size of the LED will not be affected by the excessive size of the through hole 21.

[0036] For example, the maximum angle α between the sidewall of the through hole 21 and the normal line of the surface of the light emitting structure 10 may be 65°, 67°, 70°, etc.

[0037] In the related art, the angle between the side wall of the through hole and the normal of the surface of the light-emitting structure is relatively small. In the embodiment of the present disclosure, α is within the above relatively large range, which can effectively improve the filling effect of the pad electrode layer and reduce the probability of the pad electrode layer breaking or falling off.

[0038] Optionally, the outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 is a rectangle, a sector ring or a trapezoid.

[0039] like Figure 2 As shown, the outer contour of the orthographic projection of the through hole 21 on the light emitting structure is a rectangle, the long sides of the rectangle are the second side 21b and the fourth side 21d, and the short sides of the rectangle are the first side 21a and the third side 21c.

[0040] Optionally, the ratio of the length L1 of the long side of the rectangle to the length L2 of the short side of the rectangle is greater than 3 and less than or equal to 5. If the ratio of L1 to L2 is too small, it is not conducive to reducing the ability of the photoresist layer in the long side area of ​​the rectangle to resist the stress during baking during photolithography. If the ratio of L1 to L2 is too large, it is not conducive to the miniaturization of the LED size. When the ratio of L1 to L2 is within this range, the ability of the photoresist layer in the long side area of ​​the rectangle to resist the stress during baking during photolithography can be effectively reduced, thereby increasing the inclination angle of the side wall of the through hole 21 of the first passivation layer 20, which is conducive to improving the reliability of the LED.

[0041] For example, the ratio of the length L1 of the long side of the rectangle to the length L2 of the short side of the rectangle may be 3.5, 4, 4.5, or the like.

[0042] Optionally, the length L1 of the long side of the rectangle is 9 μm to 11 μm, and the length L2 of the short side of the rectangle is 4 μm to 6 μm. In this way, the reliability of the LED can be improved without affecting the miniaturization of the size of the LED.

[0043] For example, the length L1 of the long side of the rectangle may be 9 μm, 10 μm, or 11 μm, etc., and the length L2 of the short side of the rectangle may be 4 μm, 5 μm, or 6 μm, etc.

[0044] Figure 3 FIG. 1 is a top view of another LED provided by an embodiment of the present disclosure. Figure 3 As shown, the outer contour of the orthographic projection of the through hole 21 on the light-emitting structure is a fan-shaped ring.

[0045] Exemplarily, the fan ring includes two arcuate edges and two straight edges parallel to each other, and the two ends of each arcuate edge are respectively connected to the two straight edges. The arcuate edges of the fan ring are the second side 21b and the fourth side 21d, and the straight edges of the fan ring are the first side 21a and the third side 21c.

[0046] Exemplarily, the lengths of the two straight sides of the sector ring are the same, and the lengths of the two arcuate sides are the same.

[0047] Optionally, the length of the straight side of the fan ring is 4 μm to 6 μm, and the length of the arc side of the fan ring is 7 μm to 9 μm. In this way, the reliability of the LED can be improved without affecting the miniaturization of the size of the LED.

[0048] For example, the length of the straight side of the sector ring shape may be 4 μm, 5 μm, or 6 μm, etc., and the length of the arcuate side of the sector ring shape may be 7 μm, 8 μm, or 9 μm, etc.

[0049] In other embodiments, the outer contour of the orthographic projection of the through hole 21 on the light-emitting structure may be a trapezoid, the upper base and the lower base of the trapezoid are respectively the first side 21a and the third side 21c of shorter length, and the two waists of the trapezoid are respectively the second side 21b and the fourth side 21d of longer length, or the upper base and the lower base of the trapezoid are respectively the second side 21b and the fourth side 21d of longer length, and the two waists of the trapezoid are respectively the first side 21a and the third side 21c of shorter length; or, the outer contour of the orthographic projection of the through hole 21 on the light-emitting structure may also be a parallelogram other than a rectangle, and the present disclosure does not impose any limitation on this.

[0050] Optionally, the first passivation layer 20 may be a SiO 2 layer.

[0051] By way of example, the thickness of the first passivation layer 20 may be 30,000 angstroms.

[0052] like Figure 1 As shown, the LED further includes a substrate 50 and a bonding layer 51 , and the substrate 50 is bonded to the light emitting structure 10 via the bonding layer 51 .

[0053] Illustratively, the substrate may be a sapphire substrate.

[0054] In other embodiments, the substrate may also be a Si substrate or a SiC substrate, which is not limited in the present disclosure.

[0055] Illustratively, the material of the bonding layer may be any one of photoresist, benzocyclobutene, and silica gel.

[0056] Optionally, the light emitting structure 10 includes a first semiconductor layer 11, a light emitting layer 12 and a second semiconductor layer 13 stacked in sequence in a direction away from the substrate 50, and the light emitting structure 10 has a mesa (MESA) 14 extending from a surface of the second semiconductor layer 13 away from the light emitting layer 12 toward the first semiconductor layer 11.

[0057] Optionally, the first semiconductor layer 11 is a P-type semiconductor layer.

[0058] Optionally, the first semiconductor layer 11 includes a window layer and a first carrier confinement layer which are sequentially stacked in a direction away from the substrate 50 .

[0059] Exemplarily, the window layer may be a P-type GaP window layer.

[0060] Exemplarily, the thickness of the window layer is 2.8 μm to 3.2 μm. For example, the thickness of the window layer may be 3 μm.

[0061] Exemplarily, the first carrier confinement layer may be a P-type AlInP carrier confinement layer.

[0062] Optionally, the light emitting layer 12 is a multi-quantum well layer, comprising a plurality of pairs of alternately stacked AlGaInP quantum barrier layers and AlGaInP quantum well layers, wherein the Al component content of the AlGaInP quantum barrier layers is greater than the Al component content of the AlGaInP quantum well layers.

[0063] Optionally, the second semiconductor layer 13 is an N-type semiconductor layer.

[0064] Exemplarily, the second semiconductor layer 13 includes a second carrier confinement layer, a current spreading layer, and an corrosion stop layer which are sequentially stacked in a direction away from the substrate 50 .

[0065] Exemplarily, the second carrier confinement layer may be an N-type AlInP carrier confinement layer.

[0066] Exemplarily, the current spreading layer may be an N-type AlGaInP current spreading layer.

[0067] Exemplarily, the etch stop layer may be a GaInP etch stop layer.

[0068] It should be noted that the film layer structure of the above-mentioned light-emitting structure 10 and the material of the above-mentioned film layer are only used as an example. In other embodiments, the light-emitting structure 10 can also include more or fewer film layer structures, and the material of each film layer can be selected according to actual needs, etc., and the present disclosure does not impose any restrictions on this.

[0069] Optionally, the LED further includes a connecting electrode layer, which is located between the light emitting structure 10 and the first passivation layer 20. The connecting electrode layer includes a first connecting electrode 60 and a second connecting electrode 61, wherein the first connecting electrode 60 is located on the table 14 and connected to the first semiconductor layer 11, and the second connecting electrode 61 is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12 and connected to the second semiconductor layer 13. The connecting electrode layer can improve the lateral expansion capability of the current, so that the current can be more evenly expanded laterally to various regions of the light emitting structure 10, improve the radiation recombination efficiency of the carriers, and improve the luminous efficiency of the LED. In addition, the connecting electrode layer can be reliably connected to the subsequently formed pad electrode layer, which is conducive to reducing the probability of the pad electrode layer falling off and improving the reliability of the LED.

[0070] like Figures 1 to 3 As shown, the through hole 21 includes a first through hole 211 and a second through hole 212 . The first through hole 211 is located on the first connection electrode 60 , and the second through hole 212 is located on the second connection electrode 61 .

[0071] Exemplarily, when the outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 is a rectangle, the arrangement direction of the first through hole 211 and the second through hole 212 is the length direction of the short side of the rectangle.

[0072] Exemplarily, when the outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 is a fan ring, the arrangement direction of the first through hole 211 and the second through hole 212 is the length direction of the straight side of the fan ring.

[0073] Optionally, the LED further includes a pad electrode layer, the pad electrode layer includes a first pad electrode 70 and a second pad electrode 71, the first pad electrode 70 is connected to the first connection electrode 60 through a first through hole 211, and the second pad electrode 71 is connected to the second connection electrode 61 through a second through hole 212. The pad electrode layer is used to connect to an external power source, which is beneficial to carrier injection.

[0074] Optionally, the material of the pad electrode layer includes a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au layer stacked in sequence in a direction away from the connection electrode layer. In this way, the pad electrode layer can be guaranteed to have good adhesion and conductivity, which is not only conducive to the stable connection between the pad electrode layer and the connection electrode layer, but also reduces the probability of the pad electrode layer falling off, improves the reliability of the LED, and is also conducive to carrier injection.

[0075] Exemplarily, the thickness of the Cr layer is 80 nm to 120 nm. For example, the thickness of the Cr layer may be 100 nm.

[0076] Exemplarily, the thickness of the Al layer is 2500 nm to 3500 nm. For example, the thickness of the Al layer may be 3000 nm.

[0077] Exemplarily, the thickness of the Ti layer is 450 nm to 550 nm. For example, the thickness of the Ti layer may be 500 nm.

[0078] Exemplarily, the thickness of the Ni layer is 1800 nm to 2200 nm. For example, the thickness of the Ni layer may be 2000 nm.

[0079] Exemplarily, the thickness of the Au layer is 18000 nm to 22000 nm. For example, the thickness of the Au layer may be 20000 nm.

[0080] Optionally, the LED further includes a second passivation layer 80, which is located on a surface of the first passivation layer 20 away from the light emitting structure 10, and has an opening exposing the first pad electrode 70 and the second pad electrode 71. The second passivation layer 80 can protect the surfaces of the LED that may be exposed, reduce the influence of mechanical damage or chemical corrosion on the LED, and ensure the reliability of the LED.

[0081] Exemplarily, the second passivation layer 80 is also located on the sidewalls of the first passivation layer 20 and the sidewalls of the light emitting structure 10 .

[0082] Optionally, the second passivation layer 80 may be at least one of a SiO 2 layer, an Al 2 O 3 layer, a SiN layer or a SiON layer.

[0083] Figure 4 FIG. 1 is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:

[0084] In step S1001 , a passivation material layer is formed on the light emitting structure.

[0085] In step S1002 , a first photoresist layer is formed on the passivation material layer.

[0086] The first photoresist layer has a photolithography hole exposing the passivation material layer, and the outer contour of the positive projection of the photolithography hole on the passivation material layer includes a first side, a second side, a third side and a fourth side connected in sequence end to end, the first side and the third side are opposite, the length of the first side and the length of the third side are smaller than the length of the second side, and the length of the first side and the length of the third side are smaller than the length of the fourth side.

[0087] In step S1003 , the passivation material layer is etched under the cover of the first photoresist layer to form a first passivation layer having a through hole.

[0088] The outer contour of the orthographic projection of the through hole on the light emitting structure is the same as the outer contour of the orthographic projection of the photolithographic hole on the passivation material layer.

[0089] In the disclosed embodiment, a first photoresist layer is first formed on the passivation material layer, and the outer contour of the positive projection of the photolithography hole of the first photoresist layer on the passivation material layer includes a first side, a second side, a third side and a fourth side connected in sequence end to end, the first side and the third side are opposite, the length of the first side and the length of the third side are less than the length of the second side, and the length of the first side and the length of the third side are less than the length of the fourth side, so that the ability of the first photoresist layer to resist the stress during baking in the second side and the fourth side region with a longer length can be reduced, and the photoresist material in this region is more likely to deform and shrink when the first photoresist layer is formed, so that the inclination angle of the side wall of the photolithography hole can be increased. Then, the passivation material layer is etched under the cover of the first photoresist layer to form a first passivation layer with a through hole. The outer contour of the orthographic projection of the through hole on the light-emitting structure is the same as the shape of the outer contour of the orthographic projection of the photolithographic hole on the passivation material layer, that is, it includes the same first side, second side, third side and fourth side. Therefore, the inclination angle of the side wall of the through hole of the first passivation layer can be effectively increased, that is, the angle between the side wall of the through hole and the normal of the surface of the light-emitting structure is increased. When the pad electrode layer is subsequently formed on the first passivation layer, the pad electrode layer can fill the through hole more evenly and achieve reliable electrical connection with the light-emitting structure through the through hole, thereby reducing the probability of the pad electrode layer breaking or falling off, and improving the reliability of the LED.

[0090] Figure 5 FIG. 1 is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure. Figure 5 As shown, the preparation method comprises:

[0091] In step S2001, a light emitting structure is formed on a substrate.

[0092] Optionally, step S2001 may include the following steps:

[0093] In the first step, an epitaxial stack is formed on a growth substrate.

[0094] Optionally, the growth substrate may be placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, and a second semiconductor layer, a light-emitting layer and a first semiconductor layer may be sequentially formed on the growth substrate to obtain an epitaxial stack.

[0095] Exemplarily, the growth substrate may be a GaAs substrate.

[0096] In the second step, the epitaxial stack is bonded to the substrate.

[0097] Optionally, a bonding layer may be formed by coating on the substrate, and the first semiconductor layer is bonded to the substrate via the bonding layer.

[0098] Exemplarily, the bonding temperature is 300°C to 350°C. For example, the bonding temperature may be 300°C.

[0099] Optionally, the first semiconductor layer may be roughened before bonding.

[0100] The third step is to remove the growth substrate.

[0101] Illustratively, the growth substrate on the second semiconductor layer may be removed by wet etching.

[0102] In the fourth step, a mesa (MESA) is formed in the epitaxial stack, extending from the surface of the second semiconductor layer away from the light emitting layer toward the first semiconductor layer.

[0103] Illustratively, a photoresist structure can be obtained on the surface of the second semiconductor layer away from the light-emitting layer through processes such as photoresist coating, exposure, and development, and the surface of the second semiconductor layer away from the light-emitting layer can be etched using the photoresist structure as a mask through methods such as inductively coupled plasma (ICP) etching, and the etching depth extends from the surface of the second semiconductor layer away from the light-emitting layer to the window layer, and after removing the photoresist structure, a table is formed exposing the first semiconductor layer.

[0104] Through the first to fourth steps above, a light emitting structure can be formed on the substrate.

[0105] Optionally, after the light emitting structure is formed, deep etching (Isolation, ISO) photolithography may be performed on the light emitting structure to form a cutting path exposing the substrate.

[0106] In step S2002 , a passivation material layer is formed on the light emitting structure.

[0107] Figure 6 FIG. 1 is a schematic diagram of a local structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 6 As shown, a passivation material layer 201 may be deposited on the entire surface of the light emitting structure 10 using a plasma enhanced chemical vapor deposition (PECVD) technique.

[0108] Exemplarily, the passivation material layer 201 may be a SiO 2 layer.

[0109] Optionally, before forming the passivation material layer 201 , a connection electrode layer may be formed on the light emitting structure 10 .

[0110] Optionally, after the connection electrode layer is formed, the connection electrode layer may be annealed.

[0111] In step S2003 , a second photoresist layer is formed on the passivation material layer.

[0112] Optionally, step S2003 may include the following steps:

[0113] In the first step, a layer of photoresist material is coated on the passivation material layer.

[0114] Optionally, after the photoresist material is coated, the photoresist material may be baked before exposure, so that the photoresist material can be well hardened, making it easier to perform subsequent exposure and development operations on the photoresist material.

[0115] The second step is to expose the photoresist material under the cover of the mask.

[0116] Optionally, after the photoresist material is exposed, the photoresist material may be baked after exposure.

[0117] The third step is to develop the photoresist material to obtain a second photoresist layer.

[0118] Through the above-mentioned first to third steps, a second photoresist layer can be formed on the passivation material layer. Figure 6 As shown, the second photoresist layer 40 has an initial photolithography hole 41 exposing the passivation material layer 201 .

[0119] In step S2004, the second photoresist layer and the initial photolithography holes are physically bombarded to obtain a first photoresist layer having photolithography holes.

[0120] Figure 7 FIG. 1 is a schematic diagram of a local structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 6 and Figure 7Physical bombardment refers to bombarding the second photoresist layer 40 with inert gas plasma, which can expand the opening of the initial photolithography hole 41 away from the passivation material layer 201 outward, thereby increasing the inclination angle of the side wall of the initial photolithography hole 41, and obtaining the first photoresist layer 30 with the photolithography hole 31. After the physical bombardment, the orthographic projection of the opening of the photolithography hole 31 in the first photoresist layer 30 close to the passivation material layer 201 on the passivation material layer 201 is located inside the orthographic projection of the opening of the photolithography hole 31 away from the passivation material layer 201 on the passivation material layer 201, and the side wall of the photolithography hole 31 is arc-shaped and bulges toward the center of the photolithography hole 31.

[0121] In this way, when the passivation material layer 201 is subsequently etched under the cover of the first photoresist layer 30 to form the first passivation layer, the inclination angle of the side wall of the through hole of the first passivation layer can be increased.

[0122] Optionally, the gas used for physical bombardment is Ar. When Ar is used to physically bombard the second photoresist layer 40, the opening of the initial photolithography hole 41 away from the passivation material layer 201 can be better expanded outward, and the opening of the initial photolithography hole 41 close to the passivation material layer 201 and the passivation material layer 201 will not be greatly affected.

[0123] In other embodiments, the gas used for physical bombardment may also be other inert gases according to actual needs, and the present disclosure does not impose any limitation on this.

[0124] Optionally, the upper RF power of the physical bombardment is 50 W to 150 W. If the upper RF power is too low, too little plasma will be generated, and if the upper RF power is too high, too much plasma will be generated. Too little or too much plasma will inhibit the reaction rate of the physical bombardment. The upper RF power within this range is conducive to generating a suitable amount of plasma, which can effectively expand the opening of the initial lithography hole 41 away from the passivation material layer 201 toward the outside.

[0125] For example, the upper radio frequency power of the physical bombardment may be 50 W, 100 W, or 150 W, etc.

[0126] Optionally, the lower RF power of the physical bombardment is 150 W to 250 W. If the lower RF power is too low, it will affect the energy during plasma bombardment, and the physical bombardment ability will be weak. If the lower RF power is too high, it will cause excessive energy during plasma bombardment, and the physical bombardment ability will be strong, which may affect the opening of the initial lithographic hole 41 close to the passivation material layer 201 and the passivation material layer 201. The lower RF power within this range can better expand the opening of the initial lithographic hole 41 away from the passivation material layer 201 and increase the inclination angle of the side wall of the through hole of the first passivation layer.

[0127] For example, the lower radio frequency power of the physical bombardment may be 150 W, 200 W, or 250 W, etc.

[0128] Through the above steps S2003 to S2004, a first photoresist layer 30 can be formed on the passivation material layer 201. The first photoresist layer 30 has a photolithography hole 31 exposing the passivation material layer 201, and the outer contour of the orthographic projection of the photolithography hole 31 on the passivation material layer 201 includes a first side, a second side, a third side and a fourth side connected in sequence from end to end, the first side is opposite to the third side, the length of the first side and the length of the third side are less than the length of the second side, and the length of the first side and the length of the third side are less than the length of the fourth side.

[0129] Optionally, the outer contour of the orthographic projection of the photolithographic hole 31 on the passivation material layer 201 is a rectangle, a sector ring or a trapezoid.

[0130] In step S2005 , the passivation material layer is etched under the cover of the first photoresist layer to form a first passivation layer.

[0131] like Figure 1 As shown, the first passivation layer 20 is located on the surface of the light emitting structure 10 away from the substrate 50. When a connection electrode layer is provided, the connection electrode layer is located between the light emitting structure 10 and the first passivation layer 20, and the first passivation layer 20 has a through hole 21 exposing the connection electrode layer, and the through hole 21 includes a first through hole 211 and a second through hole 212, the first through hole 211 is located on the first connection electrode 60, and the second through hole 212 is located on the second connection electrode 61. When no connection electrode layer is provided, the first passivation layer 20 has a through hole 21 exposing the light emitting structure 10.

[0132] The outer contour of the orthographic projection of the through hole 21 on the light emitting structure 10 is the same as the outer contour of the orthographic projection of the photolithographic hole on the passivation material layer.

[0133] In step S2006 , a pad electrode layer is formed on the first passivation layer.

[0134] like Figures 1 to 3 As shown, the pad electrode layer includes a first pad electrode 70 and a second pad electrode 71 . The first pad electrode 70 is connected to the first connection electrode 60 through a first through hole 211 , and the second pad electrode 71 is connected to the second connection electrode 61 through a second through hole 212 .

[0135] For example, a photoresist structure may be obtained on the first passivation layer 20 through processes such as photoresist coating, exposure, and development, and the pad electrode layer may be formed through an electron beam evaporation process and a stripping process using the photoresist structure as a mask.

[0136] In step S2007 , a second passivation layer is formed on the first passivation layer.

[0137] Optionally, the second passivation layer 80 is located on a surface of the first passivation layer 20 away from the light emitting structure 10 , and the second passivation layer 80 has an opening exposing the first pad electrode 70 and the second pad electrode 71 .

[0138] Exemplarily, an initial second passivation layer can be deposited on the entire surface of the first passivation layer 20, and a photoresist structure can be obtained on the initial second passivation layer through processes such as photoresist coating, exposure, and development. The initial second passivation layer is etched using the photoresist structure as a mask through a BOE process or an ICP etching method, and the second passivation layer 80 is formed after removing the photoresist structure.

[0139] Optionally, after completing step S2007, the substrate may be cleaved along the cutting path by a cleaving process, and the LED may be tested.

[0140] Optionally, the structure, shape, material and thickness of the LED refer to Figures 1 to 3 The detailed description of the related structural embodiments is omitted here.

[0141] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A light emitting diode, characterized in that: It comprises a light emitting structure (10) and a first passivation layer (20), The first passivation layer (20) is located on the surface of the light-emitting structure (10), and the first passivation layer (20) has a through hole (21); the outer contour of the orthographic projection of the through hole (21) on the light-emitting structure (10) comprises a first side (21a), a second side (21b), a third side (21c) and a fourth side (21d) connected in sequence end to end; the first side (21a) and the third side (21c) are opposite to each other, the length of the first side (21a) and the length of the third side (21c) are smaller than the length of the second side (21b), and the length of the first side (21a) and the length of the third side (21c) are smaller than the length of the fourth side (21d).

2. The light emitting diode according to claim 1, characterized in that: The orthographic projection of the opening of the through hole (21) close to the light-emitting structure (10) on the light-emitting structure (10) is located inside the orthographic projection of the opening of the through hole (21) far from the light-emitting structure (10) on the light-emitting structure (10); The angle between the side wall of the through hole (21) located at the second side (21b) and the fourth side (21d) and the normal line of the surface of the light-emitting structure (10) is greater than the angle between the side wall of the through hole (21) located at the first side (21a) and the normal line of the surface of the light-emitting structure (10); The angle between the side walls of the through hole (21) located on the second side (21b) and the fourth side (21d) and the normal to the surface of the light-emitting structure (10) is greater than the angle between the side walls of the through hole (21) located on the third side (21c) and the normal to the surface of the light-emitting structure (10).

3. The light emitting diode according to claim 2, characterized in that: The maximum angle between the side wall of the through hole (21) and the normal line of the surface of the light-emitting structure (10) is 65° to 70°.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The outer contour of the orthographic projection of the through hole (21) on the light-emitting structure (10) is a rectangle, a sector ring or a trapezoid.

5. The light emitting diode according to claim 4, characterized in that: The outer contour of the orthographic projection of the through hole (21) on the light-emitting structure (10) is a rectangle, and the ratio of the length of the long side of the rectangle to the length of the short side of the rectangle is greater than 3 and less than or equal to 5.

6. The light emitting diode according to any one of claims 1 to 3 and claim 5, characterized in that: The light emitting structure (10) comprises a first semiconductor layer (11), a light emitting layer (12) and a second semiconductor layer (13) which are stacked in sequence, and the light emitting structure (10) has a mesa (14) extending from a surface of the second semiconductor layer (13) away from the light emitting layer (12) toward the first semiconductor layer (11); The light-emitting diode further comprises a connecting electrode layer, the connecting electrode layer being located between the light-emitting structure (10) and the first passivation layer (20), the connecting electrode layer comprising a first connecting electrode (60) and a second connecting electrode (61), the first connecting electrode (60) being located on the mesa (14) and connected to the first semiconductor layer (11), and the second connecting electrode (61) being located on a surface of the second semiconductor layer (13) away from the light-emitting layer (12) and connected to the second semiconductor layer (13); The through hole (21) comprises a first through hole (211) and a second through hole (212); the first through hole (211) is located on the first connecting electrode (60), and the second through hole (212) is located on the second connecting electrode (61).

7. A method for preparing a light emitting diode, characterized in that: include: forming a passivation material layer (201) on the light emitting structure (10); A first photoresist layer (30) is formed on the passivation material layer (201), wherein the first photoresist layer (30) has a photolithography hole (31) exposing the passivation material layer (201), and the outer contour of the orthographic projection of the photolithography hole (31) on the passivation material layer (201) comprises a first side edge (21a), a second side edge (21b), a third side edge (21c) and a fourth side edge (21d) connected in sequence end to end, the first side edge (21a) and the third side edge (21c) are opposite to each other, the length of the first side edge (21a) and the length of the third side edge (21c) are shorter than the length of the second side edge (21b), and the length of the first side edge (21a) and the length of the third side edge (21c) are shorter than the length of the fourth side edge (21d); The passivation material layer (201) is etched under the cover of the first photoresist layer (30) to form a first passivation layer (20) having a through hole (21), wherein the outer contour of the orthographic projection of the through hole (21) on the light-emitting structure (10) is the same shape as the outer contour of the orthographic projection of the photolithographic hole (31) on the passivation material layer (201).

8. The preparation method according to claim 7, characterized in that: The step of forming a first photoresist layer (30) on the passivation material layer (201) comprises: forming a second photoresist layer (40) on the passivation material layer (201), wherein the second photoresist layer (40) has an initial photolithography hole (41) exposing the passivation material layer (201); The second photoresist layer (40) and the initial photolithography hole (41) are physically bombarded to obtain the first photoresist layer (30) having the photolithography hole (31), wherein the orthographic projection of the opening of the photolithography hole (31) close to the passivation material layer (201) on the passivation material layer (201) is located inside the orthographic projection of the opening of the photolithography hole (31) far from the passivation material layer (201) on the passivation material layer (201), and the side wall of the photolithography hole (31) is arc-shaped and bulges toward the center of the photolithography hole (31).

9. The preparation method according to claim 8, characterized in that: The gas used for the physical bombardment is Ar.

10. The preparation method according to claim 8, characterized in that: The upper radio frequency power of the physical bombardment is 50W to 150W, and the lower radio frequency power of the physical bombardment is 150W to 250W.

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