Protection driving circuit of battery system

Abstract

The invention provides a protection driving circuit of a battery system, and particularly relates to the technical field of battery protection chip design, the protection driving circuit comprises a first driving transistor and a second resistor which are connected in series between a positive electrode of a battery and a driving output end, a grid electrode of the first driving transistor is coupled to a control input end, and a grid electrode of the second driving transistor is coupled to a control output end. The control input end is used for receiving a control signal; the second driving transistor is connected in series between the driving output end and the negative electrode output end; the first resistor is connected between the grid electrode of the second driving transistor and the control input end in series; the clamping circuit is coupled between the grid electrode of the second driving transistor and the negative electrode output end; and the clamping circuit is used for clamping the voltage difference between the grid electrode of the second driving transistor and the negative electrode output end within a preset voltage. The first driving transistor and the second driving transistor can be supported to use low-voltage transistors, so that the overall manufacturing cost of the protection driving circuit is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of battery protection chip design, and in particular to a protection drive circuit for a battery system. Background Art

[0002] Battery protection chips, especially those for low-voltage batteries with an output voltage below 5V, need to use a gate control signal driver tube that can withstand high voltages of up to 20V or even 28V for the charging control tube on the protection board. Therefore, high-voltage-resistant transistors need to be used in the circuit design of the gate control signal driver tube. High-voltage-resistant transistors rely on high-cost high-voltage processes, which results in a relatively high manufacturing cost for battery protection chips. Summary of the invention

[0003] The purpose of the present disclosure is to provide a protection driving circuit for a battery system, so as to solve the technical problem of high manufacturing cost of a battery protection chip designed in the related art.

[0004] In a first aspect, an embodiment of the present disclosure provides a protection driving circuit for a battery system, the protection driving circuit comprising:

[0005] A first driving transistor and a second resistor are connected in series between the positive electrode of the battery and the driving output terminal, wherein the gate of the first driving transistor is coupled to the control input terminal, and the control input terminal is used to receive a control signal;

[0006] A second driving transistor connected in series between the driving output terminal and the negative output terminal;

[0007] A first resistor connected in series between the gate of the second driving transistor and the control input terminal;

[0008] A clamping circuit is coupled between the gate of the second driving transistor and the negative output terminal, and the clamping circuit is used to clamp the voltage difference between the gate of the second driving transistor and the negative output terminal within a predetermined voltage.

[0009] In one embodiment, the high level of the control signal is the voltage of the positive electrode of the battery, and the low level of the control signal is the voltage of the negative electrode of the battery;

[0010] When the control signal is at a low level, the first driving transistor is turned on, the second driving transistor is turned off, the driving signal output by the driving output terminal is at a high level, and the high level of the driving signal is the voltage of the positive electrode of the battery;

[0011] When the control signal is at a high level, the first driving transistor is turned off, the second driving transistor is turned on, the driving signal output by the driving output terminal is at a low level, and the low level of the driving signal is the voltage of the cathode output terminal.

[0012] In one embodiment, when the voltage difference between the gate of the second driving transistor and the negative output terminal is greater than or equal to the predetermined voltage, the clamping circuit is reversibly broken down to clamp the voltage difference between the gate of the second driving transistor and the negative output terminal at the predetermined voltage;

[0013] When the voltage difference between the gate of the second driving transistor and the negative output terminal is less than the predetermined voltage, the clamp circuit returns to an initial state. When the clamp circuit is in the initial state, the gate of the second driving transistor to the negative output terminal is in a bidirectional cutoff state.

[0014] In one embodiment, the clamping circuit comprises:

[0015] A first unidirectional conductive device coupled between the first external connection terminal and the intermediate node C and unidirectionally conductive from the first external connection terminal to the intermediate node C; and a second unidirectional conductive device coupled between the second external connection terminal and the intermediate node C and unidirectionally conductive from the second external connection terminal to the intermediate node C;

[0016] The first external connection terminal is coupled to the gate of the second driving transistor, and the second external connection terminal is coupled to the negative output terminal.

[0017] In one embodiment, the first unidirectional conductive device is a diode, a PMOS transistor or a triode, wherein:

[0018] When the first unidirectional conducting device is a diode, the anode of the first unidirectional conducting device is coupled to the first external connection terminal, and the cathode of the first unidirectional conducting device is coupled to the intermediate node C;

[0019] When the first unidirectional conducting device is a PMOS transistor, the source, gate and substrate of the first unidirectional conducting device are coupled to the first external connection terminal, and the drain of the first unidirectional conducting device is coupled to the intermediate node C;

[0020] When the first unidirectional conducting device is a triode, the emitter of the first unidirectional conducting device is coupled to the first external connection terminal, and the base and collector of the first unidirectional conducting device are coupled to the intermediate node C;

[0021] The second unidirectional conductive device is a diode, an NMOS transistor or a triode, wherein:

[0022] When the second unidirectional conducting device is a diode, an anode of the second unidirectional conducting device is coupled to the second external connection terminal, and a cathode of the second unidirectional conducting device is coupled to the intermediate node C;

[0023] When the second unidirectional conducting device is an NMOS transistor, the source, gate and substrate of the second unidirectional conducting device are coupled to the second external connection terminal, and the drain of the second unidirectional conducting device is coupled to the intermediate node C;

[0024] When the second unidirectional conducting device is a triode, the emitter of the second unidirectional conducting device is coupled to the second external connection terminal, and the base and collector of the second unidirectional conducting device are coupled to the intermediate node C;

[0025] Wherein, the transistor is an NPN transistor.

[0026] In one embodiment, when the voltage difference between the source and the drain of the first driving transistor exceeds a second predetermined voltage, the source and the drain of the first driving transistor are reversibly broken down.

[0027] In one embodiment, the driving signal is a charging driving signal, and the driving output terminal is coupled to the control terminal of the charging power switch.

[0028] The source and substrate of the charging power switch are coupled to the negative output terminal P-,

[0029] When the charging drive signal is at a high level, the charging power switch is turned on, and when the charging drive signal is at a low level, the charging power switch is turned off.

[0030] In one embodiment, the first driving transistor is a PMOS transistor MP2, a source of the PMOS transistor MP2 is coupled to the positive electrode of the battery, and a drain of the PMOS transistor MP2 is coupled to the driving output terminal.

[0031] The second driving transistor is an NMOS transistor MN2, the source of the NMOS transistor MN2 is coupled to the negative output terminal, the drain of the NMOS transistor MN2 is coupled to the driving output terminal,

[0032] The first driving transistor and the second driving transistor are manufactured using the same gate process as other MOS transistors in the protection driving circuit, so that the gate oxide breakdown voltage of the first driving transistor and the second driving transistor is equal to the gate oxide breakdown voltage of other MOS transistors.

[0033] In one embodiment, the protection driving circuit further includes:

[0034] A PMOS transistor MP1, wherein a gate of the PMOS transistor MP1 is coupled to the source input terminal, a source of the PMOS transistor MP1 is coupled to the positive electrode of the battery, and a drain of the PMOS transistor MP1 is coupled to the control input terminal;

[0035] an NMOS transistor MN1, wherein a gate of the NMOS transistor MN1 is coupled to the source input terminal, a source of the PMOS transistor MP1 is coupled to the negative electrode of the battery, and a drain of the PMOS transistor MP1 is coupled to the control input terminal;

[0036] The first drive transistor and the second drive transistor are manufactured using the same gate process as the MOS transistors MN1 and MP1, so that the gate oxide breakdown voltage of the first drive transistor and the second drive transistor is equal to the gate oxide breakdown voltage of the MOS transistors MN1 and MP1. In one embodiment, the predetermined voltage is greater than or equal to 5V, and the predetermined voltage is less than or equal to 10V.

[0037] In the present disclosure, based on the setting of the second resistor, the first driving transistor is voltage-divided and current-limited; based on the setting of the first resistor, the second driving transistor is voltage-divided and current-limited, so that the normal operating voltages of the first driving transistor and the second driving transistor are both within the low-voltage range, thereby supporting the use of low-cost low-voltage transistors for the first driving transistor and the second driving transistor to reduce the overall manufacturing cost of the protection driving circuit. Among them, the setting of the clamping circuit is to avoid the gate of the second driving transistor from being directly broken down and causing irreversible damage under extreme working conditions, thereby extending the service life of the second driving transistor and reducing the subsequent maintenance cost of the protection driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a protection drive circuit of a battery system provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of a battery protection circuit and its external circuit provided by an embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of five implementation methods of a clamping circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] In the related art, for the protection chip of the low-voltage battery with an output voltage below 5V, the driving tube of the gate control signal of the charging control tube on the protection board is coupled between the protected battery and the negative output terminal. In the application, since the level of the negative output terminal may be as low as below -20V, the level difference between the battery and the negative output terminal may be as high as 20V or even 28V. Therefore, it is necessary to use a high-voltage MOS tube as the aforementioned driving tube to avoid the situation where the driving tube is irreversibly broken down and causes damage to the protection chip. However, since the high-voltage MOS tube needs to be implemented using a high-voltage process, and the implementation cost of the high-voltage process is higher than that of the low-voltage process, the manufacturing cost of the driving tube of the gate control signal of the charging control tube in the protection chip is higher, which in turn leads to a higher overall manufacturing cost of the protection chip.

[0043] To solve the above problems, the present application provides a protection driving circuit for a battery system, such as Figure 1 As shown, the protection driving circuit includes:

[0044] A first driving transistor MP2 (PMOS transistor) and a second resistor R2 are connected in series between the positive electrode B+ of the battery and the driving output terminal CO, wherein the gate of the first driving transistor MP2 is coupled to the control input terminal C_PRE, and the control input terminal C_PRE is used to receive a control signal;

[0045] A second driving transistor MN2 (NMOS transistor) connected in series between the driving output terminal CO and the negative output terminal P-;

[0046] A first resistor R1 connected in series between the gate of the second driving transistor MN2 and the control input terminal C_PRE;

[0047] A clamp circuit is coupled between the gate of the second driving transistor MN2 and the negative output terminal P-, and the clamp circuit CLAMP CIRCUIT is used to clamp the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- within a predetermined voltage.

[0048] The working mode of the above driving protection circuit is: based on the control signal, the first driving transistor MP2 or the second driving transistor MN2 is turned on to control the driving output terminal CO to output a corresponding high level or low level driving signal.

[0049] Specifically, the high level of the control signal is the voltage of the positive electrode B+ of the battery, and the low level of the control signal is the voltage of the negative electrode B- of the battery;

[0050] When the control signal is at a low level, the first driving transistor MP2 is turned on, the second driving transistor MN2 is turned off, and the driving signal output by the driving output terminal CO is at a high level. The high level of the driving signal is the voltage of the positive electrode B+ of the battery.

[0051] When the control signal is at a high level, the first driving transistor MP2 is turned off, the second driving transistor MN2 is turned on, and the driving signal output by the driving output terminal CO is at a low level, and the low level of the driving signal is the voltage of the cathode output terminal P-.

[0052] When the source and drain of the first driving transistor MP2 are broken down by high voltage, the second resistor R2 can be used to limit current and divide voltage of the first driving transistor MP2 to protect the first driving transistor MP2 from being burned by excessive current or voltage when it is turned on.

[0053] Similarly, when the clamp circuit CLAMP CIRCUIT is broken down, the first resistor R1 can be used to limit the current and divide the voltage of the second driving transistor MN2 to protect the second driving transistor MN2 from being burned by excessive current or voltage when it is turned on.

[0054] That is to say, in the present application, the first resistor R1 and the second resistor R2 are set so that the normal operating voltage of the first driving transistor MP2 and the second driving transistor MN2 can be within the low voltage range, thereby supporting the use of low-cost low-voltage transistors (relative to the use of MOS transistors with a withstand voltage of more than 12V) as the first driving transistor MP2 and the second driving transistor MN2 in the protection driving circuit, so as to reduce the manufacturing cost of the driving tube of the gate control signal of the charging control tube while ensuring that the function of the protection driving circuit can be normally realized, thereby reducing the overall manufacturing cost of the protection driving circuit.

[0055] Among them, the low-cost low-voltage transistor can be understood as a MOS transistor with a lower voltage resistance than a MOS transistor with a voltage resistance of more than 12V. In an example, the voltage resistance of the MOS transistor can be reflected by the thickness of the transistor's gate oxide layer. At this time, the low-cost low-voltage transistor can be a transistor with a gate oxide layer thickness less than the gate oxide layer thickness of a MOS transistor with a voltage resistance of more than 12V.

[0056] Among them, the setting of the clamping circuit CLAMP CIRCUIT is used to clamp the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- within a predetermined voltage, which can avoid the gate oxide electrode of the second driving transistor MN2 being directly broken down and causing irreversible damage under extreme working conditions, thereby supporting the demand for using a low-voltage transistor as the second driving transistor MN2, thereby reducing the overall manufacturing cost of the driving circuit.

[0057] It should be understood that the predetermined voltage is less than the gate oxide breakdown voltage of the second driving transistor MN2, wherein the gate oxide breakdown voltage is specifically the breakdown voltage of the gate oxide layer.

[0058] In one embodiment, the battery protection circuit and its external circuit corresponding to the protection drive circuit of the present invention can be as follows: Figure 2 As shown, the battery protection circuit includes a charging protection circuit and a discharging protection circuit, the charging protection circuit includes the protection driving circuit, the charging control terminal CO (that is, the aforementioned driving output terminal CO) of the charging protection circuit is coupled to the control terminal of the charging power switch MNC, and the discharging control terminal DO of the discharging protection circuit is coupled to the control terminal of the discharging power switch MND.

[0059] Specifically, the aforementioned driving signal is a charging driving signal, and the source and substrate of the charging power switch MNC are coupled to the negative output terminal P-;

[0060] When the charging drive signal is at a high level, the charging power switch MNC is turned on, and the protected battery BAT1 is allowed to be charged. Conversely, when the charging drive signal is at a low level, the charging power switch MNC is turned off, and the protected battery BAT1 is prohibited from being charged.

[0061] Similarly, when the discharge control terminal DO outputs a high-level discharge driving signal, the discharge power switch MND is turned on, and the protected battery BAT1 is allowed to discharge. Conversely, when the discharge driving signal is at a low level, the discharge power switch MND is turned off, and the protected battery BAT1 is prohibited from discharging.

[0062] Among them, the charging control signal C_PRE is generated by the protection drive circuit according to the charging condition of the protected battery. When the battery does not need to be charged, such as when charging overvoltage or charging overcurrent, the charging control signal C_PRE is at a high level, which will cause the charging control terminal CO to output a low-level charging drive signal to prohibit battery charging; and when the battery is allowed to charge, the charging control signal C_PRE is at a low level, which will cause the charging control terminal CO to output a high-level charging drive signal to allow the battery to charge.

[0063] Exemplarily, both the charging power switch MNC and the discharging power switch MND may be NMOS transistors.

[0064] In one embodiment, when the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- is greater than or equal to the predetermined voltage, the clamping circuit CLAMP CIRCUIT is reversibly broken down to clamp the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- at the predetermined voltage;

[0065] When the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- is less than the predetermined voltage, the clamping circuit CLAMP CIRCUIT returns to an initial state. When the clamping circuit CLAMP CIRCUIT is in the initial state, the gate of the second driving transistor MN2 to the negative output terminal P- is in a bidirectional cut-off state.

[0066] In this embodiment, using the above-mentioned setting, when the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- is greater than or equal to the predetermined voltage, the clamping circuit CLAMP CIRCUIT is reversibly broken down to clamp the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- at the predetermined voltage. Since the breakdown of the clamping circuit CLAMP CIRCUIT is reversible, the clamping circuit CLAMP CIRCUIT can be restored to its initial state when the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- is less than the predetermined voltage.

[0067] The reversible breakdown of the clamp circuit CLAMP CIRCUIT should be understood as the breakdown of the PN junction of the source and / or drain of the clamp circuit CLAMP CIRCUIT; the irreversible breakdown of the clamp circuit CLAMP CIRCUIT should be understood as the destruction of the gate oxide layer of the gate of the clamp circuit CLAMP CIRCUIT.

[0068] The state of bidirectional cutoff from the gate of the second driving transistor MN2 to the negative output terminal P- should be understood as: current cannot flow from the gate of the second driving transistor MN2 to the negative output terminal P-, and current cannot flow from the negative output terminal P- to the gate of the second driving transistor MN2.

[0069] When the clamp circuit CLAMP CIRCUIT is in the initial state, the gate of the second driving transistor MN2 to the negative output terminal P- is in a bidirectional cut-off state, which can avoid the backflow current flowing from the negative output terminal P- to the gate of the second driving transistor MN2 (when the potential of the negative output terminal P- is higher than the potential of the negative electrode B- of the battery, the backflow current will be generated) to cause additional leakage consumption, thereby ensuring the low energy consumption requirements of the battery protection chip under extreme working conditions.

[0070] In one embodiment, the clamp circuit CLAMP CIRCUIT comprises:

[0071] A first unidirectional conductive device coupled between the first external connection terminal A and the intermediate node C and unidirectionally conductive from the first external connection terminal to the intermediate node C; and a second unidirectional conductive device coupled between the second external connection terminal B and the intermediate node C and unidirectionally conductive from the second external connection terminal to the intermediate node C;

[0072] The first external connection terminal A is coupled to the gate of the second driving transistor MN2, and the second external connection terminal B is coupled to the negative output terminal P-.

[0073] In this embodiment, the first unidirectional conductive device and the second unidirectional conductive device are used in cooperation to clamp the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- at a predetermined voltage. At the same time, when the voltage difference between the gate of the second driving transistor MN2 and the negative output terminal P- is less than the predetermined voltage, the gate of the second driving transistor MN2 to the negative output terminal P- is in a bidirectional cut-off state.

[0074] In one embodiment, the first unidirectional conductive device is a diode, a PMOS transistor or a triode, wherein:

[0075] When the first unidirectional conducting device is a diode, the anode of the first unidirectional conducting device is coupled to the first external connection terminal A, and the cathode of the first unidirectional conducting device is coupled to the intermediate node C;

[0076] When the first unidirectional conducting device is a PMOS transistor, the source, gate and substrate of the first unidirectional conducting device are coupled to the first external connection terminal A, and the drain of the first unidirectional conducting device is coupled to the intermediate node C;

[0077] When the first unidirectional conducting device is a triode, the emitter of the first unidirectional conducting device is coupled to the first external connection terminal A, and the base and collector of the first unidirectional conducting device are coupled to the intermediate node C;

[0078] The second unidirectional conductive device is a diode, an NMOS transistor or a triode, wherein:

[0079] When the second unidirectional conducting device is a diode, an anode of the second unidirectional conducting device is coupled to the second external connection terminal B, and a cathode of the second unidirectional conducting device is coupled to the intermediate node C;

[0080] When the second unidirectional conducting device is an NMOS transistor, the source, gate and substrate of the second unidirectional conducting device are coupled to the second external connection terminal B, and the drain of the second unidirectional conducting device is coupled to the intermediate node C;

[0081] When the second unidirectional conducting device is a triode, the emitter of the second unidirectional conducting device is coupled to the second external connection terminal B, and the base and collector of the second unidirectional conducting device are coupled to the intermediate node C;

[0082] Wherein, the transistor is an NPN transistor.

[0083] For example, the specific structure of the clamp circuit CLAMP CIRCUIT can be as follows: Figure 3 As shown:

[0084] Figure 3 (1) shows the structure of the clamp circuit CLAMP CIRCUIT when the first unidirectional conducting device is a PMOS transistor MP3 and the second unidirectional conducting device is an NMOS transistor MN3;

[0085] Figure 3 (2) shows the structure of the clamp circuit CLAMP CIRCUIT when the first unidirectional conducting device is a diode D1 and the second unidirectional conducting device is an NMOS transistor MN4;

[0086] Figure 3 (3) shows the structure of the clamp circuit CLAMP CIRCUIT of D2 when the first unidirectional conducting device is a PMOS transistor MP4 and the second unidirectional conducting device is a diode;

[0087] Figure 3 (4) shows the structure of the clamp circuit CLAMP CIRCUIT when the first unidirectional conductive device is a diode D3 and the second unidirectional conductive device is a diode D4;

[0088] Figure 3 (5) shows the structure of the clamp circuit CLAMP CIRCUIT when the first unidirectional conductive device is the transistor Q1 and the second unidirectional conductive device is the transistor Q2.

[0089] In one embodiment, when the voltage difference between the source and the drain of the first driving transistor MP2 exceeds the second predetermined voltage, the source and the drain of the first driving transistor MP2 are reversibly broken down, and at this time, the second resistor R2 is used for current limiting.

[0090] Among them, the gate oxide breakdown voltage of the first driving transistor MP2 is higher than the breakdown voltage from the source to the drain of the first driving transistor MP2, and the second predetermined voltage is between the gate oxide breakdown voltage of the first driving transistor MP2 and higher than the breakdown voltage from the source to the drain of the first driving transistor MP2. Therefore, when the voltage difference between the source and the drain of the first driving transistor MP2 is too high, the high voltage will preferentially break down the PN junction of the source and the drain of the first driving transistor MP2. At this time, the source and the drain of the first driving transistor MP2 are turned on, which prevents the gate oxide layer of the first driving transistor MP2 from being broken down.

[0091] Specifically, when the PN junction of the source and drain of the first driving transistor MP2 is broken down, the second resistor R2 is used to limit the current, which can avoid the generation of strong current when the source and drain of the first driving transistor MP2 are turned on, thereby avoiding the situation where the strong current burns the source and drain PN junction of the first driving transistor MP2. Therefore, the first driving transistor MP2 will not be damaged in the case of reversible breakdown, and when the voltage difference between the source and drain of the first driving transistor MP2 drops below the second predetermined voltage, the PN junction of the source and drain of the first driving transistor MP2 can be restored from the broken down state to the normal working state.

[0092] In one embodiment, the source of the PMOS transistor MP2 is coupled to the positive electrode B+ of the battery, and the drain of the PMOS transistor MP2 is coupled to the driving output terminal CO;

[0093] The source of the NMOS transistor MN2 is coupled to the negative output terminal P-, and the drain of the NMOS transistor MN2 is coupled to the driving output terminal CO;

[0094] The first driving transistor MP2 and the second driving transistor MN2 are manufactured using the same gate process as other MOS transistors in the protection driving circuit, so that the gate oxide breakdown voltage of the first driving transistor MP2 and the second driving transistor MN2 is equal to the gate oxide breakdown voltage of other MOS transistors.

[0095] It should be understood that the gate oxide breakdown voltage of the first driver transistor MP2 and the second driver transistor MN2 is equal to the gate oxide breakdown voltage of other MOS transistors. It should be understood that the difference between the actual gate oxide breakdown voltage of the first driver transistor MP2 and the second driver transistor MN2 and the actual gate oxide breakdown voltage from gate to source of other MOS transistors is less than or equal to the set error threshold.

[0096] In this embodiment, the above-mentioned setting is used to unify the gate process requirements of each MOS transistor in the protection drive circuit, so that the gate oxide breakdown voltage of each MOS transistor in the protection drive circuit tends to be consistent, thereby ensuring that the process design of each MOS transistor in the protection drive circuit to avoid irreversible breakdown by reversible breakdown can be achieved, thereby reducing the probability of irreversible breakdown of the MOS transistor in the protection drive circuit and extending the service life of the protection drive circuit.

[0097] At this time, when the clamp circuit CLAMP CIRCUIT includes a MOS transistor, the other MOS transistor may be understood as the MOS transistor included in the clamp circuit CLAMP CIRCUIT.

[0098] In one embodiment, the protection driving circuit further includes:

[0099] A PMOS transistor MP1, wherein the gate of the PMOS transistor MP1 is coupled to the digital input terminal C_CTRL, the source of the PMOS transistor MP1 is coupled to the positive electrode B+ of the battery, and the drain of the PMOS transistor MP1 is coupled to the control input terminal C_PRE, wherein the digital input terminal is used to receive a digital signal, and the aforementioned control signal is formed based on the digital signal;

[0100] an NMOS transistor MN1, wherein a gate of the NMOS transistor MN1 is coupled to the digital input terminal C_CTRL, a source of the PMOS transistor MP1 is coupled to the negative electrode B- of the battery, and a drain of the PMOS transistor MP1 is coupled to the control input terminal C_PRE;

[0101] The first driver transistor MP2 and the second driver transistor MN2 are manufactured using the same gate process as the MOS transistors MN1 and MP1, so that the gate oxide breakdown voltage of the first driver transistor MP2 and the second driver transistor MN2 is equal to the gate-to-source breakdown voltage of the MOS transistors MN1 and MP1.

[0102] The other MOS transistors include a PMOS transistor MP1 and an NMOS transistor MN1 .

[0103] In one embodiment, the predetermined voltage is greater than or equal to 6V, and the predetermined voltage is less than or equal to 10V.

[0104] The battery may be understood as a low-voltage battery with an output voltage less than or equal to 5V.

[0105] In the present invention, words such as "connect", "connected", "connect", "connected", "coupled", etc., which indicate electrical connection, indicate direct or indirect electrical connection unless otherwise specified. The direct electrical connection indicates a direct connection between two or more objects without any intervening objects, and the indirect electrical connection indicates a connection between two or more objects with one or more objects (such as electrical components or electrical units such as resistors, capacitors, inductors, switches, filters, etc.) intervening.

[0106] The terms "comprises," "comprising," or any other variations thereof of the disclosed embodiments are intended to encompass non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0107] The term "or" in the present disclosure means an inclusive "or" rather than an exclusive "or". The mention of a "first" component does not necessarily require the provision of a "second" component. In addition, unless explicitly indicated, the "first" or "second" component does not mean that the mentioned components are limited to a specific order.

[0108] The embodiments of the present disclosure are described above in conjunction with the accompanying drawings, but the present disclosure is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present disclosure, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present disclosure and the claims, all of which are within the protection of the present disclosure.

Claims

1. A protection drive circuit for a battery system, characterized in that: The protection driving circuit comprises: A first driving transistor and a second resistor are connected in series between the positive electrode of the battery and the driving output terminal, wherein the gate of the first driving transistor is coupled to the control input terminal, and the control input terminal is used to receive a control signal; A second driving transistor connected in series between the driving output terminal and the negative output terminal; A first resistor connected in series between the gate of the second driving transistor and the control input terminal; A clamping circuit is coupled between the gate of the second driving transistor and the negative output terminal, and the clamping circuit is used to clamp the voltage difference between the gate of the second driving transistor and the negative output terminal within a predetermined voltage.

2. The protection driving circuit according to claim 1, characterized in that: The high level of the control signal is the voltage of the positive electrode of the battery, and the low level of the control signal is the voltage of the negative electrode of the battery; When the control signal is at a low level, the first driving transistor is turned on, the second driving transistor is turned off, the driving signal output by the driving output terminal is at a high level, and the high level of the driving signal is the voltage of the positive electrode of the battery; When the control signal is at a high level, the first driving transistor is turned off, the second driving transistor is turned on, the driving signal output by the driving output terminal is at a low level, and the low level of the driving signal is the voltage of the cathode output terminal.

3. The protection driving circuit according to claim 1, characterized in that: When the voltage difference between the gate of the second driving transistor and the negative output terminal is greater than or equal to the predetermined voltage, the clamping circuit is reversibly broken down to clamp the voltage difference between the gate of the second driving transistor and the negative output terminal at the predetermined voltage; When the voltage difference between the gate of the second driving transistor and the negative output terminal is less than the predetermined voltage, the clamp circuit returns to an initial state. When the clamp circuit is in the initial state, the gate of the second driving transistor to the negative output terminal is in a bidirectional cutoff state.

4. The protection driving circuit according to claim 3, characterized in that: The clamping circuit comprises: A first unidirectional conductive device coupled between the first external connection terminal and the intermediate node C and unidirectionally conductive from the first external connection terminal to the intermediate node C; and a second unidirectional conductive device coupled between the second external connection terminal and the intermediate node C and unidirectionally conductive from the second external connection terminal to the intermediate node C; The first external connection terminal is coupled to the gate of the second driving transistor, and the second external connection terminal is coupled to the negative output terminal.

5. The protection driving circuit according to claim 4, characterized in that: The first unidirectional conductive device is a diode, a PMOS transistor or a triode, wherein: When the first unidirectional conducting device is a diode, the anode of the first unidirectional conducting device is coupled to the first external connection terminal, and the cathode of the first unidirectional conducting device is coupled to the intermediate node C; When the first unidirectional conducting device is a PMOS transistor, the source, gate and substrate of the first unidirectional conducting device are coupled to the first external connection terminal, and the drain of the first unidirectional conducting device is coupled to the intermediate node C; When the first unidirectional conducting device is a triode, the emitter of the first unidirectional conducting device is coupled to the first external connection terminal, and the base and collector of the first unidirectional conducting device are coupled to the intermediate node C; The second unidirectional conductive device is a diode, an NMOS transistor or a triode, wherein: When the second unidirectional conducting device is a diode, an anode of the second unidirectional conducting device is coupled to the second external connection terminal, and a cathode of the second unidirectional conducting device is coupled to the intermediate node C; When the second unidirectional conducting device is an NMOS transistor, the source, gate and substrate of the second unidirectional conducting device are coupled to the second external connection terminal, and the drain of the second unidirectional conducting device is coupled to the intermediate node C; When the second unidirectional conducting device is a triode, the emitter of the second unidirectional conducting device is coupled to the second external connection terminal, and the base and collector of the second unidirectional conducting device are coupled to the intermediate node C; Wherein, the transistor is an NPN transistor.

6. The protection driving circuit according to claim 1, characterized in that: When the voltage difference between the source and the drain of the first driving transistor exceeds the second predetermined voltage, the source and the drain of the first driving transistor are reversibly broken down.

7. The protection driving circuit according to claim 2, characterized in that: The driving signal is a charging driving signal, and the driving output terminal is coupled to the control terminal of the charging power switch. The source and substrate of the charging power switch are coupled to the negative output terminal, When the charging drive signal is at a high level, the charging power switch is turned on, and when the charging drive signal is at a low level, the charging power switch is turned off.

8. The protection driving circuit according to claim 1, characterized in that: The first driving transistor is a PMOS transistor MP2, a source of the PMOS transistor MP2 is coupled to the positive electrode of the battery, and a drain of the PMOS transistor MP2 is coupled to the driving output terminal; The second driving transistor is an NMOS transistor MN2, the source of the NMOS transistor MN2 is coupled to the negative output terminal, the drain of the NMOS transistor MN2 is coupled to the driving output terminal, The first driving transistor and the second driving transistor are manufactured using the same gate process as other MOS transistors in the protection driving circuit, so that the gate oxide breakdown voltage of the first driving transistor and the second driving transistor is equal to the gate oxide breakdown voltage of other MOS transistors.

9. The protection driving circuit according to claim 8, characterized in that: The protection driving circuit also includes: A PMOS transistor MP1, wherein a gate of the PMOS transistor MP1 is coupled to a digital input terminal, a source of the PMOS transistor MP1 is coupled to a positive electrode of a battery, a drain of the PMOS transistor MP1 is coupled to the control input terminal, and the digital input terminal is used to receive a digital signal; an NMOS transistor MN1, wherein a gate of the NMOS transistor MN1 is coupled to the digital input terminal, a source of the PMOS transistor MP1 is coupled to the negative electrode of the battery, and a drain of the PMOS transistor MP1 is coupled to the control input terminal; The first driving transistor and the second driving transistor are manufactured using the same gate process as the MOS transistors MN1 and MP1, so that the gate oxide breakdown voltage of the first driving transistor and the second driving transistor is equal to the gate oxide breakdown voltage of the MOS transistors MN1 and MP1.

10. The protection driving circuit according to claim 1, characterized in that: The predetermined voltage is greater than or equal to 6V, and the predetermined voltage is less than or equal to 10V.

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