Solar photovoltaic inverter, driving method and driving circuit

Abstract

The invention discloses a solar photovoltaic inverter, a driving method and a driving circuit, and belongs to the technical field of inverters, the solar photovoltaic inverter comprises a signal input circuit, the signal input circuit comprises an NAND gate U1, the first input end and the second input end of the NAND gate U1 are connected with an SPWM input pin, and the output end of the NAND gate U1 is connected with a dead time setting circuit; the dead time setting circuit is used for setting dead time between upper and lower bridge arms of an inverter H bridge in the full-bridge inverter driving circuit; the fault protection circuit is used for outputting a low-level signal when a fault signal is detected; the transformer pulse drive generation circuit is used for receiving the SPWM signal and generating a low-voltage signal; the transformer driving circuit is used for receiving the low-voltage signal and boosting the low-voltage signal to obtain a driving signal; and the full-bridge inverter driving circuit is used for receiving the driving signal to control the on-off of the power switch element. According to the invention, a pure hardware circuit is adopted to modulate an inversion control signal into a driving signal of the inversion H bridge, and the inverter has a protection function and is low in cost and high in response speed.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to a solar photovoltaic inverter, a driving method and a driving circuit. Background Art

[0002] With the development of electronic technology, inverter modules are used more and more widely, especially in frequency converters and inverter products, where inverter modules are essential core components. Inverter circuit is a basic chopper circuit that can convert DC into AC. It is mainly used in industrial applications such as AC power supplies and inverters. If there is an abnormality in the inverter module, such product is almost equivalent to a scrap product and cannot achieve its intended function. Therefore, the drive and protection circuits of the inverter module have received due attention in the design of frequency converter products.

[0003] At present, most of the inverter drives based on SWPM bipolar control are driven and controlled by MCU or DSP. Due to the long software delay time and lack of fast shutdown protection, the drive cannot be shut down in time and effectively, which can easily lead to direct conduction of the upper and lower bridge arms of the inverter IGBT module and cause fault damage. Summary of the invention

[0004] To solve the above problems, the present invention provides a solar photovoltaic inverter, a driving method and a driving circuit, which adopts a pure hardware circuit to modulate the inverter control signal into a driving signal of an inverter H-bridge and has a protection function, with low cost and fast response speed.

[0005] The above objectives can be achieved through the following solutions: A driving circuit of a solar photovoltaic inverter comprises: a signal input circuit, a driving signal modulation circuit and a full-bridge inverter driving circuit, wherein the driving signal modulation circuit comprises a dead time setting circuit, a fault protection circuit, a transformer pulse drive generating circuit and a transformer driving circuit; wherein the signal input circuit comprises a NAND gate U1, wherein the first input terminal and the second input terminal of the NAND gate U1 are both connected to an SPWM input pin, and the output terminal of the NAND gate U1 is connected to the dead time setting circuit; the dead time setting circuit is connected to the fault protection circuit and is used to set the inverter in the full-bridge inverter driving circuit. The dead time between the upper and lower arms of the H-bridge; the fault protection circuit is connected to the transformer pulse drive generation circuit, and is used to output a low-level signal when a fault signal is detected; the transformer pulse drive generation circuit is connected to the dead time setting circuit, and is used to receive the SPWM signal to generate a low-voltage signal; the transformer drive circuit is connected to the transformer pulse drive generation circuit, and is used to receive the low-voltage signal and boost the low-voltage signal to obtain a drive signal; the full-bridge inverter drive circuit is connected to the transformer drive circuit, and is used to receive the drive signal to control the on and off of the power switch element.

[0006] Furthermore, the dead time setting circuit includes a resistor R1 and a capacitor C1; wherein the output end of the resistor R1 is respectively connected to the input end of the capacitor C1 and the first input end of the transformer pulse drive generating circuit, and the input end of the resistor R1 is respectively connected to the output end of the NAND gate U1 and the second input end of the transformer pulse drive generating circuit; the output end of the capacitor C1 is grounded.

[0007] Further, the transformer pulse drive generating circuit includes a pulse generating subcircuit, and the pulse generating subcircuit includes an inverter U2, an inverter U3, a NAND gate U4, an inverter U5, an inverter U6, a NAND gate U7, an inverter U8, an inverter U9, a NAND gate U10, an inverter U11, an inverter U12, a NAND gate U13 and an inverter U14; wherein, the input end of the inverter U2 is connected to the output end of the resistor R1, the output end of the inverter U2 is connected to the first input end of the NAND gate U4, the second input end of the NAND gate U4 is connected to the output end of the inverter U3, the output end of the NAND gate U4 is connected to the input end of the inverter U5, and the output end of the inverter U5 is connected to the transformer driving circuit; the output end of the inverter U3 is connected to the first input end of the NAND gate U7, the NAND gate U7 is connected to the first input end of the NAND gate U7, and the NAND gate U7 is connected to the second input end of the NAND gate U4. The second input terminal is connected to the output terminal of the inverter U6, the output terminal of the NAND gate U7 is connected to the input terminal of the inverter U8, and the output terminal of the inverter U8 is connected to the transformer driving circuit; the first input terminal of the NAND gate U10 is connected to the input terminal of the resistor R1, the second input terminal of the NAND gate U10 is connected to the output terminal of the inverter U9, the output terminal of the NAND gate U10 is connected to the input terminal of the inverter U11, and the output terminal of the inverter U11 is connected to the transformer driving circuit; the output terminal of the inverter U9 is connected to the first input terminal of the NAND gate U13, the second input terminal of the NAND gate U13 is connected to the output terminal of the inverter U12, the output terminal of the NAND gate U13 is connected to the input terminal of the inverter U14, and the output terminal of the inverter U14 is connected to the transformer driving circuit.

[0008] Furthermore, the transformer pulse drive generation circuit also includes a pulse width modulation subcircuit, which includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2, a diode D3 and a diode D4; wherein the input end of the resistor R2 is respectively connected to the output end of the inverter U2 and the output end of the diode D1, the output end of the resistor R2 is respectively connected to the input end of the inverter U3, the input end of the capacitor C2 and the input end of the diode D1, and the output end of the capacitor C2 is grounded; the input end of the resistor R3 is respectively connected to the output end of the inverter U3 and the output end of the diode D2, and the output end of the resistor R3 is connected to the ground. The ends are respectively connected to the input end of the inverter U6, the input end of the capacitor C2 and the input end of the diode D2, and the output end of the capacitor C3 is grounded; the input end of the resistor R4 is respectively connected to the input end of the resistor R1 and the output end of the diode D3, the output end of the resistor R4 is respectively connected to the input end of the inverter U9, the input end of the capacitor C4 and the input end of the diode D3, and the output end of the capacitor C4 is grounded; the input end of the resistor R5 is respectively connected to the output end of the inverter U9 and the output end of the diode D4, the output end of the resistor R5 is respectively connected to the input end of the inverter U12, the input end of the capacitor C5 and the input end of the diode D4, and the output end of the capacitor C5 is grounded.

[0009] Furthermore, the fault protection circuit includes a NAND gate U15, an inverter U16, a NAND gate U17 and an inverter U18; wherein, the first input end of the NAND gate U15 is connected to the output end of the inverter U5, the second input end of the NAND gate U15 is connected to the fault signal output pin, the output end of the NAND gate U15 is connected to the input end of the inverter U16, and the output end of the inverter U16 is connected to the transformer drive circuit; the first input end of the NAND gate U17 is connected to the fault signal output pin, the second input end of the NAND gate U17 is connected to the output end of the inverter U8, the output end of the NAND gate U17 is connected to the input end of the inverter U18, and the output end of the inverter U18 is connected to the transformer drive circuit.

[0010] Further, the transformer drive circuit includes a push-pull drive sub-circuit P1, a push-pull drive sub-circuit P2, a push-pull drive sub-circuit P3, a push-pull drive sub-circuit P4, a capacitor C6, a capacitor C7, a transformer T1 and a transformer T2; wherein the input end of the push-pull drive sub-circuit P1 is connected to the output end of the inverter U11, the output end of the push-pull drive sub-circuit P1 is connected to the input end of the capacitor C6, and the output end of the capacitor C6 is connected to the positive access point of the low-voltage side of the transformer T1; the input end of the push-pull drive sub-circuit P2 is connected to the output end of the inverter U16, and the output end of the push-pull drive sub-circuit P2 is connected to the positive access point of the low-voltage side of the transformer T1. The negative access point of the low-voltage side of the transformer T1 is connected; the high-voltage side of the transformer T1 is connected to the full-bridge inverter drive circuit; the input end of the push-pull drive sub-circuit P3 is connected to the output end of the inverter U14, the output end of the push-pull drive sub-circuit P3 is connected to the input end of the capacitor C7, and the output end of the capacitor C7 is connected to the positive access point of the low-voltage side of the transformer T2; the input end of the push-pull drive sub-circuit P4 is connected to the output end of the inverter U18, and the output end of the push-pull drive sub-circuit P4 is connected to the negative access point of the low-voltage side of the transformer T1; the high-voltage side of the transformer T2 is connected to the full-bridge inverter drive circuit.

[0011] Furthermore, the full-bridge inverter drive circuit includes: transistor Q_H1, transistor Q_H2, transistor Q_L1 and transistor Q_L2; wherein the gate of the transistor Q_H1, the gate of the transistor Q_H2, the gate of the transistor Q_L1 and the gate of the transistor Q_L2 are all connected to a control circuit.

[0012] Further, the control circuit includes a first control subcircuit, a second control subcircuit, a third control subcircuit and a fourth control subcircuit; wherein the first control subcircuit includes a transistor Q1, a transistor Q2, a capacitor C8, a resistor R6 and a resistor R7; the source of the transistor Q1 is connected to the positive access point H1 on the high voltage side of the transformer T1, the drain of the transistor Q1 is respectively connected to the gate of the transistor Q2 and the input end of the resistor R6, the output end of the resistor R6 is respectively connected to the input end of the capacitor C8, the input end of the resistor R7, and the gate of the transistor Q_H1, the drain of the transistor Q2 is respectively connected to the input end of the capacitor C8, the input end of the resistor R7, and the gate of the transistor Q_H1, and the drain of the transistor Q1 is respectively connected to the input end of the capacitor C8, the input end of the resistor R7, and the gate of the transistor Q_H1. The source is respectively connected to the negative access point H1 of the high-voltage side of the transformer T1 and the gate of the transistor Q1, and the drain of the transistor Q2 is respectively connected to the output end of the capacitor C8, the output end of the resistor R7, and the emitter of the transistor Q_H1; the second control subcircuit includes a transistor Q3, a transistor Q4, a capacitor C9, a resistor R8 and a resistor R9; the source of the transistor Q3 is connected to the positive access point H2 of the high-voltage side of the transformer T2, the drain of the transistor Q3 is respectively connected to the gate of the transistor Q4 and the input end of the resistor R8, and the output end of the resistor R8 is respectively connected to the output end of the capacitor C9. The input end, the input end of the resistor R9, and the gate of the transistor Q_H2 are connected, the source of the transistor Q4 is respectively connected to the negative access point H2 on the high-voltage side of the transformer T2 and the gate of the transistor Q3, and the drain of the transistor Q4 is respectively connected to the output end of the capacitor C9, the output end of the resistor R9, and the emitter of the transistor Q_H2; the third control subcircuit includes a transistor Q5, a transistor Q6, a capacitor C10, a resistor R10 and a resistor R11; the source of the transistor Q5 is connected to the positive access point L1 on the high-voltage side of the transformer T2, and the drain of the transistor Q5 is respectively connected to the output end of the capacitor C9, the output end of the resistor R9, and the emitter of the transistor Q_H2. The gate of the transistor Q6 is connected to the input end of the resistor R10, the output end of the resistor R10 is respectively connected to the input end of the capacitor C10, the input end of the resistor R11, and the gate of the transistor Q_L1, the source of the transistor Q6 is respectively connected to the negative access point L1 of the high voltage side of the transformer T2 and the gate of the transistor Q5, and the drain of the transistor Q6 is respectively connected to the output end of the capacitor C10, the output end of the resistor R11, and the emitter of the transistor Q_L1; the fourth control subcircuit includes a transistor Q7, a transistor Q8, a capacitor C11, a resistor R12, and a resistor R13;The source of the transistor Q7 is connected to the positive access point of the high-voltage side L2 of the transformer T1, the drain of the transistor Q7 is respectively connected to the gate of the transistor Q8 and the input end of the resistor R12, the output end of the resistor R12 is respectively connected to the input end of the capacitor C11, the input end of the resistor R13, and the gate of the transistor Q_L2, the source of the transistor Q8 is respectively connected to the negative access point of the high-voltage side L2 of the transformer T1 and the gate of the transistor Q7, and the drain of the transistor Q8 is respectively connected to the output end of the capacitor C11, the output end of the resistor R13, and the emitter of the transistor Q_L2. ;

[0013] Based on the same inventive concept, the present invention also provides a driving method for a solar photovoltaic inverter, the method comprising: receiving an SPWM signal; modulating the SPWM signal to generate a low-voltage signal and boosting the voltage thereof to obtain a driving signal; controlling the on and off of transistors Q_H1, Q_H2, Q_L1, and Q_L2 according to the driving signal to convert DC power into AC power; and outputting a low-level signal to turn off the driving signal when a fault signal is detected.

[0014] Based on the same inventive concept, the present invention also provides a solar photovoltaic inverter, wherein the inverter comprises a driving circuit as described in any one of the above items, and is used for converting direct current power into alternating current power.

[0015] Compared with the prior art, the present invention has the following advantages: 1. By setting the dead time, the power switch elements of the upper and lower bridge arms of the inverter H bridge in the full-bridge inverter drive circuit are effectively prevented from being turned on at the same time, thereby avoiding the occurrence of short circuit and improving the stability of the system; the fault protection circuit can respond quickly when detecting fault signals such as overheating, overcurrent, and overvoltage, and output a low-level signal to turn off the drive signal, effectively protecting the circuit elements from damage and enhancing the reliability of the system; 2. The drive circuit and optimization design method adopted by the present invention reduce the energy loss in the conversion process, thereby improving the energy conversion efficiency; through precise pulse width modulation technology and reasonable circuit layout, the inverter can more efficiently convert DC power into AC power when working; 3. The transformer drive circuit of the present invention can boost the low-voltage pulse signal into a high-voltage signal suitable for driving the power switching element, thereby enhancing the driving ability of the drive circuit; the full-bridge inverter drive circuit adopts high-performance power switching elements and optimized control strategies, so that the inverter can handle larger currents and voltages to meet the needs of different loads.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a framework diagram of a driving circuit of a solar photovoltaic inverter according to an embodiment of the present invention.

[0019] Figure 2 The present invention is a schematic diagram of a solar photovoltaic inverter driving circuit according to an embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the circuit structure of the driving signal modulation circuit according to an embodiment of the present invention.

[0021] Figure 4 Schematic diagram of the circuit structure of a full-bridge inverter drive circuit according to an embodiment of the present invention.

[0022] Figure 5 It is a schematic flow chart of a driving method of a solar photovoltaic inverter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Reference Figure 1 An embodiment of the present invention proposes a driving circuit for a solar photovoltaic inverter, which uses a pure hardware circuit to modulate an inverter control signal into a driving signal for an inverter H-bridge and has a protection function, with low cost and fast response speed.

[0025] The driving circuit of this embodiment specifically includes: like Figure 2As shown, the signal input circuit, the drive signal modulation circuit, the full-bridge inverter drive circuit, the drive signal modulation circuit includes a dead time setting circuit, a fault protection circuit, a transformer pulse drive generation circuit, and a transformer drive circuit; wherein, The signal input circuit comprises a NAND gate U1, wherein the first input terminal and the second input terminal of the NAND gate U1 are both connected to the SPWM input pin, and the output terminal of the NAND gate U1 is connected to the dead time setting circuit; Specifically, the signal input circuit is mainly composed of NAND gate U1; NAND gate U1 receives the signal from the SPWM (sinusoidal pulse width modulation) input pin. Since both input ends of NAND gate U1 are connected to the SPWM input pin, when the SPWM signal is high, NAND gate U1 outputs a low level; when the SPWM signal is low, NAND gate U1 outputs a high level. In this way, NAND gate U1 performs logical processing on the SPWM signal.

[0026] For example, assuming that the SPWM signal is a periodic square wave signal, when the square wave signal is at a high level, the NAND gate U1 outputs a low level; when the square wave signal is at a low level, the NAND gate U1 outputs a high level. In this way, the NAND gate U1 converts the SPWM signal into another form of logic signal and transmits it to the subsequent dead time setting circuit.

[0027] A dead time setting circuit is connected to the fault protection circuit and is used to set the dead time between the upper and lower bridge arms of the inverter H bridge in the full-bridge inverter drive circuit; Specifically, a signal from a signal input circuit is received, and a dead time between upper and lower bridge arms of an inverter H-bridge in a full-bridge inverter drive circuit is set; the dead time is set to prevent power switch elements of the upper and lower bridge arms from being turned on at the same time, thereby causing a short circuit.

[0028] A fault protection circuit is connected to the transformer pulse drive generating circuit and is used to output a low level signal when a fault signal is detected; Specifically, the operating status of the circuit is monitored. When fault signals such as overheating, overcurrent, and overvoltage are detected, a low-level signal is output to the transformer pulse drive generation circuit to cut off the drive signal to the power switching element to protect the circuit from damage.

[0029] A transformer pulse drive generating circuit is connected to the dead time setting circuit and is used to receive the SPWM signal to generate a low voltage signal; Specifically, an SPWM signal that has been processed with dead time setting and fault protection is received to generate a low-voltage pulse drive signal.

[0030] The transformer driving circuit is connected to the transformer pulse driving generating circuit, and is used to receive the low voltage signal and boost the low voltage signal to obtain the driving signal; Specifically, a low-voltage pulse drive signal output by a transformer pulse drive generation circuit is received and boosted to a high-voltage signal suitable for driving a power switch element.

[0031] For example, assuming that at a certain moment, the fault protection circuit detects an overcurrent condition in the circuit, the fault protection circuit will immediately output a low-level signal to the transformer pulse drive generation circuit; after the transformer pulse drive generation circuit receives the low-level signal, it will stop generating a low-voltage pulse drive signal, thereby making it impossible for the transformer drive circuit to output a high-voltage drive signal to the power switching element, thereby achieving the purpose of protecting the circuit.

[0032] The full-bridge inverter drive circuit is connected to the transformer drive circuit and is used to receive a drive signal to control the on and off of the power switch element.

[0033] Specifically, the full-bridge inverter drive circuit is an H-bridge circuit composed of four power switching elements (such as MOSFET or IGBT); the full-bridge inverter drive circuit receives a high-voltage drive signal from a transformer drive circuit, controls the on and off of the power switching elements in the H-bridge circuit, and thus converts DC power into AC output.

[0034] Exemplarily, when the transformer drive circuit outputs a high-voltage drive signal to the full-bridge inverter drive circuit, the power switch element in the full-bridge inverter drive circuit will be switched on and off according to the waveform and frequency of the drive signal; for example, when the drive signal is at a high level, the corresponding power switch element is turned on; when the drive signal is at a low level, the corresponding power switch element is turned off; through such on-off switching, the full-bridge inverter drive circuit can convert the input DC power into AC power output.

[0035] Furthermore, if Figure 3 As shown, the dead time setting circuit includes a resistor R1 and a capacitor C1; wherein, The output end of the resistor R1 is connected to the input end of the capacitor C1 and the first input end of the transformer pulse drive generating circuit respectively, and the input end of the resistor R1 is connected to the output end of the NAND gate U1 and the second input end of the transformer pulse drive generating circuit respectively; the output end of the capacitor C1 is grounded.

[0036] Specifically, the dead time setting circuit is mainly composed of a resistor R1 and a capacitor C1. The main function of the dead time setting circuit is to set a specific time interval (i.e., dead time) to prevent the upper and lower bridge arms of the inverter H bridge in the full-bridge inverter drive circuit from being turned on at the same time. This is achieved through an RC circuit composed of a resistor R1 and a capacitor C1.

[0037] For example, when the NAND gate U1 outputs a high level (assuming that the SPWM signal is a low level at this time), the current charges the capacitor C1 through the resistor R1; due to the charging characteristics of the capacitor, the voltage on the capacitor C1 will gradually rise, but this process takes a certain amount of time, which constitutes a part of the dead time; when the NAND gate U1 outputs a low level (assuming that the SPWM signal is a high level at this time), the capacitor C1 begins to discharge, but because the discharge speed of the capacitor is relatively slow, the voltage on the capacitor C1 remains at a certain level for a period of time (i.e., during the dead time), which is sufficient to ensure that the upper and lower bridge arms of the inverter H bridge will not be turned on at the same time; by adjusting the values ​​of the resistor R1 and the capacitor C1, the length of the dead time can be accurately controlled. For example, increasing the value of the resistor R1 or the capacitor C1 will increase the charging and discharging time, thereby extending the dead time; conversely, it will shorten the dead time.

[0038] Furthermore, if Figure 3 As shown, the transformer pulse drive generating circuit includes a pulse generating subcircuit, and the pulse generating subcircuit includes an inverter U2, an inverter U3, a NAND gate U4, an inverter U5, an inverter U6, a NAND gate U7, an inverter U8, an inverter U9, a NAND gate U10, an inverter U11, an inverter U12, a NAND gate U13, and an inverter U14; wherein, The input end of the inverter U2 is connected to the output end of the resistor R1, the output end of the inverter U2 is connected to the first input end of the NAND gate U4, the second input end of the NAND gate U4 is connected to the output end of the inverter U3, the output end of the NAND gate U4 is connected to the input end of the inverter U5, and the output end of the inverter U5 is connected to the transformer driving circuit; the output end of the inverter U3 is connected to the first input end of the NAND gate U7, the second input end of the NAND gate U7 is connected to the output end of the inverter U6, the output end of the NAND gate U7 is connected to the input end of the inverter U8, and the output end of the inverter U8 is connected to the transformer driving circuit; A first input terminal of the NAND gate U10 is connected to an input terminal of the resistor R1, a second input terminal of the NAND gate U10 is connected to an output terminal of the inverter U9, an output terminal of the NAND gate U10 is connected to an input terminal of the inverter U11, and an output terminal of the inverter U11 is connected to a transformer driving circuit; an output terminal of the inverter U9 is connected to a first input terminal of the NAND gate U13, a second input terminal of the NAND gate U13 is connected to an output terminal of the inverter U12, an output terminal of the NAND gate U13 is connected to an input terminal of the inverter U14, and an output terminal of the inverter U14 is connected to a transformer driving circuit.

[0039] Specifically, the pulse generation subcircuit is composed of a plurality of inverters (U2, U3, U5, U8, U9, U11, U12, U14) and NAND gates (U4, U7, U10, U13); the main function of the pulse generation subcircuit is to generate a series of low-voltage pulse signals according to the input signal (including the signal processed by the dead time setting circuit and other possible signals); these pulse signals are logically processed by the inverters and NAND gates, and have specific waveform and timing characteristics to meet the requirements of the transformer drive circuit for the drive signal.

[0040] Exemplarily, it is assumed that at a certain moment, the dead time setting circuit outputs a high level signal to the input end of the inverter U2; due to the action of the inverter, the output end of U2 will output a low level signal to the first input end of the NAND gate U4; at the same time, it is assumed that the input end of the inverter U3 receives a low level signal (or a fixed low level), and its output end will output a high level signal to the second input end of the NAND gate U4; according to the logical characteristics of the NAND gate (outputting a low level when and only when all inputs are high levels), the NAND gate U4 will output a low level signal to the input end of the inverter U5; the inverter U5 then inverts the low level signal into a high level signal and outputs it to the transformer drive circuit; in this process, the inverters U2, U3, U5 and the NAND gate U4 work together to realize the logical processing of the input signal and the generation of the pulse signal; similarly, the combination of other inverters and NAND gates also generates corresponding pulse signals according to their respective input signals and logical characteristics and outputs them to the transformer drive circuit.

[0041] Furthermore, if Figure 3 As shown, the transformer pulse drive generation circuit also includes a pulse width modulation subcircuit, which includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2, a diode D3, and a diode D4; wherein, The input end of the resistor R2 is connected to the output end of the inverter U2 and the output end of the diode D1 respectively, the output end of the resistor R2 is connected to the input end of the inverter U3, the input end of the capacitor C2 and the input end of the diode D1 respectively, and the output end of the capacitor C2 is grounded; the input end of the resistor R3 is connected to the output end of the inverter U3 and the output end of the diode D2 respectively, the output end of the resistor R3 is connected to the input end of the inverter U6, the input end of the capacitor C2 and the input end of the diode D2 respectively, and the output end of the capacitor C3 is grounded; The input end of the resistor R4 is respectively connected to the input end of the resistor R1 and the output end of the diode D3, the output end of the resistor R4 is respectively connected to the input end of the inverter U9, the input end of the capacitor C4 and the input end of the diode D3, and the output end of the capacitor C4 is grounded; the input end of the resistor R5 is respectively connected to the output end of the inverter U9 and the output end of the diode D4, the output end of the resistor R5 is respectively connected to the input end of the inverter U12, the input end of the capacitor C5 and the input end of the diode D4, and the output end of the capacitor C5 is grounded.

[0042] Specifically, the pulse width modulation subcircuit includes resistors R2, R3, R4, R5, capacitors C2, C3, C4, C5, and diodes D1, D2, D3, D4; the main function of the pulse width modulation subcircuit is to perform pulse width modulation processing on the input signal; by adjusting the resistance and capacitance values ​​in the RC charge and discharge loop, the charge and discharge time constant of the signal can be changed, thereby affecting the pulse width of the output signal; this pulse width modulation technology is widely used in the fields of power electronics and automation control to achieve efficient conversion of voltage and current.

[0043] By way of example, it is assumed that at a certain moment, the inverter U2 outputs a high-level signal, which charges the capacitor C2 through the resistor R2; due to the charging characteristics of the capacitor, the voltage on the capacitor C2 will gradually rise, and this rising process determines the rising edge of the output signal and a part of the pulse width; when the output of the inverter U2 becomes a low level, the capacitor C2 begins to discharge through the resistor R2 and the diode D1; the discharge process determines the falling edge of the output signal and another part of the pulse width; by adjusting the values ​​of the resistor R2 and the capacitor C2, the time constant of charging and discharging can be controlled, thereby achieving precise control of the pulse width of the output signal; similarly, other RC charging and discharging loops (composed of resistors R3, R4, R5 and capacitors C3, C4, C5) also perform charging and discharging processes according to their respective input signals to generate output signals with specific pulse widths; these pulse-width modulated signals will be used together with signals generated by other circuit parts (such as the pulse generation subcircuit) as input signals of the transformer drive circuit, and ultimately drive the power switch element on and off.

[0044] Furthermore, if Figure 3 As shown, the fault protection circuit includes a NAND gate U15, an inverter U16, a NAND gate U17, and an inverter U18; wherein, A first input end of the NAND gate U15 is connected to an output end of the inverter U5, a second input end of the NAND gate U15 is connected to a fault signal output pin, an output end of the NAND gate U15 is connected to an input end of the inverter U16, and an output end of the inverter U16 is connected to a transformer driving circuit; The first input of NAND gate U17 is connected to the fault signal output pin, the second input of NAND gate U17 is connected to the output of inverter U8, the output of NAND gate U17 is connected to the input of inverter U18, and the output of inverter U18 is connected to the transformer driving circuit.

[0045] Specifically, the fault protection circuit includes NAND gates U15 and U17, and inverters U16 and U18; the main function of the fault protection circuit is to quickly cut off or adjust the output signal of the transformer drive circuit when a fault signal is detected to protect other components in the circuit from damage.

[0046] For example, suppose that during the operation of the circuit, due to some reason (such as overcurrent, overvoltage, overheating, etc.), the fault signal output pin is set to a high level, indicating that a fault is detected; at this time, if the output end of the inverter U5 is also at a high level (this depends on the working state of the pulse generating subcircuit), the NAND gate U15 will output a low level signal to the inverter U16; the inverter U16 then inverts the low level signal into a high level signal, but this high level signal may be a fault protection signal, used to instruct the transformer drive circuit to stop working or switch to a safe state; similarly, if the output end of the inverter U8 is also at a high level (this depends on the working state of another part of the pulse generating subcircuit), the NAND gate U17 will also output a low level signal to the inverter U18; the inverter U18 then inverts the low level signal into a high level signal, and also outputs it to the transformer drive circuit as a fault protection signal; in this way, the fault protection circuit can respond quickly when a fault is detected to protect the safe operation of the entire circuit system.

[0047] Furthermore, if Figure 3 As shown, the transformer driving circuit includes a push-pull driving sub-circuit P1, a push-pull driving sub-circuit P2, a push-pull driving sub-circuit P3, a push-pull driving sub-circuit P4, a capacitor C6, a capacitor C7, a transformer T1, and a transformer T2; wherein, The input end of the push-pull drive sub-circuit P1 is connected to the output end of the inverter U11, the output end of the push-pull drive sub-circuit P1 is connected to the input end of the capacitor C6, and the output end of the capacitor C6 is connected to the positive access point on the low-voltage side of the transformer T1; the input end of the push-pull drive sub-circuit P2 is connected to the output end of the inverter U16, and the output end of the push-pull drive sub-circuit P2 is connected to the negative access point on the low-voltage side of the transformer T1; the high-voltage side of the transformer T1 is connected to the full-bridge inverter drive circuit; The input end of the push-pull drive sub-circuit P3 is connected to the output end of the inverter U14, the output end of the push-pull drive sub-circuit P3 is connected to the input end of the capacitor C7, and the output end of the capacitor C7 is connected to the positive access point on the low-voltage side of the transformer T2; the input end of the push-pull drive sub-circuit P4 is connected to the output end of the inverter U18, and the output end of the push-pull drive sub-circuit P4 is connected to the negative access point on the low-voltage side of the transformer T1; the high-voltage side of the transformer T2 is connected to the full-bridge inverter drive circuit.

[0048] Specifically, the push-pull drive sub-circuit P1, the push-pull drive sub-circuit P2, the push-pull drive sub-circuit P3, and the push-pull drive sub-circuit P4 usually include a pair of switches (such as MOSFET or BJT) working in a complementary manner, which are used to generate alternating high and low voltage signals to drive transformer T1 and transformer T2; capacitor C6 and capacitor C7 can be used to smooth the voltage fluctuations generated by the switching action, or serve as energy storage elements; transformer T1 and transformer T2 convert the low voltage signal generated by the push-pull drive sub-circuit into a high voltage signal for use in the full-bridge inverter drive circuit.

[0049] Exemplarily, the inverter U11 outputs a high-level signal to the push-pull drive sub-circuit P1, and the inverter U16 outputs a high-level signal to the push-pull drive sub-circuit P2. Similarly, the inverters U14 and U18 also output signals to the push-pull drive sub-circuit P3 and P4, respectively. When the inverter U11 outputs a high level, the switch in the push-pull drive sub-circuit P1 is actuated, so that the capacitor C6 is charged and current is provided through the positive access point on the low-voltage side of the transformer T1. At the same time, the inverter U16 outputs a high level, and the switch in the push-pull drive sub-circuit P2 works in a complementary manner, providing current through the negative access point on the low-voltage side of the transformer T1, thereby forming a push-pull drive. Similarly, the outputs of the inverters U14 and U18 control the push-pull drive sub-circuits P3 and P4, thereby driving the transformer T2. The transformers T1 and T2 generate corresponding AC voltages on their high-voltage sides according to the signals provided by the push-pull drive sub-circuits. This AC voltage is transmitted to the full-bridge inverter drive circuit for further power conversion or load driving.

[0050] Furthermore, if Figure 4 As shown, the full-bridge inverter drive circuit includes: transistor Q_H1, transistor Q_H2, transistor Q_L1, transistor Q_L2; wherein, The gate of the transistor Q_H1 , the gate of the transistor Q_H2 , the gate of the transistor Q_L1 , and the gate of the transistor Q_L2 are all connected to a control circuit.

[0051] Exemplarily, when the control circuit sends a turn-on signal to the gates of Q_H1 and Q_L2, Q_H1 and Q_L2 will be turned on, while Q_H2 and Q_L1 will remain in the off state. At this time, the current will flow from the positive pole of the DC power supply through Q_H1 to the output end of the circuit, and then flow back to the negative pole of the DC power supply through Q_L2. In this process, the output end of the circuit will present a positive voltage; then, the control circuit switches the signal to turn off Q_H1 and Q_L2, and sends a turn-on signal to the gates of Q_H2 and Q_L1. At this time, Q_H2 and Q_L1 will be turned on, and the current will flow from the negative pole of the DC power supply through Q_L1 to the output end of the circuit, and then flow back to the positive pole of the DC power supply through Q_H2. In this process, the output end of the circuit will present a negative voltage; by continuously switching the control signal, the control circuit can make Q_H1, Q_H2, Q_L1, and Q_L2 alternately turned on and off at a certain frequency, thereby generating an AC voltage at the output end of the circuit. The frequency, amplitude and phase of this AC voltage can be achieved by adjusting the parameters of the control signal.

[0052] Furthermore, if Figure 4 As shown, the control circuit includes a first control subcircuit, a second control subcircuit, a third control subcircuit, and a fourth control subcircuit; wherein, The first control subcircuit includes a transistor Q1, a transistor Q2, a capacitor C8, a resistor R6, and a resistor R7; the source of the transistor Q1 is connected to the positive access point H1 on the high-voltage side of the transformer T1, the drain of the transistor Q1 is respectively connected to the gate of the transistor Q2 and the input end of the resistor R6, the output end of the resistor R6 is respectively connected to the input end of the capacitor C8, the input end of the resistor R7, and the gate of the transistor Q_H1, the source of the transistor Q2 is respectively connected to the negative access point H1 on the high-voltage side of the transformer T1 and the gate of the transistor Q1, and the drain of the transistor Q2 is respectively connected to the output end of the capacitor C8, the output end of the resistor R7, and the emitter of the transistor Q_H1; The second control subcircuit includes a transistor Q3, a transistor Q4, a capacitor C9, a resistor R8, and a resistor R9; the source of the transistor Q3 is connected to the positive access point H2 on the high-voltage side of the transformer T2, the drain of the transistor Q3 is respectively connected to the gate of the transistor Q4 and the input end of the resistor R8, the output end of the resistor R8 is respectively connected to the input end of the capacitor C9, the input end of the resistor R9, and the gate of the transistor Q_H2, the source of the transistor Q4 is respectively connected to the negative access point H2 on the high-voltage side of the transformer T2 and the gate of the transistor Q3, and the drain of the transistor Q4 is respectively connected to the output end of the capacitor C9, the output end of the resistor R9, and the emitter of the transistor Q_H2; The third control subcircuit includes a transistor Q5, a transistor Q6, a capacitor C10, a resistor R10, and a resistor R11; the source of the transistor Q5 is connected to the positive access point of the high-voltage side L1 of the transformer T2, the drain of the transistor Q5 is respectively connected to the gate of the transistor Q6 and the input end of the resistor R10, the output end of the resistor R10 is respectively connected to the input end of the capacitor C10, the input end of the resistor R11, and the gate of the transistor Q_L1, the source of the transistor Q6 is respectively connected to the negative access point of the high-voltage side L1 of the transformer T2 and the gate of the transistor Q5, and the drain of the transistor Q6 is respectively connected to the output end of the capacitor C10, the output end of the resistor R11, and the emitter of the transistor Q_L1; The fourth control subcircuit includes a transistor Q7, a transistor Q8, a capacitor C11, a resistor R12, and a resistor R13; the source of the transistor Q7 is connected to the positive access point of the high-voltage side L2 of the transformer T1, the drain of the transistor Q7 is respectively connected to the gate of the transistor Q8 and the input end of the resistor R12, the output end of the resistor R12 is respectively connected to the input end of the capacitor C11, the input end of the resistor R13, and the gate of the transistor Q_L2, the source of the transistor Q8 is respectively connected to the negative access point of the high-voltage side L2 of the transformer T1 and the gate of the transistor Q7, and the drain of the transistor Q8 is respectively connected to the output end of the capacitor C11, the output end of the resistor R13, and the emitter of the transistor Q_L2.

[0053] For example, when the positive access point H1 on the high-voltage side of transformer T1 receives a forward pulse signal, the signal is added to the gate of Q_H1 through the internal diode of Q1 and the resistor R6; since the internal diode of Q1 is turned on, the gate of Q_H1 obtains a positive voltage, causing Q_H1 to be turned on; at the same time, the forward pulse signal also charges the capacitor C8 through Q1 and R6 to provide voltage for subsequent maintenance of conduction; when the forward pulse signal turns to a low level, the gate voltage of Q1 drops to 0 (Vgs=0), causing Q1 to be turned off; since the capacitor C8 has been charged before, it will maintain the positive voltage of the gate of Q_H1 for a period of time to ensure that Q_H1 is still turned on during the low level of the pulse signal; when a reverse pulse signal is received (that is, the voltage on the high-voltage side of transformer T1 In the reverse direction, the gate of Q1 obtains a negative voltage (relative to its source), causing the internal diode of Q1 to be reversely cut off; however, since Q1 is an N_MOS tube, the negative voltage from its gate to the source will turn on Q1 (for N_MOS tube, it will be turned on when Vgs<0); the negative voltage is added to the gate of Q_H1 through Q1, resistor R6 and the internal diode of Q2, causing Q_H1 to be reverse biased and cut off; at the same time, this negative voltage also reversely charges capacitor C8 to provide voltage for subsequent maintenance of cutoff; when the reverse pulse signal turns to a low level, the gate voltage of Q1 drops to 0 again (Vgs=0), causing Q1 to be cut off; capacitor C8 now maintains the negative voltage of the gate of Q_H1 to ensure that Q_H1 is still cut off during the low level of the reverse pulse signal.

[0054] Based on the same inventive concept, Figure 5 As shown, the present invention also provides a driving method for a solar photovoltaic inverter, the method comprising: Receive SPWM signal; Modulating the SPWM signal to generate a low voltage signal and boosting it to obtain a driving signal; According to the driving signal, the on and off of transistors Q_H1, Q_H2, Q_L1 and Q_L2 are controlled to convert DC power into AC power; When a fault signal is detected, a low level signal is output to turn off the drive signal.

[0055] Based on the same inventive concept, the present invention also provides a solar photovoltaic inverter, the inverter comprising any one of the above drive circuits, for converting direct current power into alternating current power.

[0056] It should be noted that the electrical connection between the above-mentioned units does not necessarily mean the connection between the lines. The indirect connection method can be applied to the embodiments of the present invention as long as the purpose of the present invention is achieved. The above are only exemplary embodiments of the present invention and cannot limit the scope of the present invention.

[0057] That is, any equivalent changes and modifications made according to the teachings of the present invention are still within the scope of the present invention. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present invention. This application is intended to cover any variation, use or adaptive change of the present invention, which follows the general principles of the present invention and includes common knowledge or customary technical means in the art that are not described in the present invention.

Claims

1. A driving circuit for a solar photovoltaic inverter, characterized in that: The drive circuit comprises: a signal input circuit, a drive signal modulation circuit and a full-bridge inverter drive circuit, wherein the drive signal modulation circuit comprises a dead time setting circuit, a fault protection circuit, a transformer pulse drive generation circuit and a transformer drive circuit; wherein, The signal input circuit comprises a NAND gate U1, a first input terminal and a second input terminal of the NAND gate U1 are both connected to the SPWM input pin, and an output terminal of the NAND gate U1 is connected to the dead time setting circuit; The dead time setting circuit is connected to the fault protection circuit and is used to set the dead time between the upper and lower bridge arms of the inverter H bridge in the full-bridge inverter drive circuit; The fault protection circuit is connected to the transformer pulse drive generating circuit and is used to output a low level signal when a fault signal is detected; The transformer pulse drive generating circuit is connected to the dead time setting circuit and is used to receive the SPWM signal to generate a low voltage signal; The transformer driving circuit is connected to the transformer pulse driving generating circuit, and is used to receive the low voltage signal and boost the low voltage signal to obtain a driving signal; The full-bridge inverter drive circuit is connected to the transformer drive circuit and is used to receive the drive signal to control the on and off of the power switch element.

2. The driving circuit of the solar photovoltaic inverter according to claim 1, characterized in that: The dead time setting circuit includes a resistor R1 and a capacitor C1; wherein, The output end of the resistor R1 is respectively connected to the input end of the capacitor C1 and the first input end of the transformer pulse drive generating circuit, and the input end of the resistor R1 is respectively connected to the output end of the NAND gate U1 and the second input end of the transformer pulse drive generating circuit; the output end of the capacitor C1 is grounded.

3. The driving circuit of the solar photovoltaic inverter according to claim 2, characterized in that: The transformer pulse drive generating circuit includes a pulse generating subcircuit, and the pulse generating subcircuit includes an inverter U2, an inverter U3, a NAND gate U4, an inverter U5, an inverter U6, a NAND gate U7, an inverter U8, an inverter U9, a NAND gate U10, an inverter U11, an inverter U12, a NAND gate U13 and an inverter U14; wherein, The input end of the inverter U2 is connected to the output end of the resistor R1, the output end of the inverter U2 is connected to the first input end of the NAND gate U4, the second input end of the NAND gate U4 is connected to the output end of the inverter U3, the output end of the NAND gate U4 is connected to the input end of the inverter U5, and the output end of the inverter U5 is connected to the transformer driving circuit; the output end of the inverter U3 is connected to the first input end of the NAND gate U7, the second input end of the NAND gate U7 is connected to the output end of the inverter U6, the output end of the NAND gate U7 is connected to the input end of the inverter U8, and the output end of the inverter U8 is connected to the transformer driving circuit; The first input end of the NAND gate U10 is connected to the input end of the resistor R1, the second input end of the NAND gate U10 is connected to the output end of the inverter U9, the output end of the NAND gate U10 is connected to the input end of the inverter U11, and the output end of the inverter U11 is connected to the transformer driving circuit; the output end of the inverter U9 is connected to the first input end of the NAND gate U13, the second input end of the NAND gate U13 is connected to the output end of the inverter U12, the output end of the NAND gate U13 is connected to the input end of the inverter U14, and the output end of the inverter U14 is connected to the transformer driving circuit.

4. The driving circuit of the solar photovoltaic inverter according to claim 3, characterized in that: The transformer pulse drive generating circuit further includes a pulse width modulation subcircuit, and the pulse width modulation subcircuit includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2, a diode D3 and a diode D4; wherein, The input end of the resistor R2 is connected to the output end of the inverter U2 and the output end of the diode D1 respectively, the output end of the resistor R2 is connected to the input end of the inverter U3, the input end of the capacitor C2 and the input end of the diode D1 respectively, and the output end of the capacitor C2 is grounded; the input end of the resistor R3 is connected to the output end of the inverter U3 and the output end of the diode D2 respectively, the output end of the resistor R3 is connected to the input end of the inverter U6, the input end of the capacitor C2 and the input end of the diode D2 respectively, and the output end of the capacitor C3 is grounded; The input end of the resistor R4 is respectively connected to the input end of the resistor R1 and the output end of the diode D3, the output end of the resistor R4 is respectively connected to the input end of the inverter U9, the input end of the capacitor C4 and the input end of the diode D3, and the output end of the capacitor C4 is grounded; the input end of the resistor R5 is respectively connected to the output end of the inverter U9 and the output end of the diode D4, the output end of the resistor R5 is respectively connected to the input end of the inverter U12, the input end of the capacitor C5 and the input end of the diode D4, and the output end of the capacitor C5 is grounded.

5. The driving circuit of the solar photovoltaic inverter according to claim 4, characterized in that: The fault protection circuit includes a NAND gate U15, an inverter U16, a NAND gate U17 and an inverter U18; wherein, The first input end of the NAND gate U15 is connected to the output end of the inverter U5, the second input end of the NAND gate U15 is connected to the fault signal output pin, the output end of the NAND gate U15 is connected to the input end of the inverter U16, and the output end of the inverter U16 is connected to the transformer driving circuit; The first input end of the NAND gate U17 is connected to the fault signal output pin, the second input end of the NAND gate U17 is connected to the output end of the inverter U8, the output end of the NAND gate U17 is connected to the input end of the inverter U18, and the output end of the inverter U18 is connected to the transformer drive circuit.

6. The driving circuit of the solar photovoltaic inverter according to claim 5, characterized in that: The transformer driving circuit includes a push-pull driving sub-circuit P1, a push-pull driving sub-circuit P2, a push-pull driving sub-circuit P3, a push-pull driving sub-circuit P4, a capacitor C6, a capacitor C7, a transformer T1 and a transformer T2; wherein, The input end of the push-pull drive sub-circuit P1 is connected to the output end of the inverter U11, the output end of the push-pull drive sub-circuit P1 is connected to the input end of the capacitor C6, and the output end of the capacitor C6 is connected to the positive access point on the low-voltage side of the transformer T1; the input end of the push-pull drive sub-circuit P2 is connected to the output end of the inverter U16, and the output end of the push-pull drive sub-circuit P2 is connected to the negative access point on the low-voltage side of the transformer T1; the high-voltage side of the transformer T1 is connected to the full-bridge inverter drive circuit; The input end of the push-pull drive sub-circuit P3 is connected to the output end of the inverter U14, the output end of the push-pull drive sub-circuit P3 is connected to the input end of the capacitor C7, and the output end of the capacitor C7 is connected to the positive access point on the low-voltage side of the transformer T2; the input end of the push-pull drive sub-circuit P4 is connected to the output end of the inverter U18, and the output end of the push-pull drive sub-circuit P4 is connected to the negative access point on the low-voltage side of the transformer T1; the high-voltage side of the transformer T2 is connected to the full-bridge inverter drive circuit.

7. The driving circuit of the solar photovoltaic inverter according to claim 6, characterized in that: The full-bridge inverter drive circuit includes: transistor Q_H1, transistor Q_H2, transistor Q_L1 and transistor Q_L2; wherein, The gate of the transistor Q_H1 , the gate of the transistor Q_H2 , the gate of the transistor Q_L1 , and the gate of the transistor Q_L2 are all connected to a control circuit.

8. The driving circuit of the solar photovoltaic inverter according to claim 7, characterized in that: The control circuit includes a first control subcircuit, a second control subcircuit, a third control subcircuit and a fourth control subcircuit; wherein, The first control subcircuit includes a transistor Q1, a transistor Q2, a capacitor C8, a resistor R6 and a resistor R7; the source of the transistor Q1 is connected to the positive access point H1 on the high-voltage side of the transformer T1, the drain of the transistor Q1 is respectively connected to the gate of the transistor Q2 and the input end of the resistor R6, the output end of the resistor R6 is respectively connected to the input end of the capacitor C8, the input end of the resistor R7, and the gate of the transistor Q_H1, the source of the transistor Q2 is respectively connected to the negative access point H1 on the high-voltage side of the transformer T1 and the gate of the transistor Q1, and the drain of the transistor Q2 is respectively connected to the output end of the capacitor C8, the output end of the resistor R7, and the emitter of the transistor Q_H1; The second control subcircuit includes a transistor Q3, a transistor Q4, a capacitor C9, a resistor R8 and a resistor R9; the source of the transistor Q3 is connected to the positive access point H2 on the high-voltage side of the transformer T2, the drain of the transistor Q3 is respectively connected to the gate of the transistor Q4 and the input end of the resistor R8, the output end of the resistor R8 is respectively connected to the input end of the capacitor C9, the input end of the resistor R9, and the gate of the transistor Q_H2, the source of the transistor Q4 is respectively connected to the negative access point H2 on the high-voltage side of the transformer T2 and the gate of the transistor Q3, and the drain of the transistor Q4 is respectively connected to the output end of the capacitor C9, the output end of the resistor R9, and the emitter of the transistor Q_H2; The third control subcircuit includes a transistor Q5, a transistor Q6, a capacitor C10, a resistor R10 and a resistor R11; the source of the transistor Q5 is connected to the positive access point of the high-voltage side L1 of the transformer T2, the drain of the transistor Q5 is respectively connected to the gate of the transistor Q6 and the input end of the resistor R10, the output end of the resistor R10 is respectively connected to the input end of the capacitor C10, the input end of the resistor R11, and the gate of the transistor Q_L1, the source of the transistor Q6 is respectively connected to the negative access point of the high-voltage side L1 of the transformer T2 and the gate of the transistor Q5, and the drain of the transistor Q6 is respectively connected to the output end of the capacitor C10, the output end of the resistor R11, and the emitter of the transistor Q_L1; The fourth control subcircuit includes a transistor Q7, a transistor Q8, a capacitor C11, a resistor R12 and a resistor R13; the source of the transistor Q7 is connected to the positive access point of the high-voltage side L2 of the transformer T1, the drain of the transistor Q7 is respectively connected to the gate of the transistor Q8 and the input end of the resistor R12, the output end of the resistor R12 is respectively connected to the input end of the capacitor C11, the input end of the resistor R13, and the gate of the transistor Q_L2, the source of the transistor Q8 is respectively connected to the negative access point of the high-voltage side L2 of the transformer T1 and the gate of the transistor Q7, and the drain of the transistor Q8 is respectively connected to the output end of the capacitor C11, the output end of the resistor R13, and the emitter of the transistor Q_L2.

9. A method for driving a solar photovoltaic inverter, applied to the driving circuit of the solar photovoltaic inverter according to any one of claims 1 to 8, characterized in that: The method comprises: Receive SPWM signal; Modulating the SPWM signal to generate a low voltage signal and boosting it to obtain a driving signal; Controlling the on and off of transistors Q_H1, Q_H2, Q_L1, and Q_L2 according to the driving signal to convert direct current power into alternating current power; When a fault signal is detected, a low level signal is output to turn off the driving signal.

10. A solar photovoltaic inverter, characterized in that: The inverter comprises a drive circuit as claimed in any one of claims 1 to 8, for converting direct current power into alternating current power.

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