Switching device

Abstract

A first semiconductor device and a second semiconductor device of the switching device comprise a first side, a second side, a third side, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal and a sixth terminal, wherein the second side and the third side are opposite to each other; the second terminal faces the second side; the third terminal faces the third side; the first and second terminals are connected during a period in which the sixth, fourth, and fifth terminals receive the first, second, and third voltages, and the first and third terminals are connected during a period in which the sixth, fourth, and fifth terminals receive the fourth, third, and second voltages, respectively. The first delay circuit supplies a signal obtained by delaying a signal of an input terminal connected to a second terminal of the first semiconductor device to a third terminal of the second semiconductor device. The first conductor connects the fourth terminal of the first semiconductor device and the fifth terminal of the second semiconductor device. The second conductor connects the fifth terminal of the first semiconductor device and the fourth terminal of the second semiconductor device. The first sides of the first and second semiconductor devices face each other.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-129405 (filing date: August 8, 2023), which is a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a switch device. Background Art

[0004] As a technology used in wireless communication, MIMO (Multiple Input Multiple Output) is known. A transceiver supporting MIMO includes multiple antennas and multiple switching circuits. The transceiver uses a phase switching device to generate transmission signals with multiple different phases based on a common signal, and transmits the multiple transmission signals from the multiple antennas respectively. The transceiver includes the same number of phase switching devices as the number of antennas.

[0005] The performance of MIMO can be improved by increasing the number of antennas. The more antennas there are, the more phase switch devices are needed. Therefore, in order to efficiently manufacture the transceiver, it is required that the components in each phase switch device be connected simply. Summary of the invention

[0006] A switch device according to one embodiment includes a first semiconductor chip, a second semiconductor chip, a first delay circuit, a first conductor, and a second conductor. The first semiconductor chip and the second semiconductor chip each include a first side, a second side and a third side facing each other, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal arranged along the first side, and a sixth terminal. The first terminal is connected to the second terminal during a period when the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage, and the first terminal is connected to the third terminal during a period when the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage. The first delay circuit supplies a signal obtained by delaying a signal of an input terminal connected to the second terminal of the first semiconductor chip to the third terminal of the second semiconductor chip. The first conductor connects the fourth terminal of the first semiconductor chip to the fifth terminal of the second semiconductor chip. The second conductor connects the fifth terminal of the first semiconductor chip to the fourth terminal of the second semiconductor chip. The first side of the first semiconductor device is opposite to the first side of the second semiconductor device. The sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage. The sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage.

[0007] According to this embodiment, it is possible to provide a switch device in which the internal components can be easily connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Functional blocks of the transceiver device including the switch device according to the first embodiment and connections of the functional blocks are shown.

[0009] Figure 2 Functional blocks of the switch device according to the first embodiment and connections between the functional blocks are shown.

[0010] Figure 3 Component elements of a switch circuit of a switch device according to the first embodiment and connections of the components are shown.

[0011] Figure 4 The relationship between the input and output of the logic circuit included in the switch device according to the first embodiment is shown.

[0012] Figure 5 An example of the structure of the switch circuit of the switch device according to the first embodiment is shown.

[0013] Figure 6An example of a part of the structure of the switch device according to the first embodiment is shown.

[0014] Figure 7 An example of the structure of a switch circuit of a switch device according to the second embodiment is shown.

[0015] Figure 8 An example of a part of the structure of the switch device according to the second embodiment is shown.

[0016] Fig. 9 An example of the structure of a switch circuit of a switch device according to the third embodiment is shown.

[0017] Fig.10 An example of a part of the structure of the switch device according to the third embodiment is shown.

[0018] Fig.11 An example of the structure of a switch circuit of a switch device according to a fourth embodiment is shown.

[0019] Fig.12 An example of a part of the structure of the switch device according to the fourth embodiment is shown.

[0020] Description of Reference Numerals

[0021] 10…transceiver,

[0022] 1…data processing circuit,

[0023] 2… transceiver,

[0024] 3…Amplifier circuit,

[0025] 4…Switch device,

[0026] 5…antenna,

[0027] 11…Switching circuit,

[0028] 12…Delay circuit,

[0029] 13…Control circuit,

[0030] 21…Semiconductor devices,

[0031] 111…Logic circuit,

[0032] 23…Printed wiring board,

[0033] RFC, RF1, RF2, RF3, RF4, TGND, TVDD, TN... terminals,

[0034] W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, W18... wiring. DETAILED DESCRIPTION

[0035] The following describes the embodiments with reference to the accompanying drawings. In order to distinguish between a plurality of components having substantially the same function and configuration in a certain embodiment or different embodiments, sometimes numbers or letters are further added to the end of the reference figure mark. In the embodiments following a certain embodiment that has been described, the main points that are different from the embodiments that have been described are described. Unless explicitly or obviously excluded, all descriptions of a certain embodiment also apply to the descriptions of other embodiments.

[0036] In the present specification and claims, a first element “connected to” another second element includes the first element being directly connected to the second element, or being connected to the second element via an element that is always conductive or selectively conductive.

[0037] Hereinafter, the implementation method is described using an XYZ orthogonal coordinate system. The positive direction of the vertical axis of the figure is sometimes referred to as the upper side, and the negative direction is referred to as the lower side. The positive direction of the horizontal axis of the figure is sometimes referred to as the right side, and the negative direction is referred to as the left side. That is, in a top view representing an XY plane (in an XY view (hereinafter the same), the upper side refers to the +Y direction, the lower side refers to the -Y direction, the right side refers to the +X direction, and the left side refers to the -X direction.

[0038] 1. First Implementation

[0039] 1.1. Composition (structure)

[0040] Figure 1 1 shows the functional modules of the transceiver device including the switch device of the first embodiment and the connection of the functional modules. Figure 1 As shown, the transceiver device 10 includes a data processing circuit 1 , a transceiver 2 , an amplifier circuit 3 , a plurality of switch devices 4 , and a plurality of antennas 5 . Figure 1 An example of four switch devices and four antennas is shown, and the following description is based on this example.

[0041] The data processing circuit 1 is a circuit that generates data to be transmitted by the transceiver 10. The data processing circuit 1 may be realized as a single semiconductor chip or may be a circuit formed on a semiconductor substrate.

[0042] The transceiver 2 generates a signal to be transmitted by the transceiver device 10. The transceiver 2 receives data from the data processing circuit 1 and modulates the data to generate a transmission signal. The transceiver 2 may be implemented as a semiconductor chip or as a circuit formed on a semiconductor substrate.

[0043] The amplifier circuit 3 is a circuit that amplifies a signal received from the amplifier circuit 3. The amplifier circuit 3 receives a transmission signal from the transceiver 2, and amplifies the received transmission signal for transmission. The amplifier circuit 3 may be implemented as a single semiconductor chip or may be a circuit formed on a semiconductor substrate.

[0044] Each switch device 4 is a circuit that changes the phase of a received signal. The switch device 4 receives a signal from the amplifier circuit 3 and changes the phase of the received signal by a magnitude of one of a plurality of phases that is dynamically selected. Each switch device 4 is implemented as a device including a semiconductor chip, for example, a semiconductor device (or semiconductor module) including a semiconductor chip, a resin that seals the semiconductor chip, and a terminal for electrical connection to the outside.

[0045] Each antenna 5 wirelessly transmits a signal received by the antenna 5 to the outside of the transceiver 10. Each antenna 5 is connected to one switch device 4.

[0046] Figure 2 2 is a diagram showing the functional modules of the switch device of the first embodiment and the connection of the functional modules. Figure 2 As shown, the switch device 4 includes two switch circuits 11 ( 11 a and 11 b ), a plurality of delay circuits 12 ( 12 a , 12 b , 12 c , and 12 d ), and a control circuit 13 . Figure 2 An example of four delay circuits 12 is shown, and the following description is based on this example.

[0047] The switch circuit 11 includes a terminal RFC and a plurality of terminals RF (RF1, RF2, RF3, and RF4). The number of the terminals RF matches the number of the delay circuits 12. The switch circuit 11 electrically connects the terminal RFC to a dynamically selected one of the terminals RF1, RF2, RF3, and RF4 based on the control of the control circuit 13.

[0048] The switch circuits 11a and 11b are the same switch circuits. The switch circuit 11a is connected to the amplifier circuit 3 at the terminal RFC. The switch circuit 11a is connected to the input end of the delay circuit 12a at the terminal RF1. The switch circuit 11a is connected to the input end of the delay circuit 12b at the terminal RF2. The switch circuit 11a is connected to the input end of the delay circuit 12c at the terminal RF3. The switch circuit 11a is connected to the input end of the delay circuit 12d at the terminal RF4.

[0049] The switch circuit 11b is connected to an antenna 5 at a terminal RFC. The switch circuit 11b is connected to an output end of the delay circuit 12d at a terminal RF1. The switch circuit 11b is connected to an output end of the delay circuit 12c at a terminal RF2. The switch circuit 11b is connected to an output end of the delay circuit 12b at a terminal RF3. The switch circuit 11b is connected to an output end of the delay circuit 12a at a terminal RF4.

[0050] The delay circuit 12 is a circuit that delays a signal received at an input terminal by a predetermined phase and outputs the delayed signal from an output terminal. The delay circuits 12a, 12b, 12c, and 12d delay received signals by different phases.

[0051] The control circuit 13 is a circuit for controlling the operation of the switch device 4. The control circuit 13 generates a control signal for controlling the switch circuit 11 based on the operation that the switch device 4 should perform, that is, the amount of delay of the signal based on the operation, and outputs the control signal.

[0052] Figure 3 Components of a switch circuit of a switch device according to the first embodiment and connections of the components are shown. Figure 3 As shown, the switch circuit 11 includes switches SW1, SW2, SW3 and SW4, and a logic circuit 111. The switch circuit 11 includes switches SW1, SW2, SW3 and SW4, and a logic circuit 111. Figure 2 In addition to the terminals RFC, RF1, RF2, RF3, and RF4 as described above, the terminals LS, V1, V2, TVDD, and TGND are also included.

[0053] The switch SW1 receives a control signal SC1 and electrically connects or disconnects both ends of the switch SW1 based on the control signal SC1. The switch SW1 is connected between the terminal RFC and the terminal RF1. The switch SW1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0054] The switch SW2 receives the control signal SC2 and electrically connects or disconnects the two ends of the switch SW2 based on the control signal SC2. The switch SW2 terminal is connected between RFC and the terminal RF2. The switch SW2 is, for example, a MOSFET.

[0055] The switch SW3 receives the control signal SC3 and electrically connects or disconnects both ends of the switch SW3 based on the control signal SC3. The switch SW3 is connected between the terminal RFC and the terminal RF3. The switch SW3 is, for example, a MOSFET.

[0056] The switch SW4 receives the control signal SC4 and electrically connects or disconnects both ends of the switch SW4 based on the control signal SC4. The switch SW4 is connected between the terminal RFC and the terminal RF4. The switch SW4 is, for example, a MOSFET.

[0057] The logic circuit 111 generates control signals SC1, SC2, SC3, and SC4 based on the voltages received at the terminals LS, V1, and V2. Figure 4 The control signals SC1, SC2, SC3 and SC4 described below can be configured arbitrarily. The logic circuit 111 includes, for example, a plurality of logic gates.

[0058] Figure 4 The relationship between the input and output of the logic circuit included in the switch device of the first embodiment is shown. Terminals V1 and V2 receive two voltages of different magnitudes and dynamically select one of them. One voltage is called the "0" voltage. Figure 4 The voltage on the other side is called the "1" voltage. Figure 4 It is recorded as "1".

[0059] The control signals SC1, SC2, SC3, and SC4 each have one of two different magnitudes. Figure 4 In the following description, a state where control signal SC1 has a voltage that keeps switch SW1 turned on, a state where control signal SC2 has a voltage that keeps switch SW2 turned on, a state where control signal SC3 has a voltage that keeps switch SW3 turned on, and a state where control signal SC4 has a voltage that keeps switch SW4 turned on are referred to as control signals SC1, SC2, SC3, and SC4 having an ON level. A state where control signal SC1 has a voltage that keeps switch SW1 turned off, a state where control signal SC2 has a voltage that keeps switch SW2 turned off, a state where control signal SC3 has a voltage that keeps switch SW3 turned off, and a state where control signal SC4 has a voltage that keeps switch SW4 turned off are referred to as control signals SC1, SC2, SC3, and SC4 having an OFF level. Figure 4 In the , the ON level is recorded as "ON". Figure 4 In the figure, the OFF level is recorded as "OFF".

[0060] During the period when the terminal LS receives the ground voltage GND, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has an "ON" level, the control signal SC2 has an "OFF" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF1 among the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW1. That is, the terminal RF1 is selected.

[0061] During the period when the terminal LS receives the ground voltage GND, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has an "OFF" level, the control signal SC2 has an "ON" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF2 of the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW2. That is, the terminal RF2 is selected.

[0062] During the period when the terminal LS receives the ground voltage GND, the terminal V1 receives the "1" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has an "OFF" level, the control signal SC2 has an "OFF" level, the control signal SC3 has an "ON" level, and the control signal SC4 has an "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF3 among the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW3. That is, the terminal RF3 is selected.

[0063] During the period when the terminal LS receives the ground voltage GND, the terminal V1 receives the "1" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has an "OFF" level, the control signal SC2 has an "OFF" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "ON" level. Therefore, the terminal RFC is connected to only the terminal RF4 among the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW4. That is, the terminal RF4 is selected.

[0064] During the period when the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has an "OFF" level, the control signal SC2 has an "OFF" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "ON" level. Therefore, the terminal RFC is connected to only the terminal RF4 among the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW4. That is, the terminal RF4 is selected.

[0065] When the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has an "OFF" level, the control signal SC2 has an "ON" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF2 of the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW2. That is, the terminal RF2 is selected.

[0066] During the period when the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "1" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has the "OFF" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "ON" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF3 among the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW3. That is, the terminal RF3 is selected.

[0067] During the period when the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "1" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has an "ON" level, the control signal SC2 has an "OFF" level, the control signal SC3 has an "OFF" level, and the control signal SC4 has an "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF1 of the terminals RF1, RF2, RF3, and RF4 via the turned-on switch SW1. That is, the terminal RF1 is selected.

[0068] Figure 5 An example of the structure of the switch circuit of the switch device according to the first embodiment is shown. The switch circuit 11 is realized as a semiconductor device 21 . Figure 5 And the subsequent figures indicate elements shown in perspective by dashed lines.

[0069] like Figure 5 As shown in FIG. 1 , the semiconductor device 21 extends along the XY plane and has a quadrilateral shape. As an example, the semiconductor device 21 has a rectangular shape.

[0070] The semiconductor device 21 includes terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN. The terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN are arranged on the lower surface of the semiconductor device 21, that is, on the surface on the -Z direction side. The terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN are arranged along the edge of the semiconductor device 21. In one example, six terminals are arranged with intervals along each side of the semiconductor device 21. The following description is based on this example.

[0071] The side facing the terminal RFC among the four sides of the semiconductor device 21 is called the first side L1. The second side L2 is opposite to the first side L1. In one example, the first side L1 and the second side L2 are arranged in the +X direction. The side facing the terminal RF1 among the four sides of the semiconductor device 21 is called the third side L3. The third side L3 is opposite to the fourth side L4. In one example, the fourth side L4 and the third side L3 are arranged in the +Y direction.

[0072] In one example, the terminal RFC is arranged at a fourth position from the third side L3.

[0073] Terminals V1, V2, LS and TVDD face the second side L2. Terminals V1 and V2 are adjacent. In one example, terminal V1 is arranged at the fourth position from the third side L3, and terminal V2 is arranged at the fifth position from the third side L3. Terminals LS and TVDD can occupy the position of any remaining terminal among the plurality of terminals arranged along the second side L2.

[0074] Terminals RF1 and RF2 face the third side L3. Terminals RF1 and RF2 can occupy the position of any terminal among the plurality of terminals arranged along the third side L3. In one example, terminal RF1 is arranged at the second position from the first side L1, and terminal RF2 is arranged at the fifth position from the first side L1.

[0075] Terminals RF3 and RF4 face the fourth side L4. Terminal RF3 is arranged near the side closer to terminal RF2 of the first side L1 and the second side L2. If, based on the example in which terminal RF1 is arranged at the second position from the first side L1 and terminal RF2 is arranged at the fifth position from the first side L1, terminal RF3 is arranged near the second side L2 compared to the first side L1. In one example, terminal RF3 and terminal RF2 are arranged in the +Y direction.

[0076] The terminal RF4 is arranged near the first side L1 and the second side L2, whichever is closer to the terminal RF1. Based on the example in which the terminal RF1 is arranged at the second position from the first side L1 and the terminal RF2 is arranged at the fifth position from the first side L1, the terminal RF4 is arranged near the first side L1 compared to the second side L2. In one example, the terminal RF4 and the terminal RF1 are arranged in the +Y direction.

[0077] The terminal TN occupies a position other than the terminals RFC, V1, V2, LS, TVDD, and TGND. In one example, the terminal TN functions as a ground terminal.

[0078] The terminal TGND has a quadrilateral shape, and in one example, has a rectangular shape. The terminal TGND is arranged at the center of the semiconductor device 21 .

[0079] Figure 6 FIG. 1 is a diagram showing an example of a part of the structure of the switch device according to the first embodiment, and shows the arrangement of the components of the switch device along the XY plane. Figure 6 As shown, the switch device 4 includes a semiconductor device 21 (21a and 21b), a printed wiring board 23, and wirings W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18.

[0080] The printed wiring board 23 is a substrate including an insulating substrate. The printed wiring board 23 extends along the XY plane. The printed wiring board 23 may also include a plurality of insulating layers and a conductor having a pattern between the insulating layers. The printed wiring board 23 is also provided with the control circuit 13 (not shown).

[0081] Semiconductor device 21a realizes switch circuit 11a. Semiconductor device 21b realizes switch circuit 11b. Semiconductor device 21 is arranged on the surface (upper surface) on the +Z direction side of printed wiring board 23. Semiconductor device 21 faces printed wiring board 23 on the lower surface. Semiconductor device 21a and semiconductor device 21b are arranged in +X direction.

[0082] The semiconductor devices 21a and 21b face opposite directions to each other. That is, the third side L3 of the semiconductor device 21a faces the +Y direction, and the third side L3 of the semiconductor device 21b faces the -Y direction.

[0083] The terminals V1 and V2 of the semiconductor device 21 a are connected to the control circuit 13 via wiring (not shown) provided on the printed wiring board 23 , and receive a voltage from the control circuit 13 .

[0084] The terminal TVDD receives the power supply voltage VDD. One of the terminal TVDD of the semiconductor device 21a and the terminal TVDD of the semiconductor device 21b is connected to a node to which the power supply voltage VDD is supplied via a wiring (not shown) provided on the printed wiring substrate 23. The terminal TVDD of the semiconductor device 21a and the terminal TVDD of the semiconductor device 21b are connected via a wiring (not shown) provided on the printed wiring substrate 23.

[0085] The terminal TGND receives the ground voltage GND. The terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b are connected to a node that supplies the ground voltage GND through respective wirings (not shown) provided on the printed wiring substrate 23. Alternatively, one of the terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b may be connected to a node that supplies the ground voltage GND, and the terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b may be connected to each other through wirings provided on the printed wiring substrate 23.

[0086] The delay circuits 12a, 12b, 12c and 12d are arranged on the upper surface of the printed wiring board 23. The delay circuits 12a, 12b, 12c and 12d are arranged in this order in the -Y direction. The group of delay circuits 12a, 12b, 12c and 12d is arranged between the semiconductor devices 21a and 21b.

[0087] The wirings W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18 are conductors having a linear shape. The wirings W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18 are arranged on the upper surface of the printed wiring board 23.

[0088] One end of the wiring W1 overlaps with the terminal LS of the semiconductor device 21a and is connected to the terminal LS of the semiconductor device 21a. The other end of the wiring W1 overlaps with the terminal TGND of the semiconductor device 21a and is connected to the terminal TGND of the semiconductor device 21a. Thus, the voltage of the terminal LS of the semiconductor device 21a is fixed to the ground voltage GND.

[0089] One end of the wiring W2 overlaps with the terminal LS of the semiconductor device 21b and is connected to the terminal LS of the semiconductor device 21b. The other end of the wiring W2 overlaps with the terminal TVDD of the semiconductor device 21b and is connected to the terminal TVDD of the semiconductor device 21b. Thus, the voltage of the terminal LS of the semiconductor device 21b is fixed to the power supply voltage VDD.

[0090] One end of the wiring W3 overlaps with the terminal RFC of the semiconductor device 21 a and is connected to the terminal RFC of the semiconductor device 21 a . The other end of the wiring W3 is connected to the amplifier circuit 3 .

[0091] One end of the wiring W4 overlaps with the terminal RFC of the semiconductor device 21 b and is connected to the terminal RFC of the semiconductor device 21 b . The other end of the wiring W4 is connected to the amplifier circuit 3 .

[0092] One end of the wiring W11 overlaps with the terminal RF1 of the semiconductor device 21a and is connected to the terminal RF1 of the semiconductor device 21a. The other end of the wiring W11 is connected to the input terminal of the delay circuit 12a.

[0093] One end of the wiring W12 is connected to the output end of the delay circuit 12a. The other end of the wiring W12 overlaps with the terminal RF4 of the semiconductor device 21b and is connected to the terminal RF4 of the semiconductor device 21b.

[0094] One end of the wiring W13 overlaps with the terminal RF2 of the semiconductor device 21a and is connected to the terminal RF2 of the semiconductor device 21a. The other end of the wiring W13 is connected to the input terminal of the delay circuit 12b.

[0095] One end of the wiring W14 is connected to the output end of the delay circuit 12b. The other end of the wiring W14 overlaps with the terminal RF3 of the semiconductor device 21b and is connected to the terminal RF3 of the semiconductor device 21b.

[0096] The semiconductor devices 21a and 21b are shown in FIG. Figure 5 The described configuration has terminals facing opposite to each other and has a reference Figure 4 The relationship between the input (voltages of the terminals LS, V1, and V2) and the output (control signals SC1, SC2, SC3, and SC4) described above. Therefore, the group of the terminal RF1 of the semiconductor device 21a and the terminal RF4 of the semiconductor device 21b connected to each other via the delay circuit 12a is located outside the group of the terminal RF2 of the semiconductor device 21a and the terminal RF3 of the semiconductor device 21b connected to each other via the delay circuit 12b. As a result, the wiring W11 and the wiring W13 can be extended from the terminal RF1 of the semiconductor device 21a to the input end of the delay circuit 12a without crossing each other, and the wiring W13 and the wiring W11 can be extended from the terminal RF2 of the semiconductor device 21a to the input end of the delay circuit 12b without crossing each other. Furthermore, the wiring W12 and the wiring W14 can extend from the output end of the delay circuit 12a to the terminal RF4 of the semiconductor device 21b without crossing each other, and the wiring W14 and the wiring W12 can extend from the output end of the delay circuit 12b to the terminal RF3 of the semiconductor device 21b without crossing each other.

[0097] The shapes of the wiring W11 and the wiring W13 along the XY plane may have any shape as long as there is no intersection. The shapes of the wiring W12 and the wiring W14 along the XY plane may have any shape as long as there is no intersection. Figure 6 Although an example in which each of the wirings W11 , W12 , W13 , and W14 has an L-shape is shown, one or more of the wirings W11 , W12 , W13 , and W14 may be bent at two or more locations.

[0098] One end of the wiring W15 overlaps with the terminal RF3 of the semiconductor device 21a and is connected to the terminal RF3 of the semiconductor device 21a. The other end of the wiring W15 is connected to the input terminal of the delay circuit 12c.

[0099] One end of the wiring W16 is connected to the output end of the delay circuit 12c. The other end of the wiring W16 overlaps with the terminal RF2 of the semiconductor device 21b and is connected to the terminal RF2 of the semiconductor device 21b.

[0100] One end of the wiring W17 overlaps with the terminal RF4 of the semiconductor device 21a and is connected to the terminal RF4 of the semiconductor device 21a. The other end of the wiring W17 is connected to the input terminal of the delay circuit 12d.

[0101] One end of the wiring W18 is connected to the output end of the delay circuit 12d. The other end of the wiring W18 overlaps with the terminal RF1 of the semiconductor device 21b and is connected to the terminal RF1 of the semiconductor device 21b.

[0102] The semiconductor devices 21a and 21b are shown in FIG. Figure 5 The described configuration has terminals facing opposite to each other and has a reference Figure 4 The relationship between the input (voltages of the terminals LS, V1, and V2) and the output (control signals SC1, SC2, SC3, and SC4) described above. Therefore, the group of the terminal RF4 of the semiconductor device 21a and the terminal RF1 of the semiconductor device 21b connected to each other via the delay circuit 12d is located outside the group of the terminal RF3 of the semiconductor device 21a and the terminal RF2 of the semiconductor device 21b connected to each other via the delay circuit 12c. As a result, the wiring W15 and the wiring W17 can be extended from the terminal RF3 of the semiconductor device 21a to the input end of the delay circuit 12c without crossing, and the wiring W17 and the wiring W15 can be extended from the terminal RF4 of the semiconductor device 21a to the input end of the delay circuit 12d without crossing. Furthermore, the wiring W16 and the wiring W18 can extend from the output end of the delay circuit 12c to the terminal RF2 of the semiconductor device 21b without crossing each other, and the wiring W18 and the wiring W16 can extend from the output end of the delay circuit 12d to the terminal RF1 of the semiconductor device 21b without crossing each other.

[0103] The shapes of the wirings W15 and W17 along the XY plane may have any shape as long as there is no intersection. The shapes of the wirings W16 and W18 along the XY plane may have any shape as long as there is no intersection. Figure 6 Although an example in which each of the wirings W15 , W16 , W17 , and W18 has an L-shape is shown, one or more of the wirings W15 , W16 , W17 , and W18 may be bent at two or more locations.

[0104] One end of the wiring W7 overlaps with the terminal V1 of the semiconductor device 21a and is connected to the terminal V1 of the semiconductor device 21a. The other end of the wiring W7 overlaps with the terminal V2 of the semiconductor device 21b and is connected to the terminal V2 of the semiconductor device 21b. Through the wiring W7, the terminal V1 of the semiconductor device 21a and the terminal V2 of the semiconductor device 21b receive the same voltage.

[0105] One end of the wiring W8 overlaps with the terminal V2 of the semiconductor device 21a and is connected to the terminal V2 of the semiconductor device 21a. The other end of the wiring W8 overlaps with the terminal V1 of the semiconductor device 21b and is connected to the terminal V1 of the semiconductor device 21b. Through the wiring W8, the terminal V2 of the semiconductor device 21a and the terminal V1 of the semiconductor device 21b receive the same voltage.

[0106] The semiconductor device 21 has a reference Figure 4 The relationship between the input (voltages of terminals LS, V1 and V2) and the output (control signals SC1, SC2, SC3 and SC4) described above. Therefore, regarding the connection between terminal V1 and terminal V2, Figure 2 The configuration is realized by connecting the terminal V2 of the semiconductor device 21a to the terminal V1 of the semiconductor device 21b and connecting the terminal V1 of the semiconductor device 21a to the terminal V2 of the semiconductor device 21b. Figure 5 The described configuration has terminals, and they face opposite directions. Therefore, regarding the positional relationship between the terminal V1 and the terminal V2 in the Y direction, the terminal V2 of the semiconductor device 21a and the terminal V1 of the semiconductor device 21b connected to each other are located on the same side (the -Y direction side), and the terminal V1 of the semiconductor device 21a and the terminal V2 of the semiconductor device 21b connected to each other are located on the same side (the +Y direction side). As a result, the wiring W7 and the wiring W8 can be extended from the terminal V1 of the semiconductor device 21a to the terminal V2 of the semiconductor device 21b without crossing, and the wiring W8 and the wiring W7 can be extended from the terminal V2 of the semiconductor device 21a to the terminal V1 of the semiconductor device 21b without crossing.

[0107] The wiring W7 and the wiring W8 may have any shape as long as there is no intersection between the shapes along the XY plane. Figure 6 Although the example in which the wiring W7 and the wiring W8 each have a shape in which two L shapes are connected is shown, one or both of the wiring W7 and the wiring W8 may be bent at three or more locations.

[0108] By reference Figure 6 The configuration and connection described above are such that between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b, according to Figure 4 As can be seen and described below, a signal path that is dynamically determined is formed based on the voltages applied to the terminals V1 and V2. As described above, the terminal LS of the semiconductor device 21a is connected to the terminal TGND, and the terminal LS of the semiconductor device 21b is connected to the terminal TVDD. Therefore, it is noted that the terminal LS in the semiconductor device 21a receives the ground voltage GND, and the terminal LS in the semiconductor device 21b receives the power supply voltage VDD.

[0109] When the semiconductor device 21a receives a "0" voltage at both terminals V1 and V2, in the semiconductor device 21a, the control signal SC1 has an on-level, and the terminal RFC is connected to the terminal RF1. Since the semiconductor device 21a receives a "0" voltage at both terminals V1 and V2, the semiconductor device 21b receives a "0" voltage at both terminals V1 and V2. As a result, in the semiconductor device 21b, the control signal SC4 has an on-level, and the terminal RFC is connected to the terminal RF4. Therefore, between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b, a signal path is formed via the wiring W11, the delay circuit 12a, and the wiring W12. The signal path via the group of the wiring W13, the delay circuit 12b, and the wiring W14, the signal path via the group of the wiring W15, the delay circuit 12c, and the wiring W16, and the signal path via the group of the wiring W17, the delay circuit 12d, and the wiring W18 are not formed.

[0110] In the case where the semiconductor device 21a receives a "0" voltage in the terminal V1 and a "1" voltage in the terminal V2, in the semiconductor device 21a, the control signal SC2 has an on-level, and the terminal RFC is connected to the terminal RF2. Since the semiconductor device 21a receives a "0" voltage in the terminal V1 and a "1" voltage in the terminal V2, the semiconductor device 21b receives a "1" voltage in the terminal V1 and a "0" voltage in the terminal V2. Thus, in the semiconductor device 21b, the control signal SC3 has an on-level, and the terminal RFC is connected to the terminal RF3. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W13, the delay circuit 12b, and the wiring W14. A signal path through the group of wiring W11, delay circuit 12a, and wiring W12, a signal path through the group of wiring W15, delay circuit 12c, and wiring W16, and a signal path through the group of wiring W17, delay circuit 12d, and wiring W18 are not formed.

[0111] In the case where the semiconductor device 21a receives a "1" voltage in the terminal V1 and a "0" voltage in the terminal V2, in the semiconductor device 21a, the control signal SC3 has an on-level, and the terminal RFC is connected to the terminal RF3. Since the semiconductor device 21a receives a "1" voltage in the terminal V1 and a "0" voltage in the terminal V2, the semiconductor device 21b receives a "0" voltage in the terminal V1 and a "1" voltage in the terminal V2. Thus, in the semiconductor device 21b, the control signal SC2 has an on-level, and the terminal RFC is connected to the terminal RF2. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W15, the delay circuit 12c, and the wiring W16. A signal path through the group of wiring W11, delay circuit 12a, and wiring W12, a signal path through the group of wiring W13, delay circuit 12b, and wiring W14, and a signal path through the group of wiring W17, delay circuit 12d, and wiring W18 are not formed.

[0112] When the semiconductor device 21a receives a "1" voltage at both terminals V1 and V2, in the semiconductor device 21a, the control signal SC4 has an on-level, and the terminal RFC is connected to the terminal RF4. Since the semiconductor device 21a receives a "1" voltage at both terminals V1 and V2, the semiconductor device 21b receives a "1" voltage at both terminals V1 and V2. As a result, in the semiconductor device 21b, the control signal SC1 has an on-level, and the terminal RFC is connected to the terminal RF1. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W17, the delay circuit 12d, and the wiring W18. A signal path via the group of the wiring W11, the delay circuit 12a, and the wiring W12, a signal path via the group of the wiring W13, the delay circuit 12b, and the wiring W14, and a signal path via the group of the wiring W15, the delay circuit 12c, and the wiring W16 are not formed.

[0113] According to the first embodiment, as described below, a switch device having simple internal connections can be provided.

[0114] As in the first embodiment, a switch device having the same function as the switch device 4 can be realized by using the same two semiconductor devices. In this case, the same inputs of the two semiconductor devices need to be connected to each other according to the logic operation performed by the semiconductor device on the input (equivalent to the voltages of the terminals V1 and V2 in the first embodiment). That is, a semiconductor device having the same terminals as the semiconductor device 21 and performing a logic operation different from that performed by the semiconductor device 21 can be substituted for the semiconductor device 21. Figure 6 The semiconductor device 21 of FIG. 2 is used. Moreover, the terminals V1 of the two semiconductor devices are connected to each other, and the terminals V2 of the two semiconductor devices are connected to each other. Since the semiconductor devices 21 face oppositely and are opposite to each other at the sides of the terminals V1 and V2, the arrangement order of the terminals V1 and V2 in the +Y direction of the semiconductor device 21a is different from the arrangement order of the terminals V1 and V2 in the +Y direction of the semiconductor device 21b. Therefore, the wiring connecting the terminals V1 to each other and the wiring connecting the terminals V2 to each other need to cross. In order to make the wiring cross, it is necessary to have a through hole inside the printed wiring substrate. However, the manufacture of this structure is complicated.

[0115] According to the first embodiment, the switch device 4 includes two identical semiconductor devices 21a and 21b that realize the switch circuit 11 and connect the terminal RFC to the terminal RF1, RF2, RF3 or RF4 based on the combination of the voltages of the terminals V1 and V2. When the semiconductor device 21 receives a "0" voltage at the terminal V1 and a "1" voltage at the terminal V2, the semiconductor device 21a connects the terminal RFC to the terminal RF2, and the semiconductor device 21b connects the terminal RFC to the terminal RF3. When the semiconductor device 21 receives a "1" voltage at the terminal V1 and a "0" voltage at the terminal V2, the semiconductor device 21a connects the terminal RFC to the terminal RF3, and the semiconductor device 21b connects the terminal RFC to the terminal RF2. Moreover, the semiconductor devices 21a and 21b face opposite to each other and are opposite to each other on the sides of the terminals V1 and V2, the terminal V1 of the semiconductor device 21a is connected to the terminal V2 of the semiconductor device 21b, and the terminal V2 of the semiconductor device 21a is connected to the terminal V1 of the semiconductor device 21b. Thus, as long as a signal path from the terminal RF2 of the semiconductor device 21a to the terminal RF3 of the semiconductor device 21b and a signal path from the terminal RF3 of the semiconductor device 21a to the terminal RF2 of the semiconductor device 21b are formed, two signal paths can be selected by applying a "0" voltage to the terminal V1 of the semiconductor device 21a and a "1" voltage to the terminal V2 of the semiconductor device 21a, or by applying a "1" voltage to the terminal V1 of the semiconductor device 21a and a "0" voltage to the terminal V2 of the semiconductor device 21a. Therefore, by using two identical devices, a switch device 4 for switching two signal paths is realized.

[0116] Furthermore, as described above, when the semiconductor device 21 receives different voltages at the terminals V1 and V2, the semiconductor device 21a selects the terminal RF2 and the semiconductor device 21b selects the terminal RF3, or the semiconductor device 21a selects the terminal RF3 and the semiconductor device 21b selects the terminal RF2. To achieve this operation, the terminal V1 of the semiconductor device 21a is connected to the terminal V2 of the semiconductor device 21b, and the terminal V2 of the semiconductor device 21a is connected to the terminal V1 of the semiconductor device 21b. Thus, the wirings W7 and W8 do not need to cross each other. Therefore, a switch device 4 with simple internal connections can be realized.

[0117] 2. Second Implementation

[0118] The second embodiment is based on the first embodiment and is related to the arrangement of the terminal TVDD.

[0119] Figure 7FIG. 4B is an example of a structure of a switch circuit of a switch device according to the second embodiment. The switch circuit 11 of the switch device 4B according to the second embodiment is implemented as a semiconductor device 21B. Figure 7 As shown, the terminal TVDD is disposed between the terminal V1 and the terminal V2 .

[0120] Figure 8 FIG. 1 shows an example of a part of the structure of the switch device according to the second embodiment, and shows the arrangement of the components of the switch device along the XY plane. Figure 8 As shown, based on the configuration of terminal TVDD between terminal V1 and terminal V2, terminal V1 and terminal V2 are not adjacent but have a gap. According to the configuration of terminal V1 and terminal V2, terminal V1 of semiconductor device 21Ba and terminal V2 of semiconductor device 21Bb are arranged in the +X direction, and terminal V2 of semiconductor device 21Ba and terminal V1 of semiconductor device 21Bb are arranged in the +X direction. Figure 8 The above example is shown. Figure 8 In the configuration shown as an example in FIG. 1 , the wirings W7B and W8B in the second embodiment have a straight line shape.

[0121] The switch device 4B further includes a wiring W21. The wiring W21 is a conductor having a linear shape and is arranged on the upper surface of the printed wiring substrate 23. One end of the wiring W21 overlaps with the terminal TVDD of the semiconductor device 21a and is connected to the terminal TVDD of the semiconductor device 21a. The other end of the wiring W21 overlaps with the terminal TVDD of the semiconductor device 21b and is connected to the terminal TVDD of the semiconductor device 21b. In one example, the wiring W21 has a shape formed by connecting two L shapes.

[0122] According to the second embodiment, the same advantages as those of the first embodiment can be obtained. In addition, according to the second embodiment, the terminal TVDD is arranged between the terminal V1 and the terminal V2. Therefore, the wiring W21 can be arranged without crossing the wiring W7B and W8B. Thus, the switch device 4B with simple internal connection can be realized.

[0123] 3. Third Implementation

[0124] The third embodiment is based on the second embodiment, but is different from the second embodiment in the positions of the terminals V1 and V2.

[0125] Fig. 9 FIG. 4 is an example of a structure of a switch circuit of a switch device according to the third embodiment. The switch circuit 11 of a switch device 4C according to the third embodiment is implemented as a semiconductor device 21C. Fig. 9As shown, terminals V1 and V2 face the first side L1 and sandwich terminal RFC. In one example, terminal V1 is located closest to the +Y direction end among the terminals arranged along the first side L1, and terminal V2 is located closest to the -Y direction end among the terminals arranged along the first side L1.

[0126] Fig.10 FIG. 1 is a diagram showing an example of a part of the structure of the switch device according to the third embodiment, and shows the arrangement of the components of the switch device along the XY plane. Fig.10 As shown, the switch device 4C does not include the wirings W7B and W8B but includes the wirings W24 and W25 . The wirings W24 and W25 are linear conductors and are arranged on the upper surface of the printed wiring board 23 .

[0127] One end of the wiring W24 overlaps with the terminal V1 of the semiconductor device 21Ca and is connected to the terminal V1 of the semiconductor device 21Ca. The other end of the wiring W24 overlaps with the terminal V2 of the semiconductor device 21Cb and is connected to the terminal V2 of the semiconductor device 21Cb. The wiring W24 is located outside the region formed by the group of semiconductor devices 21Ca and 21Cb, and is arranged closer to the +Y direction than the wiring W11, the delay circuit 12a, and the wiring W12.

[0128] One end of the wiring W25 overlaps with the terminal V2 of the semiconductor device 21Ca and is connected to the terminal V2 of the semiconductor device 21Ca. The other end of the wiring W25 overlaps with the terminal V1 of the semiconductor device 21Cb and is connected to the terminal V1 of the semiconductor device 21Cb. The wiring W25 is located outside the region formed by the group of semiconductor devices 21Ca and 21Cb, and is arranged in the -Y direction relative to the wiring W17, the delay circuit 12d, and the wiring W18.

[0129] According to the third embodiment, the same advantages as those of the first and second embodiments can be obtained. In addition, according to the third embodiment, the terminals V1 and V2 face the first side L1 and sandwich the terminal RFC. Thus, the terminals V1 and V2 are not located in the area surrounded by the semiconductor devices 21Ca and 21Cb, the wirings W11, W12, W17 and W18, and the delay circuits 12a and 12d. Therefore, the wiring connecting the terminal V1 of the semiconductor device 21Ca to the control circuit 13 and the wiring connecting the terminal V2 of the semiconductor device 21Ca to the control circuit 13 do not need to cross any of the wirings W11, W12, W13, W14, W15, W16, W17 and W18. Therefore, the signals transmitted in the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are not affected by the voltage transmitted in the wiring connecting the terminal V1 of the semiconductor device 21Ca and the control circuit 13 and the wiring connecting the terminal V2 of the semiconductor device 21Ca and the control circuit 13. In other words, the signals transmitted in the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are suppressed from being affected by noise.

[0130] 4. Fourth Implementation

[0131] The fourth embodiment is based on the third embodiment, but is different from the third embodiment in the position of the terminal TVDD.

[0132] Fig.11 FIG. 2 shows an example of a structure of a switch circuit of a switch device according to the fourth embodiment. The switch circuit 11 of the switch device 4D according to the fourth embodiment is implemented as a semiconductor device 21D. Fig.11 As shown, the semiconductor device 21D includes a terminal TVDD2. The terminal TVDD2 is connected to the terminal TVDD inside the switch device 4D. The terminals TVDD and TVDD2 face the first side L1. The terminal TVDD is arranged between the terminal RFC and the terminal V2. The terminal TVDD2 is arranged between the terminal V1 and the terminal RFC. The position of the terminal TVDD and the position of the terminal TVDD2 can also be interchanged.

[0133] Fig.12 FIG. 1 shows an example of a part of the structure of the switch device according to the fourth embodiment, and shows the arrangement of the components of the switch device along the XY plane. Fig.12 As shown, the switch device 4D does not include the wirings W2 and W21 but includes wirings W27 and W29 . The wirings W27 and W29 are linear conductors and are arranged on the upper surface of the printed wiring board 23 .

[0134] The wiring W27 is arranged between the printed wiring substrate 23 and the semiconductor device 21Db. One end of the wiring W27 overlaps with and is connected to the terminal LS of the semiconductor device 21Db. The other end of the wiring W27 overlaps with and is connected to the terminal TVDD of the semiconductor device 21Db.

[0135] One end of the wiring W29 overlaps with the terminal TVDD of the semiconductor device 21Da and is connected to the terminal TVDD of the semiconductor device 21Da. The other end of the wiring W29 overlaps with the terminal TVDD2 of the semiconductor device 21Db and is connected to the terminal TVDD2 of the semiconductor device 21Db. The wiring W29 is located outside the region formed by the group of semiconductor devices 21Da and 21Db, and is arranged closer to the -Y direction than the wiring W25.

[0136] The wiring W29 may be connected to the terminal TVDD2 of the semiconductor device 21Da and the terminal TVDD of the semiconductor device 21Db. In this case, the wiring W29 is located outside the region formed by the combination of the semiconductor devices 21Da and 21Db and is arranged closer to the +Y direction than the wiring W24.

[0137] According to the fourth embodiment, the same advantages as those of the first to third embodiments can be obtained. In addition, the semiconductor device 21D of the fourth embodiment includes a terminal TVDD2, and the terminals TVDD and TVDD2 face the first side L1. Thus, in the switch device 4D, the terminals TVDD and TVDD2 are not located in the area surrounded by the semiconductor devices 21Da and 21Db, the wirings W11, W12, W17 and W18, and the delay circuits 12a and 12d. Therefore, the signal transmitted in the wirings W11, W12, W13, W14, W15, W16, W17 and W18 is not affected by the voltage transmitted in the wiring connecting the terminal TVDD of the semiconductor device 21Da to the control circuit 13. That is, the signal transmitted in the wirings W11, W12, W13, W14, W15, W16, W17 and W18 is suppressed from being affected by noise.

[0138] The terminal TVDD2 and the terminal V1 may be interchanged, and the terminal TVDD and the terminal V2 may be interchanged. In this case, the wiring W25 is arranged in the -Y direction of the wiring W29.

[0139] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A switch device comprising: A first semiconductor device and a second semiconductor device, each of the first semiconductor device and the second semiconductor device comprising a first side, a second side and a third side opposite to each other, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal arranged along the first side, and a sixth terminal, the first terminal being connected to the second terminal during a period when the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage, and the first terminal is connected to the third terminal during a period when the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage; a first delay circuit for supplying a signal obtained by delaying a signal at an input terminal connected to the second terminal of the first semiconductor device to the third terminal of the second semiconductor device; a first conductor connecting the fourth terminal of the first semiconductor device and the fifth terminal of the second semiconductor device; as well as a second conductor connecting the fifth terminal of the first semiconductor device and the fourth terminal of the second semiconductor device, The first side of the first semiconductor device is opposite to the first side of the second semiconductor device, The sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage, The sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage.

2. A switch device comprising: A first semiconductor device and a second semiconductor device, each of the first semiconductor device and the second semiconductor device comprising a first side, a second side and a third side opposite to each other, a fourth side opposite to the first side, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal arranged along the first side, and a sixth terminal, the first terminal being connected to the second terminal during a period when the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage, and the first terminal is connected to the third terminal during a period when the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage; a first delay circuit for supplying a signal obtained by delaying a signal at an input terminal connected to the second terminal of the first semiconductor device to the third terminal of the second semiconductor device; a first conductor connecting the fourth terminal of the first semiconductor device and the fifth terminal of the second semiconductor device; as well as a second conductor connecting the fifth terminal of the first semiconductor device and the fourth terminal of the second semiconductor device, The fourth side of the first semiconductor device is opposite to the fourth side of the second semiconductor device, The sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage, The sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage.

3. The switch device according to claim 2, The first semiconductor device and the second semiconductor device each further include a ninth terminal, the ninth terminal facing the fourth side and receiving the fourth voltage, The switch device further includes a third conductor connecting the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device.

4. The switch device according to claim 2, The first semiconductor device and the second semiconductor device each further include a ninth terminal, the ninth terminal facing the first side and receiving the fourth voltage, The switch device further includes a third conductor connecting the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device.

5. The switch device according to claim 1 or 2, further comprising a second delay circuit for supplying a signal obtained by delaying a signal at an input terminal connected to the third terminal of the first semiconductor device to the second terminal of the second semiconductor device, In each of the first semiconductor device and the second semiconductor device, During a period when the sixth terminal receives the first voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage, the first terminal is connected to the third terminal, The first terminal is connected to the second terminal during a period in which the sixth terminal receives the fourth voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the third voltage.

6. The switch device according to claim 5, Each of the first semiconductor device and the second semiconductor device further includes a seventh terminal facing the second side and an eighth terminal facing the third side. The first terminal is connected to the seventh terminal during a period when the sixth terminal receives the first voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the second voltage, and during a period when the sixth terminal receives the fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the third voltage, The first terminal is connected to the eighth terminal during a period when the sixth terminal receives the first voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the third voltage, and during a period when the sixth terminal receives the fourth voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the second voltage.

7. The switch device according to claim 6, further comprising: a third delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the seventh terminal of the first semiconductor device to the eighth terminal of the second semiconductor device; and The fourth delay circuit supplies a signal obtained by delaying a signal at an input terminal connected to the eighth terminal of the first semiconductor device to the seventh terminal of the second semiconductor device.

8. The switch device according to claim 1, The first semiconductor device and the second semiconductor device each further include a ninth terminal, the ninth terminal receiving the fourth voltage and arranged between the fourth terminal and the fifth terminal, The switch device further includes a third conductor connecting the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device.

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