Memory and preparation method thereof

Abstract

The invention relates to a memory and a preparation method thereof, and the memory comprises a memory material structure, bit lines, word lines and a plurality of active columns, wherein the bit lines and the word lines are located in a substrate, and the active columns extend in a first direction and are arranged in multiple rows and multiple columns in a second direction and a third direction; the second direction and the third direction intersect and are perpendicular to the first direction; the memory material structures are arranged corresponding to the plurality of active columns and are positioned on the top surfaces of the active columns; the bit lines are located under the active columns and extend in the third direction, and the bit lines are arranged at intervals in the second direction; the word line is located between the bit line and the memory material structure, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active columns. The integration level, the performance and the reliability of the memory can be improved at least under the condition that the performance of a semiconductor device is not reduced, and the complexity of a preparation process and the complexity of read-write control are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a memory and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements for the integration, performance and reliability of integrated circuits. The use of vertical channel transistors can reduce the cross-sectional area of ​​transistors while ensuring that the performance of semiconductor devices is not reduced, thereby improving the integration of integrated circuits.

[0003] However, in the related memory structure, an isolation structure needs to be prepared between the word lines connected to the vertical channel transistors, which increases the complexity of the memory preparation process; and multiple word lines need to be controlled separately, which increases the complexity of memory read and write control; if a leakage channel appears between adjacent word lines, it will seriously affect the performance and reliability of the memory. Summary of the invention

[0004] Based on this, it is necessary to provide a memory and a method for preparing the same in response to the problems in the above-mentioned background technology, which can at least improve the integration, performance and reliability of the memory while ensuring that the performance of the semiconductor device is not reduced, and reduce the complexity of the preparation process and the complexity of the read-write control.

[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a memory, including a memory material structure, and a bit line, a word line and a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction in a substrate; the second direction intersects with the third direction and is perpendicular to the first direction; the memory material structure is arranged corresponding to the plurality of active pillars and is located on the top surface of the active pillar; the bit line is located directly below the active pillar and extends along the third direction, and the bit line is arranged at intervals along the second direction; the word line is located between the bit line and the memory material structure, extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars.

[0006] The memory in the above embodiment is provided with a bit line located in the substrate directly below the active pillar and extending along the third direction, so that the memory cells on the active pillars adjacent to each other along the third direction share a bit line extending along the third direction; a memory material structure for non-volatile storage is provided on the top surface of the active pillar, and a word line extending along the second direction and the third direction and circumferentially surrounding multiple active pillars is provided between the bit line and the memory material structure, so that a conductive line extending along the second direction is provided on the top surface of the memory material structure adjacent to each other along the second direction, so that a memory material structure is selected through the conductive line extending along the second direction and the bit line extending along the third direction, so as to realize one-by-one control of the memory cells in a memory array of a layer in the memory. Since the word line extends along the second direction and the third direction, and multiple active pillars penetrate the word line along the first direction, the process step of preparing the word line isolation structure between the word lines of the same layer is avoided, thereby effectively reducing the complexity of the preparation process of the memory; since in the data read and write control method of the memory, the control step of scanning the word line one by one is relatively reduced, thereby effectively reducing the complexity of the read and write control of the memory.

[0007] In some embodiments, the memory further includes a gate dielectric layer, which is located between the active pillar and the word line and circumferentially surrounds the active pillar.

[0008] In some embodiments, the memory further includes a first doping region, a channel region, and a second doping region sequentially distributed on the active pillar along a first direction; and the gate dielectric layer circumferentially surrounds the channel region.

[0009] In some embodiments, the memory material structure includes a memory material layer and a conductive layer between the memory material layer and the active pillar.

[0010] In some embodiments, the memory material layer includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material, or a combination thereof.

[0011] In some embodiments, the memory further includes a word line capping layer, which is located on a top surface of the word line, extends along the second direction and the third direction, and circumferentially surrounds the plurality of active pillars.

[0012] In some embodiments, the memory further includes an isolation layer, which is located between memory material structures adjacent to each other along the second direction and the third direction and is located on a top surface of the word line capping layer.

[0013] In some embodiments, the memory also includes a conductive wire and a conductive plug arranged corresponding to the memory material structure, the conductive plug is located on the top surface of the corresponding memory material structure; the conductive wire extends along the second direction and is electrically connected to the conductive plug directly below it; wherein, the conductive wires adjacent to each other along the third direction are insulated from each other via an insulating structure located on the top surface of the isolation layer.

[0014] In some embodiments, a bottom surface dimension of the conductive plug is smaller than a top surface dimension of the conductive plug.

[0015] A second aspect of the present disclosure provides a method for preparing a memory, comprising: providing a substrate, the substrate comprising a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction, the second direction intersecting with the third direction and both being perpendicular to the first direction; forming bit lines extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillars; forming word lines extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars; and forming a one-to-one memory material structure on the top surfaces of the plurality of active pillars.

[0016] In the above-mentioned embodiment, the method for preparing the memory is as follows: after forming a plurality of active pillars extending along the first direction and arranged in multiple rows and columns along the second direction and the third direction in the substrate, the second direction intersects with the third direction and is perpendicular to the first direction; forming a bit line extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillar; then forming a word line extending along the second direction and the third direction and surrounding the plurality of active pillars in a circumferential direction; and then forming a one-to-one memory material structure on the top surface of the plurality of active pillars, so as to facilitate selecting a memory material structure through the conductive line extending along the second direction and the bit line extending along the third direction, so as to realize one-by-one control of the memory cells in a memory array of a layer in the memory. Since the word line extends along the second direction and the third direction and surrounds the plurality of active pillars in a circumferential direction, the process step of preparing the word line isolation structure between the word lines in the same layer is avoided, thereby effectively reducing the complexity of the preparation process of the memory; since in the data read and write control method of the memory, the control step of scanning the word line one by one is relatively reduced, thereby effectively reducing the complexity of the read and write control of the memory.

[0017] In some embodiments, providing a substrate includes: providing an initial substrate, in which a plurality of active walls are formed and arranged along the second direction and spaced apart by first initial isolation structures, and the active walls extend along the third direction;

[0018] A plurality of intermediate grooves extending along the second direction and arranged at intervals along the third direction are formed in the initial substrate to isolate the active wall into a plurality of active pillars, and the remaining initial substrate is used to form a substrate; the bottom surface of the intermediate groove is higher than the bottom surface of the first initial isolation structure.

[0019] In some embodiments, providing a substrate includes: providing an initial substrate, in which a plurality of active walls are formed along a second direction and are arranged at intervals by a first initial isolation structure, and the active walls extend along a third direction; a plurality of intermediate grooves are formed in the initial substrate, extending along the second direction and arranged at intervals along the third direction, and the active walls are isolated into a plurality of active pillars, and the remaining initial substrate is used to constitute a substrate; the bottom surface of the intermediate groove is higher than the bottom surface of the first initial isolation structure.

[0020] In some embodiments, forming the bit line includes: implanting ions into the substrate directly below the active pillar through the middle trench to form the bit line extending along the third direction.

[0021] In some embodiments, forming a word line includes: forming an isolation material in a middle trench; etching back the isolation material and the first initial isolation structure to form a word line trench extending along a second direction and a third direction and circumferentially surrounding a plurality of active pillars; and forming a word line in the word line trench.

[0022] In some embodiments, the active pillar includes a first doped region, a channel region, and a second doped region sequentially distributed along a first direction; a gate dielectric layer circumferentially surrounding the channel region is included between the channel region and the word line; a word line is formed in a word line groove, including: forming a gate dielectric layer during or after etching back the isolation material and the first initial isolation structure.

[0023] In some embodiments, after forming the word line and before forming the memory material structure, the method includes: forming a word line capping layer on the top surface of the word line, wherein the top surface of the word line capping layer is not lower than the top surface of the substrate; the word line capping layer extends along the second direction and the third direction and circumferentially surrounds a plurality of active pillars; an isolation layer is formed between adjacent memory material structures along the second direction and the third direction; after forming the memory material structure, the method also includes: forming a conductive plug on the top surface of the memory material structure; forming a conductive line extending along the second direction, and an insulating structure located between adjacent conductive lines along the third direction; and the conductive line electrically connects the conductive plug directly thereunder. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 Shown is a schematic top view of an array area of ​​a memory provided in one embodiment of the present disclosure;

[0026] Figure 2 It is shown as a memory provided in one embodiment of the present disclosure. Figure 1 Schematic diagram of the cross-sectional structure obtained in the aa' direction, bb' direction, cc' direction and dd' direction shown in ;

[0027] Figure 3 Shown is a schematic flow chart of a method for preparing a memory provided in an embodiment of the present disclosure;

[0028] Figure 4-Figure 10The three-dimensional structure obtained in different steps of a method for preparing a memory provided in an embodiment of the present disclosure is shown. Figure 1 Schematic diagram of the cross-sectional structure obtained in the aa' direction, bb' direction, cc' direction and dd' direction shown in ;

[0029] Fig.11 Shown is a schematic diagram of a three-dimensional structure of a memory provided in an embodiment of the present disclosure;

[0030] Fig.12 Display as Fig.11 Schematic diagram of the longitudinal section of an active column.

[0031] Description of reference numerals:

[0032] 100', initial substrate; 100, substrate; 101, first trench; 10', first initial isolation structure; 10, first isolation structure; 11', second initial isolation structure; 11, second isolation structure; 20, active wall; 31, middle trench; 32, isolation material; 33, word line trench; 341, gate dielectric layer; 51, interlayer conductive layer; 52, main conductive layer; 50, word line; 21, active pillar; 211, channel region; 40, bit line; 501, word line isolation structure; 60, word line cap layer; 71, conductive layer; 72, memory material layer; 70, memory material structure; 701, isolation layer; 702, interlayer dielectric layer; 80, conductive plug; 90, conductive line; 91, insulating structure. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0039] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0040] Please note that the mutual insulation between the two described in the embodiments of the present disclosure includes but is not limited to at least one of the presence of insulating material, insulating atmosphere or gap between the two.

[0041] See also Figure 1-Figure 2 , Figure 1 The schematic diagram of a top view of a dynamic random access memory (DRAM) array area is shown in FIG. The array area includes a plurality of storage cells. Specifically, each storage cell in the array area includes a capacitor and a transistor. The gate of the transistor is connected to a word line 50, the drain of the transistor is connected to a bit line 40, and the source of the transistor is connected to a capacitor (not shown). The opening and closing of the transistor is controlled by a voltage signal on the word line 50, and then the data information stored in the capacitor is read through the bit line 40, or the data information is written into the capacitor for storage through the bit line 40.

[0042] See also Figure 2 , Figure 2 For Figure 1The cross-sectional structure schematic diagram obtained along the aa' direction, bb' direction, cc' direction and dd' direction in the direction perpendicular to the substrate is shown in the figure. The word line 50 extends along the cc' direction / dd' direction, and the adjacent word lines 50 along the aa' direction / bb' direction are insulated from each other via the word line isolation structure 501. However, with the miniaturization of the structure size of semiconductor devices, the continuous reduction of pattern spacing and the increase in density, the size of the active area has been reduced to below 40nm. The use of vertical gate all around transistor (Vertical Gate All Around transistor, VGAA) can further effectively reduce the cross-sectional area of ​​the memory cell. However, this undoubtedly increases the complexity of preparing different word lines 50 in the same layer. Due to the reduction in the spacing between different word lines 50 in the same layer, the process complexity of preparing the word line isolation structure 501 between different word lines 50 in the same layer increases, which can easily lead to the generation of leakage channels between adjacent word lines 50 in the same layer, thereby reducing the performance and reliability of the prepared memory.

[0043] Based on the above reasons, the embodiments of the present disclosure aim to provide a memory and a method for preparing the same, which can at least improve the integration, performance and reliability of the memory while ensuring that the performance of the semiconductor device is not reduced, and reduce the complexity of the preparation process and the complexity of the read-write control.

[0044] See also Figure 3 In one embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising the following steps:

[0045] Step S20: providing a substrate, wherein the substrate includes a plurality of active pillars extending along a first direction and arranged in a plurality of rows and columns along a second direction and a third direction, wherein the second direction intersects the third direction and is perpendicular to the first direction;

[0046] Step S40: forming bit lines extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillars;

[0047] Step S60: forming a word line extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars;

[0048] Step S80: forming a one-to-one memory material structure on the top surfaces of the plurality of active pillars.

[0049] As an example, see Figure 3After forming a plurality of active pillars extending along a first direction and arranged in multiple rows and columns along a second direction and a third direction in a substrate, the second direction intersects with the third direction and is perpendicular to the first direction; forming a bit line extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillar; then forming a word line extending along the second direction and the third direction and surrounding the plurality of active pillars in a circumferential direction; and then forming a one-to-one memory material structure on the top surface of the plurality of active pillars, so as to facilitate selecting a memory material structure through the conductive line extending along the second direction and the bit line extending along the third direction, so as to realize one-by-one control of the storage cells in a storage array of a layer in the memory. Since the word line extends along the second direction and the third direction and surrounds the plurality of active pillars in a circumferential direction, the process step of preparing the word line isolation structure between the word lines in the same layer is avoided, so that the complexity of the preparation process of the memory is effectively reduced; since in the data read and write control method of the memory, the control step of scanning the word line one by one is relatively reduced, so that the complexity of the read and write control of the memory is effectively reduced.

[0050] Please note that the cross-sectional structural diagrams in the aa' direction, bb' direction, cc' direction and dd' direction shown in the following embodiments are all obtained along the three-dimensional structure obtained in the corresponding process steps. Figure 1 The diagram shows aa', bb', cc' and dd' directions, and a schematic diagram of the cross-sectional structure obtained along the direction perpendicular to the substrate; wherein the first direction is parallel to the vertical substrate direction, the second direction is parallel to the cc' / dd' direction, and the third direction is parallel to the aa' / bb' direction; the vertical substrate direction refers to the direction perpendicular to the top surface of the substrate.

[0051] As an example, see Figure 4-Figure 5 In step S20, providing the substrate 100 includes:

[0052] Step S22: providing an initial substrate 100', in which a plurality of active walls 20 are formed and arranged along the second direction by first initial isolation structures 10', and the active walls 20 extend along the third direction;

[0053] Step S24: forming a plurality of intermediate trenches 31 extending along the second direction and arranged at intervals along the third direction in the initial substrate 100', isolating the active wall 20 into a plurality of active pillars 21, and the remaining initial substrate 100' is used to constitute a substrate; the bottom surface of the intermediate trench 31 is higher than the bottom surface of the first initial isolation structure 10'.

[0054] As an example, see Figure 4The initial substrate 100' provided in step S22 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The initial substrate 100' can be a single-layer structure or a multi-layer structure. For example, the initial substrate 100' can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the initial substrate 100' can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. P-type ions can be implanted into the initial substrate 100' using an ion implantation process to form a first type doped well region (not shown), and the P-type ions can include but are not limited to at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions and indium (In) ions.

[0055] As an example, see Figure 4 In the embodiment where the initial substrate 100' comprises a P-type substrate in step S20, the active wall 20 can be formed by injecting N-type ions; correspondingly, in the embodiment where the silicon substrate comprises an N-type substrate, the active wall 20 can be formed by injecting P-type ions. Accordingly, the active wall 20 can be a P-type active wall 20 or an N-type active wall 20. The P-type active wall 20 can form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, referred to as NMOS) device, and the N-type active wall 20 can form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS) device. The N-type impurity ions can include but are not limited to at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. The concentration of N-type or P-type impurities can be less than or equal to 10 18 cm -3 , such as at about 10 17 cm -3 With about 10 18 cm -3 in the range between.

[0056] As an example, see Figure 4In step S22, a dry etching process may be used to form first grooves 101 arranged in intervals along the second direction and extending along the third direction in the initial substrate 100'. A deposition process may be used to fill at least the first grooves 101 with an isolation material 32, and the isolation material 32 also covers the exposed top surface of the initial substrate 100'. Then, a planarization process may be used to process the top surface of the isolation material 32. The isolation material 32 located in the first groove 101 is used to form a first initial isolation structure 10'. The isolation material retained on the top surface of the initial substrate 100' can prevent subsequent processes from causing contamination or damage to the initial substrate 100'. The deposition process may include, but is not limited to, at least one of a chemical vapor deposition process (CVD), a physical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD). The planarization process may include but is not limited to at least one of a chemical mechanical polishing process, a dry etching process, and a push-on process, etc. The isolation material 32 may be selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, aluminum oxide, etc., and combinations thereof.

[0057] As an example, see Figure 5 In step S24, a dry etching process can be used to form a plurality of intermediate trenches 31 extending along the second direction and arranged at intervals along the third direction in the initial substrate 100', and the active wall 20 is isolated into a plurality of active pillars 21. The remaining initial substrate 100' is used to constitute the substrate 100; the bottom surface of the intermediate trench 31 is higher than the bottom surface of the first initial isolation structure 10', so that the first initial isolation structure 10' can be used to isolate the bit lines prepared subsequently, so that the adjacent bit lines along the second direction are isolated from each other via the first initial isolation structure 10'.

[0058] As an example, see Figure 6 The step S40 of forming the bit line 40 includes:

[0059] Step S42 : implanting ions into the substrate 100 directly below the active pillar 21 through the middle trench 31 to form a bit line 40 extending along the third direction.

[0060] As an example, see Figure 6In step S42, a liner material layer (not shown) may be formed on the bottom surface of the middle trench 31 and the sidewalls opposite to the middle trench 31 along the third direction to protect the active pillar 21 and prevent the active pillar 21 from being damaged or contaminated by doped ions in the subsequent ion implantation process; and then, an ion implantation layer of about 10 Å may be implanted into the substrate 100 below the middle trench 31. 18 cm -3 and 10 19 cm -3 doping ions with a high dopant concentration between; doping ions can use P-type ions. Of course, in other embodiments, doping ions can use N-type ions, and N-type ions have a higher current. Specifically, for example, As and P ions can be used. After at least one, for example, one low-energy high-dose ion implantation, an annealing process can be performed to diffuse the doping ions in the substrate 100 to form a bit line 40 extending along a third direction. Because impurities accumulate at the interface between silicide and silicon due to segregation during the annealing process, the Schottky contact resistance is reduced. By forming a continuous metal silicide as a buried bit line 40 in the substrate 100, the resistance of the bit line 40 is reduced, and the performance of the memory is improved; by forming a VGAA transistor, the size of the memory is effectively reduced and the integration of the memory is improved.

[0061] As an example, see Figure 6-Figure 8 The step S60 of forming the word line 50 includes:

[0062] Step S62: forming an isolation material 32 in the middle trench 31;

[0063] Step S64: etching back the isolation material 32 and the first initial isolation structure 10 ′ to form a word line trench 33 extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars 21 ;

[0064] Step S66 : forming a word line 50 in the word line trench 33 .

[0065] As an example, see Figure 6 After forming the bit line 40, in step S62, a deposition process may be used to fill the isolation material 32 at least in the middle trench 31, and then a planarization process may be used to process the top surface of the isolation material 32. The isolation material 32 in the middle trench 31 is used to form a second initial isolation structure 11', and the bottom surface of the second initial isolation structure 11' is higher than the bottom surface of the first initial isolation structure 10'. The isolation material 32 may be selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, etc. and combinations thereof.

[0066] As an example, see Figure 7In step S64, the first initial isolation structure 10' and the second initial isolation structure 11' can be etched back to form a word line groove 33 whose bottom surface is flush and higher than the top surface of the bit line 40, and the word line groove 33 extends along the second direction and the third direction and circumferentially surrounds the active pillar 21; the remaining first initial isolation structure 10' is used to form the first isolation structure 10; the remaining second initial isolation structure 11' is used to form the second isolation structure 11. The bottom surface of the second isolation structure 11 is higher than the bottom surface of the first isolation structure 10, and the top surface of the second isolation structure 11 is flush with the top surface of the first isolation structure 10 and lower than the bottom surface of the word line prepared later, so as to prepare the word line extending along the second direction and the third direction.

[0067] As an example, see Figure 8 The active pillar 21 includes a first doping region, a channel region 211 and a second doping region sequentially distributed along a first direction; the step S66 of forming a word line 50 in the word line trench 33 includes:

[0068] Step S662 : during or after etching back the first initial isolation structure 10 ′ and the second initial isolation structure 11 ′, a gate dielectric layer 341 circumferentially surrounding the channel region is formed.

[0069] As an example, see Figure 8 In the process of etching back the first initial isolation structure 10' and the second initial isolation structure 11' to form the word line trench 33, a layer of isolation material can be retained on the outer surface of the active pillar 21 as a gate dielectric layer 341 to reduce the process flow of additionally preparing the gate dielectric layer 341. The material of the gate dielectric layer 341 can be silicon oxide.

[0070] As an example, see Figure 8 , the first doping region can be used to form a source, and the second doping region can be used to form a drain. In other embodiments, the first doping region can be used to form a drain, and the second doping region can be used to form a source.

[0071] As an example, see Figure 8 In the process of etching back the first initial isolation structure 10' and the second initial isolation structure 11' to form the word line groove 33, the word line groove 33 exposing the side surface of the active pillar 21 can be formed, and then the side surface of the active pillar 21 can be treated by a thermal oxidation process to form a gate dielectric layer 341 on the side surface of the active pillar 21. Since part of the active pillar 21 can be consumed in the process of thermally oxidizing the side surface of the active pillar 21 to form the gate dielectric layer 341, the spacing between the adjacent gate dielectric layers 341 along the second direction or the third direction is relatively increased, thereby increasing the size of the word line 50 between the adjacent gate dielectric layers 341 along the second direction or the third direction, and reducing the impedance of the word line 50. The material of the gate dielectric layer 341 can be silicon oxide.

[0072] As an example, see Figure 8 After the gate dielectric layer 341 is formed in step S60, an interlayer conductive layer 51 is formed on the bottom surface and sidewall of the word line groove 33, and the interlayer conductive layer 51 also circumferentially surrounds the active pillar 21; then the main conductive layer 52 is filled in the word line groove 33, and the interlayer conductive layer 51 and the main conductive layer 52 are etched back until the top surfaces of the two are lower than the top surface of the active pillar 21 and not lower than the top surface of the channel area 211. For example, the top surfaces of the interlayer conductive layer 51 and the main conductive layer 52 after etching can be set to be flush with the top surface of the channel area 211, and the remaining interlayer conductive layer 51 and the remaining main conductive layer 52 are used to form the word line 50, and the top surface of the word line 50 is not lower than the top surface of the channel area 211. The interlayer conductive layer 51 can be used as a barrier layer. The material of the barrier layer may include TiN, TaN, WN or a combination thereof to prevent the conductive material from diffusing to form a leakage channel during the process of depositing the main conductive layer 52 to prepare the word line 50, thereby improving the performance and reliability of the prepared semiconductor device.

[0073] As an example, see Figure 8 The interlayer conductive layer 51 may be used as a work function layer, and the work function layer includes one or more layers of conductive materials, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. The main conductive layer 52 may include W, Cu, Ti, Al, Co or a combination thereof.

[0074] As an example, see Fig. 9 , after forming the word line 50 and before forming the memory material structure 70, comprising:

[0075] Step S72 : forming a word line capping layer 60 on the top surface of the word line 50 , wherein the top surface of the word line capping layer 60 is not lower than the top surface of the active pillar 21 ; the word line capping layer 60 extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars 21 .

[0076] As an example, see Figure 8 In step S72, a deposition process may be used to form a word line capping layer 60 on the top surface of the word line 50, the top surface of which is not lower than the top surface of the active pillar 21. The material of the word line capping layer 60 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or a combination thereof.

[0077] As an example, see Fig. 9 In step S80, a one-to-one memory material structure 70 is formed on the top surface of the plurality of active pillars 21, including:

[0078] Step S81: after forming the word line capping layer 60, forming an isolation material layer (not shown) covering the word line capping layer 60, the isolation material layer extending along the second direction and the third direction;

[0079] Step S82: patterning the isolation material layer to obtain a first through hole (not shown) located directly above the active pillar 21, the first through hole and the active pillar 21 are arranged one-to-one; the remaining isolation material layer is used to form the isolation layer 701;

[0080] Step S83: removing the isolation material 32 on the top surface of the active pillar 21 through the first through hole;

[0081] Step S84: forming a conductive layer 71 on the top surface of the active pillar 21 in the first through hole, wherein the conductive layer 71 covers the exposed top surface of the active pillar 21;

[0082] Step S85 : forming a memory material layer 72 on the exposed top surface of the conductive layer 71 in the first through hole. The conductive layer 71 and the memory material layer 72 are used to together constitute a memory material structure 70 .

[0083] As an example, see Fig. 9 In step S82, a wet etching process may be used to remove the isolation material 32 on the top surface of the active pillar 21 to expose the top surface of the active pillar 21; in step S84, a deposition process may be used to form a conductive layer 71 on the exposed top surface of the active pillar 21, and the conductive layer 71 covers the exposed top surface of the active pillar 21; in step S86, a deposition process may be used to form a memory material layer 72 on the exposed top surface of the conductive layer 71, and the conductive layer 71 and the memory material layer 72 are used to jointly constitute a memory material structure 70. The material of the conductive layer 71 may include but is not limited to titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof; the material of the memory material layer 72 may include but is not limited to a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material or a combination thereof.

[0084] As an example, see Fig. 9 In step S80 , a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process may also be used to form a one-to-one memory material structure 70 on the top surfaces of the plurality of active pillars 21 .

[0085] As an example, see Fig.10 , an isolation layer 701 is formed between adjacent memory material structures 70 along the second direction and the third direction; after forming the memory material structure 70, the method further includes:

[0086] Step S92: forming a conductive plug 80 on the top surface of the memory material structure 70;

[0087] Step S94: forming conductive lines 90 extending along the second direction and insulating structures 91 located between adjacent conductive lines 90 along the third direction; the conductive lines 90 are electrically connected to the conductive plugs 80 directly thereunder.

[0088] As an example, see Fig.10 In step S94, a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process can be used to form a conductive line 90 extending along the second direction, and the conductive lines 90 adjacent to each other along the third direction are insulated from each other via an insulating structure 91.

[0089] As an example, see Fig.10 In step S92, a conductive plug 80 is formed on the top surface of the memory material structure 70, including:

[0090] Step S921: forming an interlayer dielectric material layer (not shown), the interlayer dielectric material layer covers the isolation layer 701 and extends along the second direction and the third direction;

[0091] Step S922: patterning the interlayer dielectric material layer to obtain a second through hole (not shown) located directly above the active pillar 21, the second through hole and the active pillar 21 are arranged one-to-one; the remaining interlayer dielectric material layer is used to form the interlayer dielectric layer 702; the top surface opening size of the second through hole is larger than the bottom surface opening size of the second through hole;

[0092] Step S923: forming a conductive plug 80 in the second through hole.

[0093] As an example, see Fig. 9In step S921, a deposition process may be used to form an interlayer dielectric material layer (not shown), and the interlayer dielectric material layer includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In step S922, after a first patterned mask layer (not shown) is formed on the top surface of the interlayer dielectric material layer, the first patterned mask layer has a pattern for defining the second through hole, and the interlayer dielectric material layer is dry-etched using the first patterned mask layer as a mask. Based on the physical property that the ion etching rate of the top layer is greater than the etching rate of the bottom layer in the dry etching, a second through hole that is wide at the top and narrow at the bottom is obtained. In step S923, a deposition process may be used to fill the second through hole with a conductive plug material, and then a planarization process is used to process the top surface of the conductive plug material to obtain a conductive plug 80 located in the second through hole. The bottom surface size of the conductive plug 80 is smaller than the top surface size of the conductive plug 80, so as to relatively increase the contact area between the conductive plug 80 and the conductive line 90 prepared subsequently, thereby reducing the impedance. The material of the conductive plug 80 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof to meet the actual needs of various application scenarios and reduce the cost and complexity of preparation.

[0094] As an example, see Fig.10 , the conductive plug 80, the memory material layer 72 and the conductive layer 71 can form a stacked structure with a storage function. The conductive layer 71 may include a non-magnetic metal material, and the non-magnetic metal material includes a non-magnetic metal element. For example, the non-magnetic metal material used to make the conductive layer 71 may include but is not limited to TiN, TaN, WN, W, Cu, Al, Ta, Ru, Mo, Pt or a combination thereof; the conductive plug 80 may include a non-magnetic metal material, and the materials of the conductive plug 80 and the conductive layer 71 may be the same or different. The memory material layer 72 may include a magnetic tunnel junction material layer, for example, a reference magnetic layer, a tunnel barrier layer and a free magnetic layer stacked in sequence along a first direction, the reference magnetic layer being adjacent to the conductive layer 71; the reference magnetic layer may be made of a first ferromagnetic material, and the free magnetic layer may be made of a second ferromagnetic material; the first ferromagnetic material may include a hard ferromagnetic material, for example, Co, CoFe, CoFeB, CoFeBTa, NiFe, CoPt, CoFeNi or a combination thereof; the second ferromagnetic material includes a hard ferromagnetic material, and the second ferromagnetic material may be the same as or different from the first ferromagnetic material. The tunnel barrier layer may be an electrically insulating material that allows electrons to tunnel, for example, magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), zirconium oxide (ZrO2) or a combination thereof.

[0095] As an example, see Fig.10 , after forming the conductive plug 80 in the second through hole, further comprising:

[0096] Step S101: forming an insulating material layer (not shown), the insulating material layer covers the top surface of the interlayer dielectric layer 702 and extends along the second direction and the third direction;

[0097] Step S102: patterning the insulating material layer to obtain a conductive line groove (not shown) located directly above the active pillar 21, the conductive line groove extending along the second direction and arranged at intervals along the third direction; the remaining insulating material layer is used to form the insulating structure 91;

[0098] Step S103: forming a conductive wire 90 in the conductive groove.

[0099] As an example, see Fig.10 In step S101, a deposition process may be used to form an insulating material layer covering the top surface of the interlayer dielectric layer 702 and extending along the second direction and the third direction. The insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In step S102, a second patterned mask layer may be formed on the top surface of the insulating material layer. The second patterned mask layer has an opening pattern for defining the shape, position and size of the wire groove. The insulating material layer is etched using the second patterned mask layer as a mask to obtain a wire groove located directly above the active pillar 21. The wire groove extends along the second direction and is arranged at intervals along the third direction. The remaining insulating material layer is used to form an insulating structure 91. In step S103, at least one of an electroplating process, a chemical plating process, a placement process, a printing process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a photolithography process, etc. can be used to form the conductive line 90 in the conductive groove; the material of the conductive line 90 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof.

[0100] As an example, see Fig.10 By selecting a bit line 40 and a conductive line 90, a memory cell on an active column 21 electrically connecting the two can be selected to perform read and write control on the memory cell, which relatively reduces the control steps of scanning the word lines 50 one by one, thereby effectively reducing the complexity of memory read and write control.

[0101] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 3At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0102] In some embodiments, see Figure 1 , Figure 10-12 , provides a memory, including a memory material structure 70, and a bit line 40, a word line 50 and a plurality of active pillars 21 extending along a first direction and arranged in a plurality of rows and columns along a second direction and a third direction in a substrate 100; the second direction intersects with the third direction and is perpendicular to the first direction; the memory material structure 70 is arranged corresponding to the plurality of active pillars 21 and is located on the top surface of the active pillar 21; the bit line 40 is located directly below the active pillar 21 and extends along the third direction, and the bit line 40 is arranged at intervals along the second direction; the word line 50 is located between the bit line 40 and the memory material structure 70, extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars 21.

[0103] As an example, see Figure 1 , Figure 10-12 , by setting a bit line 40 located in the substrate directly below the active pillar 21 and extending along the third direction, so that the storage cells on the active pillars 21 adjacent to each other along the third direction share a bit line 40 extending along the third direction; by setting a memory material structure 70 for non-volatile storage on the top surface of the active pillar 21, a word line 50 extending along the second direction and the third direction and circumferentially surrounding multiple active pillars 21 is set between the bit line 40 and the memory material structure 70, that is, multiple active pillars 21 penetrate the word line 50 along the first direction, so as to facilitate the setting of a conductive line 90 extending along the second direction on the top surface of the memory material structure 70 adjacent to each other along the second direction, so as to select a memory material structure 70 via the conductive line 90 extending along the second direction and the bit line 40 extending along the third direction, thereby realizing one-by-one control of the storage cells in a storage array of a layer in the memory. Since the word line 50 extends along the second direction and the third direction and circumferentially surrounds multiple active pillars 21, the process steps of preparing the word line 50 isolation structure between the word lines 50 of the same layer are avoided, thereby effectively reducing the complexity of the preparation process of the memory; since in the data reading and writing control method of the memory, the control steps of scanning the word lines 50 one by one are relatively reduced, thereby effectively reducing the complexity of the memory reading and writing control.

[0104] As an example, see Figure 1 , Figure 10-12The memory further includes a gate dielectric layer 341; the gate dielectric layer 341 is located between the active pillar 21 and the word line 50 and circumferentially surrounds the active pillar 21. By providing the gate dielectric layer 341 circumferentially surrounding the active pillar 21 between the active pillar 21 and the word line 50, a ring gate is formed in the process of forming the word line 50, which reduces the complexity of the ring gate preparation process and improves the performance of the prepared transistor.

[0105] As an example, see Figure 1 , Figure 10-12 The memory further includes a first doping region, a channel region 211 and a second doping region sequentially distributed on the active pillar 21 along the first direction; the gate dielectric layer 341 circumferentially surrounds the channel region 211. A junctionless transistor can be formed on the active pillar 21, and a source, a vertical channel and a drain arranged in sequence can be formed on the active pillar 21, which can ensure the controllability of the transistor gate and improve the integration density and electrical performance of the memory.

[0106] As an example, see Figure 11-Figure 12 , the memory material structure 70 includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material or a combination thereof.

[0107] As an example, see Figure 1 , Figure 10-12 The memory also includes a first isolation structure 10 extending along the third direction, and the first isolation structure 10 is located between the bit lines 40 adjacent to each other along the second direction and the active pillars 21 adjacent to each other along the second direction; the bottom surface of the first isolation structure 10 is lower than the bottom surface of the bit line 40 and the top surface is lower than the bottom surface of the word line 50, so that the first isolation structure 10 can be used to electrically isolate the bit lines 40 adjacent to each other along the second direction.

[0108] As an example, see Figure 1 , Figure 10-12 The memory further includes a word line capping layer 60 located on the top surface of the word line 50. The word line capping layer 60 is located on the top surface of the word line 50, and the top surface of the word line capping layer 60 is not lower than the top surface of the active pillar 21. The word line capping layer 60 extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars 21.

[0109] As an example, see Figure 1 , Figure 10-12 The memory further includes an isolation layer 701 located on the top surface of the word line cap layer 60, the isolation layer 701 is located between the memory material structures 70 adjacent to each other along the second direction and the third direction, and is located on the top surface of the word line cap layer 60. For example, the isolation layer 701 may be arranged to extend along the second direction and the third direction, and the memory material structure 70 may penetrate the isolation layer 701 along the first direction.

[0110] As an example, see Figure 1 , Figure 10-12The memory also includes a conductive line 90 and a conductive plug 80 corresponding to the memory material structure 70, and the conductive plug 80 is located on the top surface of the corresponding memory material structure 70; the conductive line 90 extends along the second direction and electrically connects the conductive plug 80 directly below it; wherein the conductive lines 90 adjacent to each other along the third direction are insulated from each other via an insulating structure 91 located on the top surface of the isolation layer. The material of the conductive plug 80 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof. The material of the conductive line 90 may include titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof. The material of the conductive plug 80 and the conductive line 90 may be the same or different.

[0111] As an example, see Figure 1 , Figure 10-12 The bottom surface size of the conductive plug 80 is smaller than the top surface size of the conductive plug 80, so as to relatively increase the contact area between the conductive plug 80 and the subsequently prepared conductive wire 90, thereby reducing the impedance.

[0112] As an example, see Figure 1 , Figure 10-12 , the memory material structure 70 includes a memory material layer 72 and a conductive layer 71 located between the memory material layer 72 and the active pillar 21. The conductive plug 80, the memory material layer 72 and the conductive layer 71 can form a stacked structure with a storage function. The conductive layer 71 may include a non-magnetic metal material, and the non-magnetic metal material includes a non-magnetic metal element. For example, the non-magnetic metal material used to make the conductive layer 71 may include but is not limited to titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, tungsten nitride, etc. or a combination thereof; the conductive plug 80 may include a non-magnetic metal material, and the materials of the conductive plug 80 and the conductive layer 71 may be the same or different. The memory material layer 72 may include a magnetic tunnel junction material layer, for example, a reference magnetic layer, a tunnel barrier layer and a free magnetic layer stacked in sequence along a first direction, the reference magnetic layer being adjacent to the conductive layer 71; the reference magnetic layer may be made of a first ferromagnetic material, and the free magnetic layer may be made of a second ferromagnetic material; the first ferromagnetic material may include a hard ferromagnetic material, for example, Co, CoFe, CoFeB, CoFeBTa, NiFe, CoPt, CoFeNi or a combination thereof; the second ferromagnetic material includes a hard ferromagnetic material, and the second ferromagnetic material may be the same as or different from the first ferromagnetic material. The tunnel barrier layer may be an electrically insulating material that allows electrons to tunnel, for example, magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), zirconium oxide (ZrO2) or a combination thereof.

[0113] As an example, see Figure 1 , Figure 10-12By selecting a bit line 40 and a conductive line 90, a memory cell on an active column 21 electrically connecting the two can be selected to perform read and write control on the memory cell, which relatively reduces the control steps of scanning the word lines 50 one by one, thereby effectively reducing the complexity of memory read and write control.

[0114] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, unless the corresponding cross-sectional structural schematic diagrams are given separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can refer to each other.

[0115] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A memory, characterized in that: It includes a memory material structure, and a bit line, a word line and a plurality of active pillars extending along a first direction and arranged in a plurality of rows and columns along a second direction and a third direction in a substrate; the second direction intersects the third direction and is perpendicular to the first direction; The memory material structure is arranged corresponding to the plurality of active pillars and is located on the top surface of the active pillars; The bit lines are located directly below the active pillars and extend along the third direction, and the bit lines are arranged at intervals along the second direction; The word line is located between the bit line and the memory material structure, extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars.

2. The memory according to claim 1, characterized in that: Also includes: The gate dielectric layer is located between the active pillar and the word line and circumferentially surrounds the active pillar.

3. The memory according to claim 2, characterized in that: It also includes a first doping region, a channel region and a second doping region sequentially distributed on the active pillar along the first direction; The gate dielectric layer circumferentially surrounds the channel region.

4. The memory according to any one of claims 1 to 3, characterized in that: The memory material structure includes a memory material layer and a conductive layer located between the memory material layer and the active pillar.

5. The memory according to claim 4, characterized in that: The memory material layer includes a magnetic tunnel junction, a phase change material, a ferroelectric material, a resistive material or a combination thereof.

6. The memory according to any one of claims 1 to 3, characterized in that: Also includes: The word line capping layer is located on the top surface of the word line, extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars.

7. The memory according to claim 6, characterized in that: Also includes: The isolation layer is located between the memory material structures adjacent to each other along the second direction and the third direction, and is located on the top surface of the word line cap layer.

8. The memory according to claim 7, characterized in that: Also includes: A conductive plug, arranged corresponding to the memory material structure and located on the top surface of the corresponding memory material structure; as well as a conductive line extending along the second direction and electrically connected to a conductive plug directly below the conductive line; Wherein, the conductive wires adjacent to each other along the third direction are insulated from each other via an insulating structure located on the top surface of the isolation layer.

9. The memory according to claim 8, characterized in that: The bottom surface size of the conductive plug is smaller than the top surface size of the conductive plug.

10. A method for preparing a memory, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of active pillars extending along a first direction and arranged in a plurality of rows and columns along a second direction and a third direction, wherein the second direction intersects the third direction and is perpendicular to the first direction; forming bit lines extending along the third direction and arranged at intervals along the second direction in the substrate directly below the active pillar; forming a word line extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars; A one-to-one memory material structure is formed on the top surfaces of the plurality of active pillars.

11. The preparation method according to claim 10, characterized in that: The providing of the substrate comprises: Providing an initial substrate, in which a plurality of active walls are formed and arranged along the second direction by first initial isolation structures, and the active walls extend along the third direction; A plurality of intermediate grooves extending along the second direction and arranged at intervals along the third direction are formed in the initial substrate to isolate the active wall into the plurality of active pillars, and the remaining initial substrate is used to constitute the substrate; the bottom surface of the intermediate groove is higher than the bottom surface of the first initial isolation structure.

12. The preparation method according to claim 11, characterized in that: Forming the bit line includes: Ions are implanted into the substrate directly below the active pillar through the middle trench to form a bit line extending along the third direction.

13. The preparation method according to claim 12, characterized in that: Forming the word line includes: forming an isolation material in the middle trench; etching back the isolation material and the first initial isolation structure to form a word line trench extending along the second direction and the third direction and circumferentially surrounding the plurality of active pillars; The word line is formed in the word line trench.

14. The preparation method according to claim 13, characterized in that: The active pillar includes a first doping region, a channel region and a second doping region sequentially distributed along the first direction; A gate dielectric layer circumferentially surrounding the channel region is included between the channel region and the word line; The word line is formed in the word line trench, comprising: The gate dielectric layer is formed during or after etching back the isolation material and the first initial isolation structure.

15. The preparation method according to any one of claims 10 to 14, characterized in that: After forming the word line and before forming the memory material structure, the method comprises: forming a word line capping layer on the top surface of the word line, wherein the top surface of the word line capping layer is not lower than the top surface of the substrate; the word line capping layer extends along the second direction and the third direction and circumferentially surrounds the plurality of active pillars; An isolation layer is formed between adjacent memory material structures along the second direction and the third direction; after forming the memory material structure, the method further includes: forming a conductive plug on the top surface of the memory material structure; Conductive lines extending along the second direction and insulating structures located between the conductive lines adjacent to each other along the third direction are formed; the conductive lines are electrically connected to the conductive plugs directly below them.

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