Preparation method of small-size cellular silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device

Abstract

The invention provides a preparation method of a small-size cellular silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device. The preparation method comprises the following steps of preprocessing a wafer; performing partition impurity ion implantation; annealing treatment; performing surface treatment; preparing field oxygen; preparing a polycrystal gate; preparing an electrode and a passivation layer; the partitions comprise a Pwell region, an N + region, a P + region and a JFET region; impurity ion implantation of at least the N + region comprises the following steps: growing an implantation mask on the front surface of a wafer, coating photoresist, exposing and developing to form a partition pattern implantation region; forming partition injection regions on the injection mask by adopting dry etching, and removing the photoresist; injecting impurity ions by adopting at least two times of inclined injection methods to form partitions, and rotating the wafer along the axis of the wafer between the two times of inclined injection methods; and after the partitions are formed, the injection mask is removed. The method solves the problem of floating glue falling caused by an overlarge photoresist longitudinal-width ratio in a small-size cell unit doping preparation process, and ensures that the size of a doping region meets the design size.

Description

Technical Field

[0001] The present invention relates to the technical field of SiC semiconductor power device preparation, and in particular to a method for preparing a small-size cellular silicon carbide MOSFET device. Background Art

[0002] With the rapid development of power semiconductor technology and power electronics technology, the advancement and industrialization of silicon carbide power electronic device technology will open up new application areas for high-voltage power systems. Compared with traditional silicon-based devices, devices made of silicon carbide, a typical representative of the third-generation semiconductor material, have the advantages of high voltage level, high power density, high switching frequency, and high temperature resistance. They are an important foundation for the upgrading and all-round innovative development of power electronic equipment.

[0003] Since the commercialization of SiC power devices, silicon carbide MOSFET has completed three major technological changes. The main technical features of the third generation are greatly reduced power loss, smaller device area, 50% reduction in on-resistance compared to the second generation SiC MOSFET, and lower operating costs than silicon devices.

[0004] At present, the main methods to reduce on-resistance are as follows: first, reduce the channel length to further reduce the channel resistance of SiC MOSFET; second, reduce the gate-source interface state density and increase the channel mobility, which can reduce the channel resistance by 50%; third, reduce the area of ​​a single cell to achieve a higher current density. Since the electric field strength on the surface of the gate SiO2 in SiC MOSFET is about 2.5 times that of the corresponding SiC surface, and since silicon carbide materials are known for their high critical breakdown electric field strength (about 10 times that of silicon materials), the electric field strength on the gate SiO2 in SiC MOSFET is extremely high, an order of magnitude higher than the electric field strength on the gate SiO2 in SiMOSFET / IGBT. Therefore, the reliability of the gate oxide layer of SiC MOSFET faces serious challenges. Therefore, for planar SiC MOSFET, reducing the cell size (Cell Pitch) is the main method to improve the conduction capability of the device. Such as Figure 4 The key design parameters of the planar gate MOSFET structure, among which the JFET area width and the source contact area width are the main optimization objects. When using conventional processes to dope the N+, P+, Pwell and JFET areas, it is necessary to prepare an implantation mask. The mask of the SiC MOSFET device with small-sized cells will cause the mask to deform, shift or even fall off during the lithography, etching and stripping processes, such as Figure 2 , 3 , which leads to the mismatch between the doping area and the design parameters, resulting in the failure of chip preparation. Summary of the invention

[0005] The present invention aims at the problems existing in the prior art and provides a method for preparing a small-sized cellular silicon carbide MOSFET device, which solves the problem of photoresist peeling caused by an excessively large aspect ratio during the doping preparation process of small-sized cellular units, and ensures that the size of the doped area meets the designed size.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: A method for preparing a small-size cellular silicon carbide MOSFET device comprises the following steps:

[0007] Wafer pretreatment; partition impurity ion implantation; annealing to activate the impurity ions implanted in the partition; surface thermal oxidation and removal of sacrificial oxide layer; field oxygen preparation; polycrystalline gate preparation; electrode and passivation layer preparation;

[0008] The partitions include a Pwell region, an N+ region, a P+ region, and a JFET region;

[0009] At least the impurity ion implantation of the N+ region comprises the following steps:

[0010] Growing an implantation mask on the front side of the wafer;

[0011] Applying photoresist on the surface of the injection mask, and performing exposure and development to form a partition pattern injection area on the photoresist;

[0012] Based on the partitioned pattern injection area, forming a partitioned injection area on the injection mask by dry etching, and removing the photoresist;

[0013] Implanting impurity ions into the partitioned injection region by at least two tilted injections to form the partitioned region;

[0014] The tilted implantation method comprises: tilting the wafer to implant the impurity ions into the partitioned implantation area;

[0015] After completing the tilted implantation method once, rotating the wafer along the wafer axis, and then performing the tilted implantation method again;

[0016] The implantation mask is removed after the partitions are formed.

[0017] Furthermore, when the wafer is tilted, the angle between the wafer surface and the injection direction is 10° to 60°.

[0018] Furthermore, when the shape of the cell is a bar, the tilted injection method is performed twice.

[0019] Furthermore, when the shape of the cell is a regular polygon or a circle, the tilted injection method is performed at least four times.

[0020] Furthermore, between two adjacent tilted implantation methods, the angle of rotating the wafer along the wafer axis is 360° / N, where N is the number of tilted implantation methods, and the direction of the rotation is the same each time.

[0021] Furthermore, the implantation mask is a hard mask, a mask medium of the implantation mask includes at least one of silicon oxide, polysilicon or silicon nitride, and a growth thickness of the implantation mask is 1.0 μm to 3.5 μm.

[0022] Furthermore, the temperature of the tilted injection method is 400-600°C.

[0023] Furthermore, the annealing treatment is performed at a temperature of 1600°C to 1900°C.

[0024] Furthermore, the temperature of the surface thermal oxidation is 1000°C to 1300°C.

[0025] A method for impurity ion implantation of a small-size cellular silicon carbide MOSFET device comprises the following steps:

[0026] Growing an implantation mask on the front side of the wafer;

[0027] Applying photoresist on the surface of the injection mask, and performing exposure and development to form a partition pattern injection area on the photoresist;

[0028] Based on the partitioned pattern injection area, forming a partitioned injection area on the injection mask by dry etching, and removing the photoresist;

[0029] Implanting impurity ions into the partitioned injection region by at least two tilted injections to form the partitioned region;

[0030] The tilted implantation method comprises: tilting the wafer to implant the impurity ions into the partitioned implantation area;

[0031] After completing the tilted implantation method once, the wafer is rotated along the wafer axis and then the tilted implantation method is performed again.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention tilts and rotates the wafer during the impurity ion implantation process, so that the impurity ions are incident on the bottom of the mask edge, thereby increasing the size of the implantation area and reducing the size of the non-implantation area, thereby solving the problem of photoresist peeling caused by an excessively large aspect ratio of the photoresist during the doping preparation process of small-sized cell units, especially when the aspect ratio of the photoresist is greater than 3:2, thereby ensuring the preparation of the implantation mask and ensuring that the size of the doping area meets the design size;

[0034] 2. The present invention reduces the photoresist and injection mask drifting or even falling off in the non-exposed area due to the excessively large aspect ratio by increasing the layout design size. During the injection, the impurity ions are injected into the bottom of the mask edge by tilting the injection area, which can reduce the size of the non-exposed area, thereby reducing the cell size and increasing the current density.

[0035] 3. The method provided by the present invention can reduce the P+ region in the unit cell to 0.3μm~0.4μm, the N+ region to 0.5μm~0.6μm, and the entire unit cell to 5μm~6μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the manufacturing process of a small-size cellular silicon carbide MOSFET device according to an embodiment of the present invention, (a) is MARK preparation, (b) is impurity ion implantation in the Pwell region, (c) is the first tilted implantation of impurity ions in the N+ region, (d) is the second tilted implantation of impurity ions in the N+ region, (e) is impurity ion implantation in the P+ region, (f) is annealing, field oxygen preparation and gate preparation, (g) is the growth of an implantation mask during source preparation, (h) is the formation of a source etch region during source preparation, (i) is source ohmic contact preparation, and (j) is drain preparation;

[0037] Figure 2 A schematic diagram of the tipping, glue drifting and shedding of small-sized cellular silicon carbide MOSFET devices in the prior art;

[0038] Figure 3 This is an actual picture of the dumping, glue drifting and falling off of small-sized cellular silicon carbide MOSFET devices in the prior art;

[0039] Figure 4 It is a schematic diagram of the cross section of MOSFET in the prior art. DETAILED DESCRIPTION

[0040] It is worth noting that the methods used in the present invention are all conventional methods unless otherwise specified; the raw materials and devices used are all conventional commercially available products, and their sources are not specifically limited unless otherwise specified.

[0041] See also Figure 1 A method for preparing a small-size cellular silicon carbide MOSFET device comprises the following steps:

[0042] Wafer pretreatment; the wafer is a silicon carbide wafer, and the wafer pretreatment includes cleaning the silicon carbide wafer to remove organic contamination and particles on the surface of the silicon carbide wafer;

[0043] After wafer pretreatment, MARK preparation is usually performed. Photoresist is applied to the front side of the wafer, and exposure and development are performed to form a MARK mark pattern area. Based on the MARK mark pattern area, an etching process is used to etch the front side of the wafer to form a MARK mark. The depth of the MARK mark is 0.2μm to 0.8μm, and the photoresist is removed.

[0044] Partition impurity ion implantation; the partitions include Pwell area, N+ area, P+ area and JFET area;

[0045] The impurity ion implantation of at least the N+ region comprises the following steps:

[0046] Growing an implantation mask on the front side of the wafer; the implantation mask has a growth thickness of 1.0 μm to 3.5 μm;

[0047] A photoresist with a thickness of 1 μm to 3 μm is applied on the surface of the injection mask, and exposure and development are performed to form a partition pattern injection area on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0048] Based on the partitioned pattern injection area, a partitioned injection area is formed on the injection mask by dry etching, the depth of the partitioned injection area is 1.0 μm to 3.5 μm, and the photoresist is removed;

[0049] The impurity ions are implanted into the partitioned implantation area by at least two tilted implantation methods to form the partitioned area; the temperature of the tilted implantation method is 400-600°C.

[0050] The tilted injection method includes: tilting the wafer to inject impurity ions into the partitioned injection area; when tilting the wafer, the angle between the wafer surface and the injection direction is 10°~60°, and when tilting the wafer, the angle between the wafer surface and the injection direction should be away from 4° to avoid tunnel injection of ions in the crystal; the use of the tilted injection method will expand the size of the doping area, thereby increasing the size of the partitioned injection area, reducing the difficulty of device preparation, and solving the problems of drifting and falling off caused by too small a size.

[0051] After completing one tilt implantation method, the wafer is rotated along the wafer axis and then the next tilt implantation method is performed;

[0052] After forming the partitions, the implantation mask is removed.

[0053] When the wafer is horizontal, the depth of the N+ region after impurity ion implantation is 0.2μm to 1.3μm;

[0054] When the shape of the cell is a bar, the tilted injection method is performed twice. Preferably, after completing one tilted injection method, the angle of the wafer is rotated 180° along the wafer axis, and then the next tilted injection method is performed;

[0055] When the shape of the cell is a regular polygon or a circle, at least four tilted implantation methods are performed. Preferably, between two adjacent tilted implantation methods, the angle of the wafer rotated along the wafer axis is 360° / N, where N is the number of tilted implantation methods, and the direction of each rotation is the same. For example, four tilted implantation methods are performed, and between two adjacent tilted implantation methods, the angle of the wafer rotated along the wafer axis in the same direction each time is 90°, and the number of rotations is three times in total.

[0056] The impurity ion implantation step of the Pwell region, the P+ region or the JFET region is the same as the impurity ion implantation step of the N+ region, or the impurity ion implantation step of the Pwell region, the P+ region or the JFET region is:

[0057] Growing an implantation mask on the front side of the wafer; the implantation mask has a growth thickness of 1.0 μm to 3.5 μm;

[0058] A photoresist with a thickness of 1 μm to 3 μm is applied on the surface of the injection mask, and exposure and development are performed to form a partition pattern injection area on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0059] Based on the partitioned pattern injection area, a partitioned injection area is formed on the injection mask by dry etching, the depth of the partitioned injection area is 1.0 μm to 3.5 μm, and the photoresist is removed;

[0060] Implanting impurity ions into the partitioned injection area by an implantation method to form a partition;

[0061] The implantation mask is removed after the partitions are formed.

[0062] The partitioned injection region also includes a Pwell region injection region, a P+ region injection region and a JFET region injection region;

[0063] The depth of impurity ions injected into the Pwell region is 0.8μm to 1.8μm;

[0064] The depth of impurity ion implantation in the P+ region is 0.3μm to 0.8μm;

[0065] The depth of impurity ion implantation in the JFET region is 0.4μm to 1.5μm;

[0066] Preferably, after dry etching is used to form partitioned injection areas on the injection mask for the Pwell area, N+ area, P+ area and JFET area and the photoresist is removed, an injection mask layer of 30nm to 50nm is fully grown on the wafer surface to reduce damage to the wafer surface caused by injection.

[0067] The injection mask is a hard mask, and the mask medium of the injection mask includes at least one of silicon oxide, polysilicon or silicon nitride. The mask medium of the injection mask includes but is not limited to non-metallic media such as silicon oxide, polysilicon or silicon nitride, which is easy to deposit and remove; in addition, the injection mask is a single layer or multiple layers;

[0068] Annealing is performed to activate the impurity ions injected into the partition; the temperature of the annealing is 1600°C to 1900°C, and after the surface of the wafer is protected, the impurity ions injected into the partition are activated by high-temperature annealing at 1600°C to 1900°C in a vacuum or N2 atmosphere; preferably, the surface of the wafer is protected by a carbon film to prevent the surface of the SiC wafer from being damaged due to high temperature;

[0069] Surface thermal oxidation and removal of sacrificial oxide layer; the temperature of surface thermal oxidation is 1000℃~1300℃; in vacuum or O2 atmosphere, thermally oxidize the wafer surface and then remove the sacrificial oxide layer, which can remove the surface damage layer caused by injection or etching;

[0070] Field oxygen preparation; growing an injection mask on the front side of the wafer; the growth thickness of the injection mask is 0.8 μm to 1.2 μm; applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a field oxygen etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s; based on the partitioned field oxygen etching pattern, forming a field oxygen etching area on the injection mask by dry etching or wet etching, the depth of the field oxygen etching area is 0.8 μm to 1.2 μm, and removing the photoresist;

[0071] Preparation of polycrystalline gate; the preparation steps of polycrystalline gate are as follows:

[0072] Thermal oxidation in O2 or a mixture of O2 and NO at a temperature of 1100°C to 1300°C for 10min to 150min, so that the thickness of the thermal oxidation layer reaches 40nm to 70nm;

[0073] Perform gate oxide annealing at 1100°C to 1300°C in a NO2 or NO atmosphere for 10min to 60min;

[0074] The polysilicon is grown by LPCVD method to a thickness of 0.5 μm to 3.5 μm;

[0075] Doping ions are injected into the polysilicon, and then high temperature is used to make the doping ions diffuse evenly in the polysilicon (polycrystalline push junction) to improve the conductivity of the polysilicon, and then photolithography-etching is performed to leave the polycrystalline gate;

[0076] Preparation of electrodes and passivation layers; including:

[0077] Source preparation, the steps of source preparation are:

[0078] An isolation medium is grown on the front side of the wafer by using LPCVD or PECVD method; the growth thickness of the isolation medium is 0.5 μm to 1.2 μm;

[0079] A photoresist having a thickness of 1 μm to 3 μm is coated on the surface of the isolation medium, and exposure and development are performed to form a field source electrode etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0080] Based on the field source etching pattern, a source etching region is formed on the implantation mask by dry etching, the depth of the source etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0081] A source electrode metal with a thickness of 50 nm to 200 nm is prepared in the source electrode etching area by a metal sputtering method;

[0082] Rapid annealing is performed at 950°C to 1050°C in a vacuum, N2 or Ar atmosphere for 1 min to 3 min;

[0083] Corrosion of source metal to form a source electrode;

[0084] The steps of gate preparation are:

[0085] Applying photoresist with a thickness of 1 μm to 3 μm, and performing exposure and development to form a first gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0086] Based on the first gate etching pattern, a first gate etching region is formed on the implantation mask by dry etching, wherein the depth of the first gate etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0087] A gate metal with a thickness of 2 μm to 5 μm is prepared in the gate etching area by a metal sputtering method;

[0088] A photoresist having a thickness of 1 μm to 3 μm is applied on the gate metal surface, and exposure and development are performed to form a second gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0089] etching the gate metal based on the second gate etching pattern;

[0090] Annealing is performed at a temperature of 400° C. to 550° C. in a vacuum, N2 or Ar atmosphere for 30 min to 60 min to form a gate;

[0091] Preparation of the passivation layer. The steps of preparing the passivation layer are:

[0092] Depositing an initial passivation layer on the front side of the wafer; the deposition thickness of the initial passivation layer is 0.8 μm to 1.5 μm;

[0093] Coating PI on the surface of the initial passivation layer, and performing exposure and development to form a PI passivation pattern on the photoresist, wherein the exposure time is 1000ms to 2000ms, and the development time is 180s to 300s;

[0094] Bake in vacuum at 300°C to 450°C for 30min to 100min;

[0095] Based on the PI passivation pattern, dry etching is used to expose the source electrode on the initial passivation layer to form a passivation layer;

[0096] Drain preparation, the steps of drain preparation are:

[0097] Provide front protection for the wafer;

[0098] Remove the oxide layer and polycrystalline on the back of the wafer;

[0099] Depositing drain metal on the back side of the wafer;

[0100] By using laser annealing with energy of 1.4KJ / cm~3.5KJ / cm to treat the drain metal, laser annealing is used to form alloy contact, reducing front contamination;

[0101] The drain is obtained by metal thickening.

[0102] The embodiment of the present invention also provides a method for impurity ion implantation of a small-size cellular silicon carbide MOSFET device, comprising the following steps:

[0103] Growth of an implant mask on the front side of the wafer;

[0104] Applying photoresist on the surface of the injection mask, and performing exposure and development to form a partition pattern injection area on the photoresist;

[0105] Based on the partitioned pattern injection area, a partitioned injection area is formed on the injection mask by dry etching, and the photoresist is removed;

[0106] Implanting impurity ions into the partitioned injection area by at least two tilted injection methods to form a partition;

[0107] The tilted implantation method includes: tilting the wafer to implant the impurity ions into the partitioned implantation area;

[0108] After completing one tilted implantation method, the wafer is rotated along the wafer axis and then the next tilted implantation method is performed.

[0109] Embodiment 1;

[0110] A method for preparing a small-size cellular silicon carbide MOSFET device comprises the following steps:

[0111] Wafer pretreatment; the wafer is a silicon carbide wafer, and the wafer pretreatment includes cleaning the silicon carbide wafer to remove organic contamination and particles on the surface of the silicon carbide wafer;

[0112] After wafer pretreatment, MARK (mark) preparation is performed, photoresist of 1 μm to 3 μm is coated on the front side of the wafer, and exposure and development are performed to form a MARK mark pattern area, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s; based on the MARK mark pattern area, a dry etching process is used to etch on the front side of the wafer to form a MARK mark, and the depth of the MARK mark is 0.3 μm to 0.6 μm, and the photoresist is removed;

[0113] Partition impurity ion implantation; the partitions include Pwell area, N+ area, P+ area and JFET area;

[0114] The steps of impurity ion implantation in the Pwell region are:

[0115] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.0 μm to 2.5 μm;

[0116] A photoresist with a thickness of 1 μm to 3 μm is applied on the surface of the injection mask, and exposure and development are performed to form a Pwell region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0117] Based on the Pwell region pattern injection region, a Pwell region injection region is formed on the injection mask by dry etching, the depth of the Pwell region injection region is 1.0 μm to 2.5 μm, and the photoresist is removed;

[0118] The impurity ions are implanted into the Pwell region to form the Pwell region. The temperature of the implantation method is 400-600° C., and the depth of the impurity ion implantation in the Pwell region is 0.8 μm-1.2 μm.

[0119] After forming the Pwell region, the implantation mask is removed.

[0120] The impurity ion implantation in the N+ region includes the following steps:

[0121] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.2 μm to 2.5 μm;

[0122] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form an N+ region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0123] Based on the N+ region pattern injection region, an N+ region injection region is formed on the injection mask by dry etching, the depth of the N+ region injection region is 1.2 μm to 2.5 μm, and the photoresist is removed;

[0124] The impurity ions are injected into the N+ region by four tilted injection methods to form the N+ region; when the wafer is horizontal, the depth of the impurity ions in the N+ region after injection is 0.2μm to 1.3μm; the temperature of the tilted injection method is 400 to 600°C: specifically, the cell is a square cell, and the tilted injection method includes: tilting the wafer so that the angle between the wafer surface and the injection direction is 20° to 30°, and injecting the impurity ions into the N+ injection region; rotating the wafer 90° along the wafer axis, and then performing the next tilted injection method, and so on, rotating the wafer 90° along the wafer axis between two adjacent tilted injection methods, until the four tilted injection methods are completed;

[0125] After forming the partitions, the implantation mask is removed.

[0126] The steps for impurity ion implantation in the P+ region are:

[0127] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.2 μm to 2.5 μm;

[0128] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a P+ region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0129] Based on the P+ region pattern injection region, a P+ region injection region is formed on the injection mask by dry etching, the depth of the P+ region injection region is 1.2 μm to 2.5 μm, and the photoresist is removed;

[0130] The impurity ions are implanted into the P+ region to form the P+ region. The temperature of the implantation method is 400-600° C. and the depth of the impurity ions implanted into the P+ region is 0.3 μm-0.8 μm.

[0131] After forming the P+ region, the implantation mask is removed.

[0132] The steps of impurity ion implantation in the JFET region are:

[0133] Growing an implantation mask on the front side of the wafer; the implantation mask has a growth thickness of 1.5 μm to 3.5 μm;

[0134] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a JFET region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0135] Based on the JFET region pattern injection region, a JFET region injection region is formed on the injection mask by dry etching, the depth of the JFET region injection region is 1.5 μm to 3.5 μm, and the photoresist is removed;

[0136] The impurity ions are implanted into the JFET region to form the JFET region. The temperature of the implantation method is 400-600° C., and the depth of the impurity ion implantation in the JFET region is 0.4 μm-1.2 μm.

[0137] After forming the JFET region, the implantation mask is removed.

[0138] Annealing is used to activate the impurity ions injected into the partition; the annealing temperature is 1600°C to 1900°C, the annealing time is 10min to 60min, and after the wafer is surface protected, the impurity ions injected into the partition are activated by high-temperature annealing at 1600°C to 1900°C in a vacuum or N2 atmosphere; surface protection is used to protect the silicon carbide surface from precipitation of carbon elements; surface protection is a conventional process in the field and will not be described in detail here;

[0139] Surface thermal oxidation and removal of sacrificial oxide layer; the temperature of surface thermal oxidation is 1000℃~1300℃, and the time of surface thermal oxidation is 20min~60min; in vacuum or O2 atmosphere, thermally oxidize the wafer surface, and then remove the sacrificial oxide layer, which can remove the surface damage layer caused by injection or etching;

[0140] Field oxygen preparation; growing an injection mask on the front side of the wafer; the growth thickness of the injection mask is 0.8 μm to 1.2 μm; applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a field oxygen etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s; based on the partitioned field oxygen etching pattern, forming a field oxygen etching area on the injection mask by dry etching or wet etching, the depth of the field oxygen etching area is 0.8 μm to 1.2 μm, and removing the photoresist;

[0141] Preparation of polycrystalline gate; the preparation steps of polycrystalline gate are as follows:

[0142] Thermal oxidation in O2 or a mixture of O2 and NO at a temperature of 1100°C to 1300°C for 10min to 150min, so that the thickness of the thermal oxidation layer reaches 40nm to 70nm;

[0143] Perform gate oxide annealing at 1100°C to 1300°C in a NO2 or NO atmosphere for 10min to 60min;

[0144] The polysilicon is grown by LPCVD method to a thickness of 0.5 μm to 3.5 μm;

[0145] Doping ions are injected into the polysilicon, and then high temperature is used to make the doping ions diffuse evenly in the polysilicon (polycrystalline push junction) to improve the conductivity of the polysilicon, and then photolithography-etching is performed to leave the polycrystalline gate;

[0146] Preparation of electrodes and passivation layers; including:

[0147] Source preparation, the steps of source preparation are:

[0148] An isolation medium is grown on the front side of the wafer by using LPCVD or PECVD method; the growth thickness of the isolation medium is 0.5 μm to 1.2 μm;

[0149] A photoresist having a thickness of 1 μm to 3 μm is coated on the surface of the isolation medium, and exposure and development are performed to form a field source electrode etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0150] Based on the field source etching pattern, a source etching region is formed on the implantation mask by dry etching, the depth of the source etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0151] A source electrode metal with a thickness of 50 nm to 200 nm is prepared in the source electrode etching area by a metal sputtering method;

[0152] Rapid annealing is performed at 950°C to 1050°C in a vacuum, N2 or Ar atmosphere for 1 min to 3 min;

[0153] Corrosion of source metal to form a source electrode;

[0154] The steps of gate preparation are:

[0155] Applying photoresist with a thickness of 1 μm to 3 μm, and performing exposure and development to form a first gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0156] Based on the first gate etching pattern, a first gate etching region is formed on the implantation mask by dry etching, wherein the depth of the first gate etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0157] A gate metal with a thickness of 2 μm to 5 μm is prepared in the gate etching area by a metal sputtering method;

[0158] A photoresist having a thickness of 1 μm to 3 μm is applied on the gate metal surface, and exposure and development are performed to form a second gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0159] etching the gate metal based on the second gate etching pattern;

[0160] Annealing is performed at a temperature of 400° C. to 550° C. in a vacuum, N2 or Ar atmosphere for 30 min to 60 min to form a gate;

[0161] Preparation of the passivation layer. The steps of preparing the passivation layer are:

[0162] Depositing an initial passivation layer on the front side of the wafer; the deposition thickness of the initial passivation layer is 0.8 μm to 1.5 μm;

[0163] Coating PI on the surface of the initial passivation layer, and performing exposure and development to form a PI passivation pattern on the photoresist, wherein the exposure time is 1000ms to 2000ms, and the development time is 180s to 300s;

[0164] Bake in vacuum at 300°C to 450°C for 30min to 100min;

[0165] Based on the PI passivation pattern, dry etching is used to expose the source electrode on the initial passivation layer to form a passivation layer;

[0166] Drain preparation, the steps of drain preparation are:

[0167] Provide front protection for the wafer;

[0168] Remove the oxide layer and polycrystalline on the back of the wafer;

[0169] Depositing drain metal on the back side of the wafer;

[0170] The drain metal is treated by laser annealing with an energy of 2KJ / cm to 3.5KJ / cm;

[0171] The drain is obtained by metal thickening.

[0172] Embodiment 2;

[0173] A method for preparing a small-size cellular silicon carbide MOSFET device comprises the following steps:

[0174] Wafer pretreatment; the wafer is a silicon carbide wafer, and the wafer pretreatment includes cleaning the silicon carbide wafer to remove organic contamination and particles on the surface of the silicon carbide wafer;

[0175] After wafer pretreatment, MARK (mark) preparation is performed, photoresist of 1 μm to 3 μm is coated on the front side of the wafer, and exposure and development are performed to form a MARK mark pattern area, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s; based on the MARK mark pattern area, a dry etching process is used to etch on the front side of the wafer to form a MARK mark, and the depth of the MARK mark is 0.3 μm to 0.6 μm, and the photoresist is removed;

[0176] Partition impurity ion implantation; the partitions include Pwell area, N+ area, P+ area and JFET area;

[0177] The steps of impurity ion implantation in the Pwell region are:

[0178] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.0 μm to 2.5 μm;

[0179] A photoresist with a thickness of 1 μm to 3 μm is applied on the surface of the injection mask, and exposure and development are performed to form a Pwell region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0180] Based on the Pwell region pattern injection region, a Pwell region injection region is formed on the injection mask by dry etching, the depth of the Pwell region injection region is 1.0 μm to 2.5 μm, and the photoresist is removed;

[0181] The impurity ions are implanted into the Pwell region to form the Pwell region. The temperature of the implantation method is 400-600° C., and the depth of the impurity ion implantation in the Pwell region is 0.8 μm-1.2 μm.

[0182] After forming the Pwell region, the implantation mask is removed.

[0183] The impurity ion implantation in the N+ region includes the following steps:

[0184] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.2 μm to 2.5 μm;

[0185] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form an N+ region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0186] Based on the N+ region pattern injection region, an N+ region injection region is formed on the injection mask by dry etching, the depth of the N+ region injection region is 1.2 μm to 2.5 μm, and the photoresist is removed;

[0187] The impurity ions are implanted into the N+ region by two tilted implantation methods to form the N+ region; when the wafer is horizontal, the depth of the impurity ions in the N+ region after implantation is 0.2μm to 1.3μm; the temperature of the tilted implantation method is 400 to 600°C: specifically, the cell is a strip cell, and the tilted implantation method includes: tilting the wafer so that the angle between the wafer surface and the implantation direction is 10° to 60°, and implanting the impurity ions into the N+ implantation region; rotating the wafer 180° along the wafer axis, and then performing the next tilted implantation method;

[0188] After forming the partitions, the implantation mask is removed.

[0189] The steps for impurity ion implantation in the P+ region are:

[0190] An implantation mask is grown on the front side of the wafer; the implantation mask has a growth thickness of 1.2 μm to 2.5 μm;

[0191] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a P+ region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0192] Based on the P+ region pattern injection region, a P+ region injection region is formed on the injection mask by dry etching, the depth of the P+ region injection region is 1.2 μm to 2.5 μm, and the photoresist is removed;

[0193] The impurity ions are implanted into the P+ region to form the P+ region. The temperature of the implantation method is 400-600° C. and the depth of the impurity ions implanted into the P+ region is 0.3 μm-0.8 μm.

[0194] After forming the P+ region, the implantation mask is removed.

[0195] The steps of impurity ion implantation in the JFET region are:

[0196] Growing an implantation mask on the front side of the wafer; the implantation mask has a growth thickness of 1.5 μm to 3.5 μm;

[0197] Applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a JFET region pattern injection region on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0198] Based on the JFET region pattern injection region, a JFET region injection region is formed on the injection mask by dry etching, the depth of the JFET region injection region is 1.5 μm to 3.5 μm, and the photoresist is removed;

[0199] The impurity ions are implanted into the JFET region to form the JFET region. The temperature of the implantation method is 400-600° C., and the depth of the impurity ion implantation in the JFET region is 0.4 μm-1.2 μm.

[0200] After forming the JFET region, the implantation mask is removed.

[0201] The impurity ions injected into the partition are activated by annealing treatment; the annealing temperature is 1600°C to 1900°C, the annealing time is 10min to 60min, and after the surface of the wafer is protected, the impurity ions injected into the partition are activated by high-temperature annealing at 1600°C to 1900°C in a vacuum or N2 atmosphere;

[0202] Surface thermal oxidation and removal of sacrificial oxide layer; the temperature of surface thermal oxidation is 1000℃~1300℃, and the time of surface thermal oxidation is 20min~60min; in vacuum or O2 atmosphere, thermally oxidize the wafer surface, and then remove the sacrificial oxide layer, which can remove the surface damage layer caused by injection or etching;

[0203] Field oxygen preparation; growing an injection mask on the front side of the wafer; the growth thickness of the injection mask is 0.8 μm to 1.2 μm; applying a photoresist with a thickness of 1 μm to 3 μm on the surface of the injection mask, and performing exposure and development to form a field oxygen etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s; based on the partitioned field oxygen etching pattern, forming a field oxygen etching area on the injection mask by dry etching or wet etching, the depth of the field oxygen etching area is 0.8 μm to 1.2 μm, and removing the photoresist;

[0204] Preparation of polycrystalline gate; the preparation steps of polycrystalline gate are as follows:

[0205] Thermal oxidation in O2 or a mixture of O2 and NO at a temperature of 1100°C to 1300°C for 10min to 150min, so that the thickness of the thermal oxidation layer reaches 40nm to 70nm;

[0206] Perform gate oxide annealing at 1100°C to 1300°C in a NO2 or NO atmosphere for 10min to 60min;

[0207] The polysilicon is grown by LPCVD method to a thickness of 0.5 μm to 3.5 μm;

[0208] Doping ions are injected into the polysilicon, and then high temperature is used to make the doping ions diffuse evenly in the polysilicon (polycrystalline push junction) to improve the conductivity of the polysilicon, and then photolithography-etching is performed to leave the polycrystalline gate;

[0209] Preparation of electrodes and passivation layers; including:

[0210] Source preparation, the steps of source preparation are:

[0211] An isolation medium is grown on the front side of the wafer by using LPCVD or PECVD method; the growth thickness of the isolation medium is 0.5 μm to 1.2 μm;

[0212] A photoresist having a thickness of 1 μm to 3 μm is coated on the surface of the isolation medium, and exposure and development are performed to form a field source electrode etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms and the development time is 30 s to 120 s;

[0213] Based on the field source etching pattern, a source etching region is formed on the implantation mask by dry etching, the depth of the source etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0214] A source electrode metal with a thickness of 50 nm to 200 nm is prepared in the source electrode etching area by a metal sputtering method;

[0215] Rapid annealing is performed at 950°C to 1050°C in a vacuum, N2 or Ar atmosphere for 1 min to 3 min;

[0216] Corrosion of source metal to form a source electrode;

[0217] Gate preparation, the steps of gate preparation are:

[0218] Applying photoresist with a thickness of 1 μm to 3 μm, and performing exposure and development to form a first gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0219] Based on the first gate etching pattern, a first gate etching region is formed on the implantation mask by dry etching, wherein the depth of the first gate etching region is 0.5 μm to 1.2 μm, and the photoresist is removed;

[0220] A gate metal with a thickness of 2 μm to 5 μm is prepared in the gate etching area by a metal sputtering method;

[0221] A photoresist having a thickness of 1 μm to 3 μm is applied on the gate metal surface, and exposure and development are performed to form a second gate etching pattern on the photoresist, wherein the exposure time is 100 ms to 900 ms, and the development time is 30 s to 120 s;

[0222] etching the gate metal based on the second gate etching pattern;

[0223] Annealing is performed at a temperature of 400° C. to 550° C. in a vacuum, N2 or Ar atmosphere for 30 min to 60 min to form a gate;

[0224] Preparation of the passivation layer. The steps of preparing the passivation layer are:

[0225] Depositing an initial passivation layer on the front side of the wafer; the deposition thickness of the initial passivation layer is 0.8 μm to 1.5 μm;

[0226] Coating PI on the surface of the initial passivation layer, and performing exposure and development to form a PI passivation pattern on the photoresist, wherein the exposure time is 1000ms to 2000ms, and the development time is 180s to 300s;

[0227] Bake in vacuum at 300°C to 450°C for 30min to 100min;

[0228] Based on the PI passivation pattern, dry etching is used to expose the source electrode on the initial passivation layer to form a passivation layer;

[0229] Drain preparation, the steps of drain preparation are:

[0230] Provide front protection for the wafer;

[0231] Remove the oxide layer and polycrystalline on the back of the wafer;

[0232] Depositing drain metal on the back side of the wafer;

[0233] The drain metal is treated by laser annealing with an energy of 2KJ / cm to 3.5KJ / cm;

[0234] The drain is obtained by metal thickening.

[0235] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, rather than to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions of the technical solution of the present invention by ordinary technicians in this field do not deviate from the essence and scope of the technical solution of the present invention.

Claims

1. A method for preparing a small-size cellular silicon carbide MOSFET device, characterized in that: The following steps are involved: Wafer pre-processing; Partitioned impurity ion implantation; Activating the impurity ions implanted in the partition by annealing; Surface thermal oxidation and removal of sacrificial oxide layer; Field oxygen preparation; polycrystalline gate preparation; Preparation of electrodes and passivation layers; The partitions include a Pwell region, an N+ region, a P+ region, and a JFET region; At least the impurity ion implantation of the N+ region comprises the following steps: Growing an implantation mask on the front side of the wafer; Applying photoresist on the surface of the injection mask, and performing exposure and development to form a partition pattern injection area on the photoresist; Based on the partitioned pattern injection area, forming a partitioned injection area on the injection mask by dry etching, and removing the photoresist; Implanting impurity ions into the partitioned injection region by at least two tilted injections to form the partitioned region; The tilted implantation method comprises: tilting the wafer to implant the impurity ions into the partitioned implantation area; After completing the tilted implantation method once, rotating the wafer along the wafer axis, and then performing the tilted implantation method again; The implantation mask is removed after the partitions are formed.

2. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: Features: When the wafer is tilted, the angle between the wafer surface and the injection direction is 10° to 60°.

3. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: When the shape of the cell is a bar, the tilted injection method is performed twice.

4. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: When the shape of the cell is a regular polygon or a circle, the tilted implantation method is performed at least four times.

5. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 3 or 4, characterized in that: Between two adjacent tilted implantation methods, the angle of rotating the wafer along the wafer axis is 360° / N, where N is the number of tilted implantation methods, and the direction of the rotation is the same each time.

6. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: The injection mask is a hard mask, a mask medium of the injection mask includes at least one of silicon oxide, polysilicon or silicon nitride, and a growth thickness of the injection mask is 1.0 μm to 3.5 μm.

7. The method for preparing a small-size cellular silicon carbide MOSFET device according to any one of claims 1 to 4 and 6, characterized in that: The temperature of the tilted injection method is 400-600°C.

8. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: The temperature of the annealing treatment is 1600°C to 1900°C.

9. The method for preparing a small-size cellular silicon carbide MOSFET device according to claim 1, characterized in that: The temperature of the surface thermal oxidation is 1000°C to 1300°C.

10. A method for impurity ion implantation of a small-size cellular silicon carbide MOSFET device, characterized in that: The following steps are involved: Growth of an implant mask on the front side of the wafer; Applying photoresist on the surface of the injection mask, and performing exposure and development to form a partition pattern injection area on the photoresist; Based on the partitioned pattern injection area, forming a partitioned injection area on the injection mask by dry etching, and removing the photoresist; Implanting impurity ions into the partitioned injection region by at least two tilted injections to form the partitioned region; The tilted implantation method comprises: tilting the wafer to implant the impurity ions into the partitioned implantation area; After completing the tilted implantation method once, the wafer is rotated along the wafer axis and then the tilted implantation method is performed again.

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