GaN-based HEMT device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to a GaN-based HEMT device and a preparation method thereof, a gate dielectric layer of the GaN-based HEMT device is any one of a laminated gate dielectric and a single-layer gate dielectric, and the gate dielectric layer comprises any one of a GeN dielectric layer and a GeON dielectric layer. According to the GaN-based HEMT device, the leakage current of the gate dielectric layer can be effectively reduced, the voltage endurance capability of the device is improved, breakdown or damage is avoided, a high-quality interface structure can be formed, the adverse effect of an interface state on the performance of the device is reduced, and the efficiency and power performance of the GaN-based HEMT device are remarkably improved. Therefore, the selection range of the gate dielectric material of the GaN-based HEMT device is widened, the performance of the device is remarkably improved and the cost is reduced through fine material selection and structural design, and powerful support is provided for wide application of the GaN-based HEMT device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a GaN-based HEMT device and a preparation method thereof. Background Art

[0002] With the rapid development of modern electronic technology, GaN (gallium nitride) based devices have shown broad application prospects in military and civilian fields such as satellite communications and high-efficiency radars due to their excellent high mobility, high voltage resistance and high saturation speed. Such devices not only require miniaturization to meet the growing demand for integration, but also must meet high standards in reliability, high efficiency and low noise to ensure stable operation in various complex environments.

[0003] However, GaN-based devices face a series of challenges in practical applications, among which gate leakage current, limited forward gate voltage swing, and current collapse are key factors affecting device performance. The increase in gate leakage current will directly lead to increased power consumption and reduced device reliability, while the limitation of forward voltage swing may hinder the normal operation of the device under high voltage conditions. In addition, the current collapse phenomenon will further reduce the output power and efficiency of the device, seriously restricting its application in high-performance systems.

[0004] To overcome these challenges, researchers have extensively explored methods of depositing a layer of dielectric materials (such as Al2O3, HfO2, and SiN) under the gate. These dielectric layers help reduce the current collapse effect and improve the stability of the threshold voltage by improving the interface quality between the gate and the GaN material, thereby enhancing the overall performance of the device.

[0005] At present, the growth methods used to deposit these dielectric layers mainly include PECVD (plasma enhanced chemical vapor deposition), PEALD (plasma enhanced atomic layer deposition), LPCVD (low pressure chemical vapor deposition), MOCVD (metal organic chemical vapor deposition) and MBE (molecular beam epitaxy). However, each method has certain limitations. For example, when PECVD is deposited at 300°C, energy damage may be introduced and a higher hydrogen content may be caused, which has an adverse effect on device performance. LPCVD requires a higher growth temperature (about 750°C), which not only increases the process difficulty, but also may damage the surface quality of GaN, especially when the temperature exceeds 650°C, the GaN surface may decompose, produce defects and reduce the channel mobility.

[0006] Although MOCVD has the potential to grow SiN in situ as a gate dielectric, the Si contamination problem in the cavity and its incompatibility with recessed gate technology limit its application. Therefore, although these methods have improved the performance of GaN-based devices to a certain extent, it is still a huge challenge to achieve low gate leakage, large gate voltage swing and low interface state density at the same time.

[0007] In view of this, there is an urgent need to develop a new gate dielectric deposition technology to overcome the limitations of existing methods and further improve the performance and reliability of GaN-based devices. Summary of the invention

[0008] The object of the present invention is to provide a GaN-based HEMT device and a preparation method thereof, which effectively improves the efficiency and power performance of the GaN-based HEMT device.

[0009] In a first aspect, the present invention provides a GaN-based HEMT device, wherein a gate dielectric layer of the GaN-based HEMT device is any one of a stacked gate dielectric and a single-layer gate dielectric, and the gate dielectric layer includes any one of a GeN and a GeON dielectric layer.

[0010] As a preferred embodiment of the present technical solution, the thickness of the GeN dielectric layer is 5-50 nm, and the thickness of the GeON dielectric layer is 5-50 nm.

[0011] In a second aspect, the present invention further provides a method for preparing the above-mentioned GaN-based HEMT device, comprising the following steps:

[0012] S1, fabricating a source electrode and a drain electrode on a GaN buffer layer of an epitaxial substrate;

[0013] S2, electrically isolating the active area of ​​the device;

[0014] S3, forming a GeN or GeON gate dielectric layer on the surface of the device;

[0015] S4. Make gate electrodes and metal interconnect layers to complete the preparation of GaN-based HEMT devices.

[0016] As a preferred embodiment of the present technical solution, in step S3, when the gate dielectric layer is manufactured, a Ge metal film is deposited on the device surface by thermal evaporation, and then a GeN or GeON gate dielectric layer is formed on the device surface by plasma treatment or high temperature annealing.

[0017] As a preferred embodiment of the present technical solution, in step S3, when manufacturing the gate dielectric layer, any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition and molecular beam epitaxy is used to directly generate a GeN or GeON thin film on the device surface.

[0018] As a preferred embodiment of the present technical solution, step S1 includes:

[0019] Photolithography of source electrode region and drain electrode region on SiN or GaN cap layer;

[0020] depositing an ohmic metal material on the source electrode region and the drain electrode region;

[0021] Rapid thermal annealing causes the ohmic metal material to sink into the GaN buffer layer to form an ohmic contact.

[0022] As a preferred embodiment of the present technical solution, in step S2, the active area of ​​the device is electrically isolated by ion implantation or mesa isolation.

[0023] As a preferred embodiment of the present technical solution, when the ion implantation method is adopted, first, a mask is prepared on the surface of the device to protect the active area from the influence of the ion implantation, and then, the doping atoms are implanted into the semiconductor material in the form of a high-speed ion beam. After the implantation is completed, the mask material is removed to form an isolation area.

[0024] As a preferred embodiment of the present technical solution, when the mesa isolation method is adopted, first, a mask is prepared on the surface of the device to define the shape and position of the mesa isolation, and then, the semiconductor material not protected by the mask is removed by physical etching to form a mesa structure. After the etching is completed, the mask material is removed to form an isolation area.

[0025] As a preferred embodiment of the present technical solution, step S4 includes:

[0026] Depositing a passivation layer on the surface of the gate electrode and the gate dielectric layer;

[0027] The source, gate and drain are etched to make interconnect openings, and interconnect metal is evaporated to complete the preparation of the GaN-based HEMT device.

[0028] The GaN-based HEMT device and the preparation method thereof of the present invention have at least the following beneficial effects:

[0029] 1. The GaN-based HEMT device of the present invention uses GeN or GeON as the gate dielectric. GeN or GeON can be used not only as a gate dielectric but also as a passivation layer. GeN or GeON has excellent electrical properties and chemical stability, and can effectively reduce the leakage current of the gate dielectric layer, thereby improving the voltage resistance of the device. At the same time, they have good interface compatibility with GaN materials, which helps to form a high-quality interface structure and reduce the adverse effects of the interface state on device performance. In addition, the GaN-based HEMT device of the present invention includes a stacked gate dielectric structure and a single-layer gate dielectric, wherein the stacked gate dielectric structure can further optimize the electrical properties and stability of the gate dielectric layer through the combination of different materials; and the single-layer gate dielectric structure has the advantages of simple preparation process and low cost. Regardless of which structure is adopted, it can improve production efficiency and reduce costs while meeting device performance requirements;

[0030] 2. In the preparation method of the GaN-based HEMT device of the present invention, first, the position and size of the source electrode and the drain electrode are precisely controlled to ensure that the electrical performance of the device meets the design requirements. Then, the active area of ​​the device is electrically isolated to prevent current crosstalk between the active areas and improve the stability and reliability of the device. Further, GeN or GeON is used as the gate dielectric layer material to significantly reduce the leakage current and interface state density of the gate dielectric layer, thereby improving the efficiency and power performance of the device. Finally, the structure and size of the gate electrode and the metal interconnect layer are precisely controlled to ensure that the electrical performance and reliability of the device meet the design requirements. The GaN-based HEMT device prepared by the present invention can effectively reduce the leakage current of the gate dielectric layer and improve the voltage resistance of the device without breakdown or damage, and is helpful to form a high-quality interface structure, reduce the adverse effects of the interface state on the device performance, and significantly improve its efficiency and power performance.

[0031] 3. The present invention not only broadens the selection range of gate dielectric materials for GaN-based HEMT devices, but also achieves significant improvement in device performance and reduction in cost through sophisticated material selection and structural design, providing strong support for the widespread application of GaN-based HEMT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the preparation process of the GaN-based HEMT device of the present invention;

[0034] Figure 2 The source electrode and the drain electrode are fabricated on the GaN buffer layer of the epitaxial substrate in the present invention;

[0035] Figure 3 The active area of ​​the device is electrically isolated for the present invention;

[0036] Figure 4 For the present invention, a GeN or GeON gate dielectric layer is fabricated on the surface of the device;

[0037] Figure 5 Making a gate electrode for the present invention;

[0038] Figure 6 Graph showing leakage characteristics of the MIS-HEMT device prepared in Example 3 of the present invention and a common HEMT device under gate reverse bias conditions;

[0039] Figure 7 This is a graph showing the output characteristics of the MIS-HEMT device prepared in Example 3 of the present invention. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0042] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] Example 1

[0044] This embodiment provides a GaN-based HEMT device, the gate dielectric layer of the GaN-based HEMT device is any one of a stacked gate dielectric and a single-layer gate dielectric, which is not strictly limited by the present invention, wherein the stacked gate dielectric structure can further optimize the electrical properties and stability of the gate dielectric layer by combining different materials; and the single-layer gate dielectric structure has the advantages of simple preparation process and low cost. Regardless of which structure is adopted, it can improve production efficiency and reduce costs while meeting the performance requirements of the device. In addition, the gate dielectric layer in this embodiment includes any one of GeN and GeON dielectric layers, and GeN or GeON is used as the gate dielectric. GeN or GeON can not only be used as a gate dielectric, but also as a passivation layer. Since GeN or GeON has excellent electrical properties and chemical stability, it can effectively reduce the leakage current of the gate dielectric layer, thereby improving the withstand voltage of the device. At the same time, they have good interface compatibility with GaN materials, which helps to form a high-quality interface structure, reduce the adverse effects of the interface state on the device performance, and significantly improve the efficiency and power performance of GaN-based HEMT devices.

[0045] Specifically, in a specific embodiment of the present invention, the thickness of the GeN dielectric layer is any value between 5-50nm, and preferably 5-10nm, and the thickness of the GeON dielectric layer is any value between 5-50nm, and preferably 5-10nm. The GeN or GeON dielectric layer of the present invention mainly acts as a gate dielectric layer or a passivation layer, or acts as a gate dielectric and a passivation layer at the same time, and its thickness can be adjusted according to actual needs, and the present invention does not strictly limit it.

[0046] In addition, the present invention does not impose strict limitations on the types of GaN-based HEMT devices, including but not limited to microwave and millimeter wave devices.

[0047] Example 2

[0048] like Figure 1 As shown, this embodiment provides a method for preparing the above-mentioned GaN-based HEMT device, which specifically includes the following steps:

[0049] S1, fabricating a source electrode and a drain electrode on a GaN buffer layer of an epitaxial substrate;

[0050] Step S1 Preferably, step S1 specifically includes:

[0051] Photolithography of source electrode region and drain electrode region on SiN or GaN cap layer;

[0052] Further depositing an ohmic metal material on the source electrode region and the drain electrode region, specifically, first, on the surface of the semiconductor material, define an ohmic contact pattern by photolithography technology, that is, coat a layer of photoresist on the surface of the material, and then use a mask and ultraviolet irradiation to form the required pattern; then, remove the unirradiated part of the photoresist by a chemical development step, so as to leave the pattern outline of the ohmic contact on the surface of the material; then, in the defined ohmic pattern area, remove the semiconductor material of a certain depth by physical or chemical methods to form a groove, so as to improve the current transmission efficiency by reducing the contact resistance and optimize the performance of the ohmic contact; and then deposit one or more layers of ohmic metal stacks in the groove treated with the ohmic recess, which usually include metals such as Ti (titanium), Al (aluminum), Ni (nickel) and Au (gold), and the deposition process can be achieved by electron beam evaporation, sputtering or other physical vapor deposition techniques;

[0053] Finally, after the ohmic metal stack is deposited, the device is placed in a high temperature environment for alloying treatment to allow a chemical reaction to occur between the metal stack and the semiconductor material to form a stable alloy interface, thereby reducing the contact resistance. During the alloying process, different metals in the metal stack may diffuse and react with each other to form an ohmic contact. The alloying conditions are different for different ohmic systems. For example, for a gold system, the annealing temperature is 800°C-900°C, the atmosphere is nitrogen, and the annealing time is 30s-1min.

[0054] S2, electrically isolating the active area of ​​the device;

[0055] In step S2, preferably, when electrically isolating the active region of the device, ion implantation or mesa isolation is used to electrically isolate the active region of the device.

[0056] When using the ion implantation method, first, a mask is prepared on the device surface to protect the active area from the impact of ion implantation and define the area that needs to be isolated; then, the doping atoms (such as Ar or N, etc.) are injected into the semiconductor material not protected by the mask in the form of a high-speed ion beam; after the implantation is completed, the mask material is removed, leaving the isolation area formed by the ion implantation.

[0057] When the mesa isolation method is used, first, a mask is prepared on the surface of the device to define the shape and position of the mesa isolation. Then, a physical etching method (such as dry etching or wet etching) is used to remove the semiconductor material not protected by the mask to form a mesa structure that isolates the active area from other areas. After the etching is completed, the mask material is removed to form an isolation area.

[0058] S3, forming a GeN or GeON gate dielectric layer on the surface of the device;

[0059] Step S3: Preferably, when the gate dielectric layer is made, a Ge metal film is deposited on the device surface by thermal evaporation, and then a GeN or GeON gate dielectric layer is formed on the device surface by plasma treatment or high temperature annealing;

[0060] When the gate dielectric layer of the present invention is manufactured, the dielectric nitridation or nitridation method is not limited to plasma treatment and high temperature annealing, and any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition and molecular beam epitaxy can be used to directly generate GeN or GeON film on the device surface.

[0061] For example, when chemical vapor deposition is used, precursor gases containing Ge and N (such as GeH4 and NH3) are introduced into the reaction chamber, and chemical reactions are carried out at high temperatures to directly generate GeN or GeON films on the device surface. This method can accurately control the thickness and composition of the film and is suitable for large-area uniform deposition.

[0062] When using atomic layer deposition, two or more precursor gases are introduced into the reaction chamber through alternating pulses, and a short vacuum is performed after each pulse to deposit GeN or GeON on the device surface layer by layer. This method has extremely high thickness control accuracy (up to nanometer level) and can form high-quality, pinhole-free films.

[0063] When physical vapor deposition is used, Ge is evaporated into atoms or molecules using an evaporation source (such as electron beam evaporation or sputtering), which then reacts with N2 gas in a reaction chamber to form GeN or GeON and deposit on the device surface. This method can form high-purity films and is suitable for applications with strict requirements on film composition.

[0064] When molecular beam epitaxy is used, atomic or molecular beams of Ge and N are introduced into the reaction chamber under ultra-high vacuum conditions using precise beam control, and epitaxial growth is carried out on the device surface. This method can precisely control the composition, structure and thickness of the film and is suitable for the preparation of high-performance electronic devices.

[0065] S4. Make gate electrodes and metal interconnect layers to complete the preparation of GaN-based HEMT devices.

[0066] Step S4: Preferably, the preparation of the gate electrode comprises the following steps:

[0067] First, a layer of photoresist is coated on the surface of the MIS-HEMT device on which a GeON or GeN gate dielectric layer has been formed, and then the pattern of the gate is defined by photolithography technology;

[0068] On the defined gate pattern, one or more layers of gate metal material are deposited by physical vapor deposition (such as sputtering or electron beam evaporation) or chemical vapor deposition;

[0069] After the gate metal deposition is completed, a stripping solution (such as acetone or ethanol) is used to strip the gate metal material not covering the gate pattern from the device surface;

[0070] After stripping is completed, the device is cleaned with a cleaning agent such as deionized water to remove residual stripping solution and impurities;

[0071] After the gate metal is stripped and cleaned, the gate electrode preparation process is completed. At this point, the gate electrode has been accurately defined on the gate dielectric layer and forms an effective electrical connection with the source and drain electrodes of the device.

[0072] The preparation of the metal interconnect layer includes the following steps:

[0073] Design a reasonable metal wiring solution based on the device's test requirements and circuit layout;

[0074] At the source electrode, drain electrode and gate electrode of the device, holes are opened by laser drilling or mechanical drilling;

[0075] After the holes are opened, metal wires are deposited on the surface of the device by physical vapor deposition or electroplating, and connected to each electrode through the holes;

[0076] Finally, a uniform SiN dielectric layer is deposited on the device surface by plasma enhanced chemical vapor deposition (PECVD) and other methods, thus completing the preparation of the GaN-based HEMT device.

[0077] Example 3

[0078] like Figure 2-5As shown, this embodiment provides a specific method for preparing a GaN-based HEMT device, comprising the following steps:

[0079] S1. Select an epitaxial substrate including a substrate, a GaN buffer layer, an AlN insertion layer and a SiN cap layer from bottom to top, and make a source electrode and a drain electrode on the GaN buffer layer of the epitaxial substrate, further define the ohmic pattern by photolithography, deposit an ohmic metal stack (Ti / Al / Ni / Au) by ohmic recess processing technology, and further anneal at 800℃-900℃ for 30s-1min to form an ohmic contact with the high-temperature alloy;

[0080] S2. Prepare a mask on the device surface to protect the active area from the influence of ion implantation and define the area to be isolated. Then, dopant atoms Ar are implanted into the semiconductor material not protected by the mask in the form of a high-speed ion beam. After the implantation is completed, remove the mask material, leaving the isolation area formed by the ion implantation.

[0081] S3, depositing a Ge metal film on the device surface by thermal evaporation, and then forming a GeON gate dielectric layer on the device surface by N plasma treatment under vacuum conditions;

[0082] S4. Using photolithography technology, a gate pattern is defined on the device surface where a GeON gate dielectric layer has been formed. On the defined gate pattern, a layer of Ni metal material is deposited by physical vapor deposition. After the gate metal deposition is completed, a stripping liquid (such as acetone or ethanol) is used to strip the gate metal material not covered on the gate pattern from the device surface. After the stripping is completed, a cleaning agent such as deionized water is used to clean the device to remove the residual stripping liquid and impurities, thereby completing the production of the gate electrode.

[0083] S5. Design a reasonable metal wiring scheme according to the device test requirements and circuit layout; use laser drilling or mechanical drilling to make holes at the source electrode, drain electrode and gate electrode of the device; after the holes are made, use physical vapor deposition to deposit metal wires on the device surface and form connections with each electrode through the holes;

[0084] S6. Using plasma enhanced chemical vapor deposition method, a uniform SiN dielectric layer is deposited on the surface of the device to complete the preparation of GaN-based HEMT device.

[0085] Figure 6 : is a leakage characteristic diagram of the MIS-HEMT prepared in this embodiment and the common HEMT device under the gate reverse bias condition. It can be seen from the figure that the gate reverse leakage of the MIS-HEMT device prepared in the present invention is reduced by 3 orders of magnitude compared with the common HEMT device;

[0086] Figure 7 This is an output characteristic diagram of the MIS-HEMT device prepared in this embodiment. It can be seen from the figure that the MIS-HEMT device prepared in the present invention improves the saturation output current while suppressing current collapse.

[0087] In summary, the GaN-based HEMT device prepared by the present invention can effectively reduce the leakage current of the gate dielectric layer and improve the voltage resistance of the device without breakdown or damage, and is helpful to form a high-quality interface structure, reducing the adverse effects of the interface state on the device performance, so that its efficiency and power performance are significantly improved.

[0088] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaN-based HEMT device, characterized in that: The gate dielectric layer of the GaN-based HEMT device is any one of a stacked gate dielectric and a single-layer gate dielectric, and the gate dielectric layer includes any one of a GeN dielectric layer and a GeON dielectric layer.

2. The GaN-based HEMT device according to claim 1, characterized in that: The thickness of the GeN dielectric layer is 5-50 nm, and the thickness of the GeON dielectric layer is 5-50 nm.

3. The method for preparing a GaN-based HEMT device according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1, fabricating a source electrode and a drain electrode on a GaN buffer layer of an epitaxial substrate; S2, electrically isolating the active area of ​​the device; S3, forming a GeN or GeON gate dielectric layer on the surface of the device; S4. Make gate electrodes and metal interconnect layers to complete the preparation of GaN-based HEMT devices.

4. The preparation method according to claim 3, characterized in that: In step S3, when the gate dielectric layer is manufactured, a Ge metal film is deposited on the device surface by thermal evaporation, and then a GeN or GeON gate dielectric layer is formed on the device surface by plasma treatment or high temperature annealing.

5. The preparation method according to claim 3, characterized in that: In step S3, when the gate dielectric layer is manufactured, any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition and molecular beam epitaxy is used to directly form a GeN or GeON thin film on the device surface.

6. The preparation method according to claim 3, characterized in that: Step S1 includes: Photolithography of source electrode region and drain electrode region on SiN or GaN cap layer; depositing an ohmic metal material on the source electrode region and the drain electrode region; Rapid thermal annealing causes the ohmic metal material to sink into the GaN buffer layer to form an ohmic contact.

7. The preparation method according to claim 3, characterized in that: In step S2, the active region of the device is electrically isolated by ion implantation or mesa isolation.

8. The preparation method according to claim 7, characterized in that: When using the ion implantation method, first, a mask is prepared on the device surface to protect the active area from the impact of ion implantation. Then, the doped atoms are implanted into the semiconductor material in the form of a high-speed ion beam. After the implantation is completed, the mask material is removed to form an isolation area.

9. The preparation method according to claim 7, characterized in that: When using the mesa isolation method, first, a mask is prepared on the surface of the device to define the shape and position of the mesa isolation. Then, the semiconductor material not protected by the mask is removed by physical etching to form a mesa structure. After the etching is completed, the mask material is removed to form an isolation area.

10. The preparation method according to claim 3, characterized in that: Step S4 includes: Depositing a passivation layer on the surface of the gate electrode and the gate dielectric layer; The source, gate and drain are etched to make interconnect openings, and interconnect metal is evaporated to complete the preparation of the GaN-based HEMT device.

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