Gallium nitride MIS-HEMT device structure

Abstract

The invention relates to a gallium nitride MIS-HEMT device structure. The device comprises a substrate; the AlN layer is arranged on the substrate; the GaN buffer layer is arranged on the AlN layer; the GaN channel layer is arranged on the GaN buffer layer; the AlN space layer is arranged on the GaN channel layer; the two-dimensional electron gas layer is formed in the GaN channel layer and is close to an interface between the GaN channel layer and the AlN space layer; the AlGaN potential barrier layer is arranged on the AlN space layer; the source electrode and the drain electrode are respectively arranged on the AlGaN barrier layer; the p-GaN layer is arranged on the AlGaN barrier layer and is positioned between the source electrode and the drain electrode; the insulating layer is covered on the p-GaN layer; the grid electrode is arranged on the insulating layer; a grid electrode coarsening structure is at least partially arranged on one surface, in contact with the insulating layer, of the grid electrode; and a p-GaN layer coarsening structure corresponding to the grid electrode coarsening structure is arranged on one surface, close to the insulating layer, of the p-GaN layer. According to the invention, the problem of short-channel effect deterioration caused by reduction of the device size is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride MIS-HEMT device structure. Background Art

[0002] As a III-V semiconductor material, GaN has broad application prospects in microwave / millimeter wave high-power devices and power electronics due to its excellent electron transmission performance, high breakdown electric field and high electron saturation velocity. Metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) is a device based on GaN material. It is developed on the basis of traditional high electron mobility transistor (HEMT). By introducing an insulating layer between the gate and the semiconductor, the gate leakage current is effectively reduced and the reliability and breakdown voltage of the device are improved.

[0003] However, as the size of MIS-HEMT devices continues to shrink, the gate length also decreases, resulting in a significant enhancement of the short channel effect, which in turn causes an increase in device leakage current, seriously affecting the reliability and performance of MIS-HEMT devices. Summary of the invention

[0004] To this end, the present invention provides a gallium nitride MIS-HEMT device structure, which aims to solve the problem of deterioration of short channel effect caused by the reduction of device size. By roughening the bottom of the gate and combining gallium nitride oxide (GaO) to form a high-quality insulating layer, leakage current is effectively suppressed and the voltage resistance and overall reliability of the device are improved.

[0005] In order to solve the above technical problems, the present invention provides a gallium nitride MIS-HEMT device structure, comprising: substrate; An AlN layer is disposed on the substrate; A GaN buffer layer, disposed on the AlN layer; A GaN channel layer, disposed on the GaN buffer layer; An AlN space layer is disposed on the GaN channel layer; A two-dimensional electron gas layer, wherein the two-dimensional electron gas layer is formed in the GaN channel layer and is close to an interface between the GaN channel layer and the AlN space layer; An AlGaN barrier layer is disposed on the AlN space layer; A source electrode and a drain electrode are respectively arranged on the AlGaN barrier layer; A p-GaN layer, disposed on the AlGaN barrier layer and between the source and the drain; An insulating layer, covering the p-GaN layer; A gate, disposed on the insulating layer; The gate is at least partially provided with a gate roughening structure on one side in contact with the insulating layer; and the p-GaN layer is provided with a p-GaN layer roughening structure on one side close to the insulating layer corresponding to the gate roughening structure.

[0006] In one embodiment of the present invention, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer covers the surface of the p-GaN layer and the AlGaN barrier layer respectively, the second insulating layer covers the first insulating layer, and the gate is arranged on the second insulating layer; wherein, an insulating layer roughening structure is arranged on a side where the first insulating layer and the second insulating layer are in contact with each other.

[0007] In one embodiment of the present invention, the average roughness of the gate roughening structure, the insulating layer roughening structure and the p-GaN layer roughening structure are all in the range of 2 to 50 nm.

[0008] In one embodiment of the present invention, the ratio of the width of the gate roughening structure to the width of the gate is 0.5-1.2.

[0009] In one embodiment of the present invention, the p-GaN layer is covered with a GaO layer conforming to the roughened structure of the p-GaN layer, and the thickness of the GaO layer is 0.5-5 nm.

[0010] In one embodiment of the present invention, a first groove extending to the AlN space layer is opened along the p-GaN layer, the insulating layer extends into the first groove and has a second groove, the bottom of the gate extends into and fills the second groove, the p-GaN layer roughening structure is distributed on the bottom wall and side walls of the first groove, the p-GaN layer roughening structure is covered with a GaO layer conforming to the p-GaN layer roughening structure, and the gate roughening structure is distributed on the bottom wall and side walls of the second groove.

[0011] In one embodiment of the present invention, the average roughness of the p-GaN layer roughening structure on the side wall of the first groove is not greater than the average roughness of the p-GaN layer roughening structure on the bottom wall of the first groove; The average roughness of the gate roughening structure on the side wall of the second groove is not greater than the average roughness of the gate roughening structure on the bottom wall of the second groove; The average roughness of the p-GaN layer roughening structure on the bottom wall of the first groove and the average roughness of the gate roughening structure on the bottom wall of the second groove are both 2-50 nm; The average roughness of the p-GaN layer roughening structure on the side wall of the first groove and the average roughness of the gate roughening structure on the side wall of the second groove are both 0.5-20 nm.

[0012] In one embodiment of the present invention, the morphology of the gate roughening structure includes irregular sawtooth shape, regular sawtooth shape, hemispherical shape, rectangular block shape and / or trapezoidal block shape.

[0013] The above technical solution of the present invention has the following advantages compared with the prior art: The gallium nitride MIS-HEMT device structure described in the present invention performs a roughening treatment at the bottom of the gate and combines gallium nitride oxide (GaO) to form a high-quality insulating layer, thereby effectively suppressing leakage current and improving the voltage resistance and overall reliability of the device. Specifically, the present invention uses a hard mask or maskless etching technology to form a p-GaN surface structure (roughening pattern) with a certain average roughness at the bottom of the gate, and then uses oxygen plasma treatment or ion implantation to generate a thin GaO insulating layer in the roughening area. This structure not only increases the interface area between the gate and the substrate and enhances the insulation performance, but also improves the electric field distribution by roughening the surface, reduces the leakage current, and thus improves the performance and reliability of the MIS-HEMT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0015] Figure 1 It is a structural schematic diagram of the gallium nitride MIS-HEMT device structure in Example 1 of the present invention.

[0016] Figure 2 It is a structural schematic diagram of the gallium nitride MIS-HEMT device structure in Example 2 of the present invention.

[0017] Figure 3 It is a structural schematic diagram of the gallium nitride MIS-HEMT device structure in Example 3 of the present invention.

[0018] Figure 4 It is a structural schematic diagram of the gallium nitride MIS-HEMT device structure in Example 4 of the present invention.

[0019] Figure 5 yes Figure 4 A partial enlarged schematic diagram of .

[0020] Description of the Figures in the Specification: 101. substrate; 102. AlN layer; 103. GaN buffer layer; 104. GaN channel layer; 105. two-dimensional electron gas layer; 106. AlN space layer; 107. AlGaN barrier layer; 108. source; 109. gate; 110. drain; 111. gate roughening structure; 112. insulating layer; 113. first insulating layer; 114. second insulating layer; 115. p-GaN layer roughening structure; 116. GaO layer; 117. first groove; 118. second groove; 119. p-GaN layer; 120. insulating layer roughening structure. DETAILED DESCRIPTION

[0021] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0022] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0023] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0024] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0025] Example 1 Reference Figure 1 As shown, this embodiment provides a GaN MIS-HEMT device structure, including: Substrate 101; An AlN layer 102 is disposed on the substrate 101; A GaN buffer layer 103, disposed on the AlN layer 102; A GaN channel layer 104 is disposed on the GaN buffer layer 103; An AlN space layer 106 is disposed on the GaN channel layer 104; A two-dimensional electron gas layer 105, wherein the two-dimensional electron gas layer 105 is formed in the GaN channel layer 104 and is close to the interface between the GaN channel layer 104 and the AlN space layer 106; An AlGaN barrier layer 107 is disposed on the AlN space layer 106; A source electrode 108 and a drain electrode 110 are respectively disposed on the AlGaN barrier layer 107; A p-GaN layer 119, disposed on the AlGaN barrier layer 107 and located between the source electrode 108 and the drain electrode 110; An insulating layer 112, covering the p-GaN layer 119; the insulating layer 112 may be made of Si3N4 or Al2O3; A gate 109 is disposed on the insulating layer 112; The gate 109 has a surface contacting the insulating layer 112 at least partially provided with a gate roughening structure 111 ; the p-GaN layer 119 has a surface close to the insulating layer 112 provided with a p-GaN layer roughening structure 115 corresponding to the gate roughening structure 111 .

[0026] Specifically, the insulating layer 112 includes a first insulating layer 113 and a second insulating layer 114, the first insulating layer 113 covers the surface of the p-GaN layer 119 and the AlGaN barrier layer 107 respectively, the second insulating layer 114 covers the first insulating layer 113, and the gate 109 is arranged on the second insulating layer 114; wherein, an insulating layer roughening structure 120 is arranged on the side where the first insulating layer 113 and the second insulating layer 114 contact each other.

[0027] Specifically, the average roughness of the gate roughening structure 111 , the insulating layer roughening structure 120 , and the p-GaN layer roughening structure 115 are all between 2 and 50 nm.

[0028] Specifically, the ratio of the width Lw of the gate roughening structure 111 to the width Lg of the gate 109 is 0.5-1.2.

[0029] Specifically, the morphology of the gate roughening structure 111 includes irregular sawtooth or regular sawtooth. It can be formed by plasma etching and hard template method (for example, using Ni nanoparticles). When using the plasma etching method, the target surface corresponding to the bottom of the gate 109, the insulating layer 112 and the p-GaN layer 119 is cleaned, a layer of photoresist is coated on the target area, and the area to be roughened is defined by photolithography technology, and a specific gas (such as chlorine, fluorinated gas or oxygen, etc.) is used to generate plasma; the etching process parameters (such as etching gas flow, power, reaction time) are adjusted to achieve nano-scale roughness control; the surface is etched to form a regular or irregular sawtooth roughening structure.

[0030] A hard template method is used to form a roughened structure (taking Ni nanoparticles as an example), and a solution deposition method or a physical vapor deposition method is used to form uniformly distributed Ni particles on the target surface; the size and distribution density of the Ni particles are adjusted to achieve the desired roughening effect; the Ni particles are used as a mask to selectively etch the material surface; during the etching process, the area protected by the Ni particles remains intact, while the exposed area is etched to form a jagged or irregular morphology.

[0031] This embodiment effectively increases the contact area between the gate 109, the insulating layer 112 and the p-GaN layer 119, and improves the insulation performance: the roughened contact between the gate 109 and the insulating layer 112 reduces the occurrence of leakage current, thereby enhancing the insulation characteristics of the device.

[0032] Example 2 Reference Figure 2 As shown, this embodiment provides a GaN MIS-HEMT device structure, including: Substrate 101; An AlN layer 102 is disposed on the substrate 101; A GaN buffer layer 103, disposed on the AlN layer 102; A GaN channel layer 104 is disposed on the GaN buffer layer 103; An AlN space layer 106 is disposed on the GaN channel layer 104; A two-dimensional electron gas layer 105, wherein the two-dimensional electron gas layer 105 is formed in the GaN channel layer 104 and is close to the interface between the GaN channel layer 104 and the AlN space layer 106; An AlGaN barrier layer 107 is disposed on the AlN space layer 106; A source electrode 108 and a drain electrode 110 are respectively disposed on the AlGaN barrier layer 107; A p-GaN layer 119, disposed on the AlGaN barrier layer 107 and located between the source electrode 108 and the drain electrode 110; An insulating layer 112 covering the p-GaN layer 119; A gate 109 is disposed on the insulating layer 112; Among them, a side of the gate 109 in contact with the insulating layer 112 is at least partially provided with a gate coarsening structure 111; a side of the p-GaN layer 119 close to the insulating layer 112 is provided with a p-GaN layer coarsening structure 115 corresponding to the gate coarsening structure 111, and the p-GaN layer 119 is covered with a GaO layer 116 conforming to the p-GaN layer coarsening structure 115, and the thickness of the GaO layer 116 is 0.5~5nm.

[0033] The GaO layer 116 can be further formed into a thin layer of GaO by oxygen plasma or ion implantation based on the roughening of the p-GaN layer 119 at the bottom of the gate 109. The oxygen plasma treatment method uses active oxygen to modify the surface of the p-GaN layer 119 to generate a conformal thin layer of GaO. Oxygen or an oxygen mixed gas (such as O2 / N2) is introduced, and a high-frequency electric field (such as radio frequency or microwave) is applied to ionize the oxygen to form a plasma; the active oxygen in the plasma reacts with the surface of the p-GaN layer 119, selectively oxidizing the surface Ga atoms to GaO; the surface morphology of the roughened structure area is retained, and a conformal GaO thin layer is formed at the same time.

[0034] The ion implantation method implants oxygen ions into the surface of the p-GaN layer 119 to chemically modify the surface and generate the GaO layer 116. The implanted oxygen ions combine with Ga on the surface to form a chemically stable GaO layer 116.

[0035] The GaO layer 116 formed at the bottom of the gate 109 serves as an insulator, effectively blocking the leakage current path between the gate 109 and the substrate 101, greatly reducing the leakage current of the device. This not only improves the switching efficiency of the device, but also reduces power consumption and prolongs the service life of the device.

[0036] Specifically, the gate roughening structure 111 , the GaO layer 116 and the p-GaN layer roughening structure 115 are respectively located on three mutually parallel planes and have the same width.

[0037] Specifically, the gate roughening structure 111 , the GaO layer 116 , and the p-GaN layer roughening structure 115 are symmetrically arranged along a symmetrical cross-section of the gate 109 .

[0038] It can be understood that the average roughness of the GaO layer 116 is equal to that of the gate roughening structure 111. Specifically, the average roughness of the gate roughening structure 111 and the p-GaN layer roughening structure 115 are both between 2 and 50 nm.

[0039] Specifically, the ratio of the width of the gate roughening structure 111 to the width of the gate 109 is 0.5-1.2.

[0040] Specifically, the gate roughening structure 111 may have an irregular sawtooth shape or a regular sawtooth shape, or a rectangular block shape or a trapezoidal block shape.

[0041] Example 3 Reference Figure 3 As shown, this embodiment provides a GaN MIS-HEMT device structure. Compared with Embodiment 2, the gate roughening structure 111 has a hemispherical shape. The rest of the structure is the same as Embodiment 2. Specifically, after coating with a single layer of SiO2 balls (PS balls), etching to form a hemispherical shape includes the following steps: SiO2 balls or PS balls (polystyrene microspheres) are selected, and the size is usually in the range of 50 nm to 500 nm, and the appropriate ball diameter is selected according to the size of the target roughened structure; Disperse SiO2 or PS spheres in deionized water and add a small amount of surfactant (such as sodium dodecyl sulfate, SDS) to prevent particle aggregation; The prepared SiO2 / PS ball suspension is drop-coated on the surface of the gate 109 to be processed, and the particles are evenly distributed and form a monolayer array by natural drying or spin coating. The uniformity of self-assembly is controlled, and the monolayer coverage of the spheres is ensured by optimizing the liquid concentration and spin coating speed.

[0042] Heat treatment is performed on the coated ball layer to increase the adhesion between the particles and the substrate and prevent the particles from falling off during the subsequent etching process; Using a single layer of SiO2 / PS balls as a hard template, a hemispherical roughening structure is formed in the gate 109 region through an etching process, using a reactive ion etching (RIE) device or an ICP etching device (plasma enhanced etching device).

[0043] By setting the regular morphology of the hemispherical protrusions, a higher contact area is provided, and the contact with the insulating layer 112 enhances the interface strength and electrical performance.

[0044] Example 4 Reference Figure 4 , Figure 5 As shown, this embodiment provides a GaN MIS-HEMT device structure, specifically a D-Mode HEMT structure, including: Substrate 101; An ALN ​​layer 102 is disposed on the substrate 101; A GaN buffer layer 103, disposed on the AlN layer 102; A GaN channel layer 104 is disposed on the GaN buffer layer 103; An AlN space layer 106 is disposed on the GaN channel layer 104; A two-dimensional electron gas layer 105, wherein the two-dimensional electron gas layer 105 is formed in the GaN channel layer 104 and is close to the interface between the GaN channel layer 104 and the AlN space layer 106; An AlGaN barrier layer 107 is disposed on the AlN space layer 106; A source electrode 108 and a drain electrode 110 are respectively disposed on the AlGaN barrier layer 107; A p-GaN layer 119, disposed on the AlGaN barrier layer 107 and located between the source electrode 108 and the drain electrode 110; An insulating layer 112 covering the p-GaN layer 119; A gate 109 is disposed on the insulating layer 112; A first groove 117 extending to the AlN space layer 106 is opened along the p-GaN layer 119, the insulating layer 112 extends into the first groove 117 and has a second groove 118, the bottom of the gate 109 extends into and fills the second groove 118, the p-GaN layer roughening structure 115 is distributed on the bottom wall and side walls of the first groove 117, the p-GaN layer roughening structure 115 is covered with a GaO layer 116 conforming to the p-GaN layer roughening structure 115, and the gate roughening structure 111 is distributed on the bottom wall and side walls of the second groove 118.

[0045] The average roughness of the p-GaN layer roughening structure 115 on the side wall of the first groove 117 is not greater than the average roughness of the p-GaN layer roughening structure 115 on the bottom wall of the first groove 117; The average roughness of the gate roughening structure 111 on the side wall of the second groove 118 is not greater than the average roughness of the gate roughening structure 111 on the bottom wall of the second groove 118; The roughness of the p-GaN layer roughening structure 115 on the bottom wall of the first groove 117 and the average roughness of the gate roughening structure 111 on the bottom wall of the second groove 118 are both 2-50 nm; The average roughness of the p-GaN layer roughening structure 115 on the sidewall of the first groove 117 and the average roughness of the gate roughening structure 111 on the sidewall of the second groove 118 are both 0.5-20 nm.

[0046] Specifically, the ratio of the width Lw of the gate roughening structure 111 (ie, the bottom wall width of the second groove 118 ) to the width Lg of the gate 109 is in the range of 0.5 to 1.2.

[0047] This embodiment is aimed at the D-Mode HEMT (depletion mode high electron mobility transistor) structure, and significantly improves the performance and reliability of the device by introducing a groove structure and corresponding roughening treatment in the p-GaN layer 119 and the gate 109 region. Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A gallium nitride MIS-HEMT device structure, characterized in that: include: Substrate (101); An AlN layer (102) is disposed on the substrate (101); A GaN buffer layer (103) is disposed on the AlN layer (102); A GaN channel layer (104) is disposed on the GaN buffer layer (103); An AlN space layer (106) is disposed on the GaN channel layer (104); A two-dimensional electron gas layer (105), wherein the two-dimensional electron gas layer (105) is formed in the GaN channel layer (104) and is close to an interface between the GaN channel layer (104) and the AlN space layer (106); An AlGaN barrier layer (107) is disposed on the AlN space layer (106); A source electrode (108) and a drain electrode (110) are respectively arranged on the AlGaN barrier layer (107); A p-GaN layer (119) is disposed on the AlGaN barrier layer (107) and is located between the source electrode (108) and the drain electrode (110); An insulating layer (112), covering the p-GaN layer (119); A gate (109) is disposed on the insulating layer (112); The gate (109) has a surface in contact with the insulating layer (112) at least partially provided with a gate coarsening structure (111); and the p-GaN layer (119) has a surface close to the insulating layer (112) provided with a p-GaN layer coarsening structure (115) corresponding to the gate coarsening structure (111).

2. A gallium nitride MIS-HEMT device structure according to claim 1, characterized in that: The insulating layer (112) comprises a first insulating layer (113) and a second insulating layer (114); the first insulating layer (113) covers the surface of the p-GaN layer (119) and the AlGaN barrier layer (107) respectively; the second insulating layer (114) covers the first insulating layer (113); and the gate (109) is arranged on the second insulating layer (114); wherein an insulating layer coarsening structure (120) is arranged on a surface where the first insulating layer (113) and the second insulating layer (114) are in contact with each other.

3. A gallium nitride MIS-HEMT device structure according to claim 2, characterized in that: The average roughness of the gate roughening structure (111), the insulating layer roughening structure (120) and the p-GaN layer roughening structure (115) are all between 2 and 50 nm.

4. A gallium nitride MIS-HEMT device structure according to claim 2, characterized in that: The ratio of the width of the gate coarsening structure (111) to the width of the gate (109) is between 0.5 and 1.

2.

5. The gallium nitride MIS-HEMT device structure according to claim 1, characterized in that: The p-GaN layer (119) is covered with a GaO layer (116) conforming to the p-GaN layer roughening structure (115), and the thickness of the GaO layer (116) is 0.5-5 nm.

6. The gallium nitride MIS-HEMT device structure according to claim 1, characterized in that: A first groove (117) extending to the AlN space layer (106) is opened along the p-GaN layer (119), the insulating layer (112) extends into the first groove (117) and has a second groove (118), the bottom of the gate (109) extends into and fills the second groove (118), the p-GaN layer coarsening structure (115) is distributed on the bottom wall and side wall of the first groove (117), the p-GaN layer coarsening structure (115) is covered with a GaO layer (116) conforming to the p-GaN layer coarsening structure (115), and the gate coarsening structure (111) is distributed on the bottom wall and side wall of the second groove (118).

7. A gallium nitride MIS-HEMT device structure according to claim 6, characterized in that: The average roughness of the p-GaN layer roughening structure (115) on the side wall of the first groove (117) is not greater than the average roughness of the p-GaN layer roughening structure (115) on the bottom wall of the first groove (117); The average roughness of the gate coarsening structure (111) on the side wall of the second groove (118) is not greater than the average roughness of the gate coarsening structure (111) on the bottom wall of the second groove (118); The average roughness of the p-GaN layer roughening structure (115) on the bottom wall of the first groove (117) and the average roughness of the gate roughening structure (111) on the bottom wall of the second groove (118) are both 2-50 nm; The average roughness of the p-GaN layer coarsening structure (115) on the side wall of the first groove (117) and the average roughness of the gate coarsening structure (111) on the side wall of the second groove (118) are both 0.5-20 nm.

8. A gallium nitride MIS-HEMT device structure according to any one of claims 1 to 7, characterized in that: The morphology of the gate coarsening structure (111) includes an irregular sawtooth shape, a regular sawtooth shape, a hemispherical shape, a rectangular block shape and / or a trapezoidal block shape.

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