Transistor structure
By adopting a multi-layer gate dielectric layer structure and virtual gate design in the transistor structure, the problem of poor electrical performance of transistor structures when reducing the size in the prior art is solved, and smaller size and better electrical performance are achieved The effect of performance.
Patent Information
- Application Number
- CN202310971919.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-03
- Publication Date
- 2025-02-18
AI Technical Summary
It is difficult for existing transistor structures to maintain good electrical performance while reducing the size.
A multi-layer gate dielectric layer structure is adopted, wherein the thickness of the second portion is greater than the thickness of the first portion, and a virtual gate is provided on the second portion, the virtual gate is located between the gate and the second doped region.
Effectively reduces the size of the transistor structure, while improving its electrical performance, such as breakdown voltage and turn-on current, reducing the Kirk effect.
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Figure CN119486198A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and in particular to a transistor structure. Background Art
[0002] Transistor structures are widely used in various electronic products. However, how to further reduce the size of the transistor structure and further improve the electrical performance of the transistor structure is a goal of continuous efforts. Summary of the invention
[0003] The present invention provides a transistor structure which can have a smaller size and better electrical performance.
[0004] The present invention provides a transistor structure, including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region and a virtual gate. The gate dielectric layer is located on the substrate. The gate dielectric layer includes a first portion and a second portion. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first portion and the second portion. The first doped region and the second doped region are located in the substrate on both sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The virtual gate is located on the second portion between the gate and the second doped region.
[0005] According to an embodiment of the present invention, in the above transistor structure, the second portion may be embedded in the substrate.
[0006] According to an embodiment of the present invention, in the transistor structure, the bottom surface of the second portion may be lower than the bottom surface of the first portion, and the top surface of the second portion may be coplanar with the top surface of the first portion.
[0007] According to an embodiment of the present invention, in the transistor structure, the bottom surface of the gate dielectric layer may include a stepped profile, the bottom surface of the gate may be a flat surface, and the gate may be a metal gate.
[0008] According to an embodiment of the present invention, in the transistor structure, the top surface of the second portion may be higher than the top surface of the first portion, and the bottom surface of the second portion may be coplanar with the bottom surface of the first portion.
[0009] According to an embodiment of the present invention, in the above transistor structure, the top surface of the gate dielectric layer may include a step profile. The bottom surface of the gate may include a step profile. The gate may be a polysilicon gate (poly gate).
[0010] According to an embodiment of the present invention, in the transistor structure, the first portion and the second portion may be integrally formed.
[0011] According to an embodiment of the present invention, in the transistor structure, a portion of the first drift region may be located directly below the second portion.
[0012] According to an embodiment of the present invention, in the transistor structure, a portion of the first drift region may be located directly below the dummy gate.
[0013] According to an embodiment of the present invention, in the transistor structure, a portion of the first drift region may be located directly below the gate.
[0014] According to an embodiment of the present invention, in the transistor structure, the dummy gate may be electrically connected to the second doped region.
[0015] According to an embodiment of the present invention, in the above transistor structure, the dummy gate may be separated from the gate.
[0016] According to an embodiment of the present invention, in the above transistor structure, a first isolation structure and a second isolation structure may also be included. The first isolation structure is located in the substrate. The first doped region may be located between the first isolation structure and the gate. The second isolation structure is located in the substrate. The second doped region may be located between the second isolation structure and the dummy gate.
[0017] According to an embodiment of the present invention, in the above transistor structure, a bottom surface of the first drift region may be lower than a bottom surface of the second isolation structure.
[0018] According to an embodiment of the present invention, the transistor structure may further include a bulk region. The bulk region is located in the substrate. The first doped region may be located between the bulk region and the gate.
[0019] According to an embodiment of the present invention, in the transistor structure, the body region may be connected to the first doped region.
[0020] According to an embodiment of the present invention, the transistor structure may further include a second drift region. The second drift region is located in the substrate on the other side of the gate. The first doped region may be located in the second drift region.
[0021] According to an embodiment of the present invention, the transistor structure may further include a first well region and a second well region. The first well region is located in the substrate. The first doped region, the second doped region and the first drift region may be located in the first well region. The second well region is located in the substrate. The first well region may be located in the second well region.
[0022] According to an embodiment of the present invention, in the transistor structure, the first well region may have a first conductivity type, and the first doped region, the second doped region, the first drift region and the second well region may have a second conductivity type.
[0023] According to an embodiment of the present invention, the transistor structure may further include a first metal silicide layer and a second metal silicide layer. The first metal silicide layer is located on the first doped region. The second metal silicide layer is located on the second doped region.
[0024] Based on the above, in the transistor structure proposed by the present invention, the gate dielectric layer includes a first portion and a second portion, and the thickness of the second portion is greater than the thickness of the first portion. In addition, the virtual gate is located on the second portion between the gate and the second doped region. Therefore, the size of the transistor structure can be effectively reduced, and the electrical performance of the transistor structure can be effectively improved (e.g., increasing the breakdown voltage, increasing the turn-on current and reducing the Kirk effect).
[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 are cross-sectional views of transistor structures according to some embodiments of the present invention;
[0027] Figure 2 sectional views of transistor structures according to some other embodiments of the present invention.
[0028] Description of Figure Numbers:
[0029] 10,20: Transistor structure
[0030] 100: substrate
[0031] 102: Gate dielectric layer
[0032] 104: Gate
[0033] 106,108: Doping area
[0034] 110,120: Drift zone
[0035] 112: Virtual gate
[0036] 114,116: Isolation structure
[0037] 118: Main area
[0038] 122,124: Well region
[0039] 126,128: Metal silicide layer
[0040] 130: Dielectric layer
[0041] 132,134,136: Interconnection structure
[0042] P1: Part 1
[0043] P2: Part 2
[0044] S1,S2,S5,S7,S8,S9: Bottom
[0045] S3, S4, S6: Top surface
[0046] T1, T2: thickness DETAILED DESCRIPTION
[0047] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.
[0048] Figure 1 is a cross-sectional view of a transistor structure according to some embodiments of the present invention.
[0049] Please refer to Figure 1 , the transistor structure 10 includes a substrate 100, a gate dielectric layer 102, a gate 104, a doped region 106, a doped region 108, a drift region 110, and a dummy gate 112. In some embodiments, the transistor structure 10 may be a laterally diffused metal oxide semiconductor (LDMOS) transistor structure. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have a first conductivity type (e.g., P type).
[0050] Hereinafter, the first conductivity type and the second conductivity type may be one and the other of the P-type conductivity type and the N-type conductivity type, respectively. That is, the first conductivity type and the second conductivity type are different conductivity types. In this embodiment, the first conductivity type may be the P-type conductivity type, and the second conductivity type may be the N-type conductivity type, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be the N-type conductivity type, and the second conductivity type may be the P-type conductivity type.
[0051] The gate dielectric layer 102 is located on the substrate 100. The gate dielectric layer 102 includes a first portion P1 and a second portion P2. The second portion P2 is connected to the first portion P1. The thickness T2 of the second portion P2 is greater than the thickness T1 of the first portion P1. The first portion P1 and the second portion P2 may be integrally formed. In the present embodiment, the second portion P2 may be embedded in the substrate 100. The bottom surface S2 of the second portion P2 may be lower than the bottom surface S1 of the first portion P1. The top surface S4 of the second portion P2 and the top surface S3 of the first portion P1 may be coplanar. The bottom surface S5 of the gate dielectric layer 102 may include the bottom surface S1 and the bottom surface S2. The bottom surface S5 of the gate dielectric layer 102 may include a stepped profile. The top surface S6 of the gate dielectric layer 102 may include the bottom surface S3 and the bottom surface S4. The top surface S6 of the gate dielectric layer 102 may be a flat surface. In some embodiments, the material of the gate dielectric layer 102 is, for example, silicon oxide.
[0052] The gate 104 is located on the first portion P1 and the second portion P2. The bottom surface S7 of the gate 104 may be a flat surface. In this embodiment, the gate 104 may be a metal gate.
[0053] The doped region 106 and the doped region 108 are located in the substrate 100 on both sides of the gate dielectric layer 102. In some embodiments, the doped region 106 can be used as a source, and the doped region 108 can be used as a drain. In some embodiments, the doped region 106 and the doped region 108 can have a second conductivity type (e.g., N-type).
[0054] The drift region 110 is located in the substrate 100 on one side of the gate 104. The doped region 108 is located in the drift region 110. In some embodiments, a portion of the drift region 110 may be located directly below the second portion P2. In some embodiments, a portion of the drift region 110 may be located directly below the gate 104. In some embodiments, the drift region 110 may have a second conductivity type (e.g., N-type).
[0055] The dummy gate 112 is located on the second portion P2 between the gate 104 and the doped region 108. The dummy gate 112 may be separated from the gate 104. In some embodiments, the dummy gate 112 may be electrically connected to the doped region 108. In some embodiments, a portion of the drift region 110 may be located directly below the dummy gate 112. In this embodiment, the dummy gate 112 may be a metal gate.
[0056] The transistor structure 10 may further include an isolation structure 114 and an isolation structure 116. The isolation structure 114 is located in the substrate 100. The doped region 106 may be located between the isolation structure 114 and the gate 104. The isolation structure 116 is located in the substrate 100. The doped region 108 may be located between the isolation structure 116 and the dummy gate 112. In some embodiments, the bottom surface S8 of the drift region 110 may be lower than the bottom surface S9 of the isolation structure 116. In some embodiments, the isolation structure 114 and the isolation structure 116 may be shallow trench isolation (STI) structures. In some embodiments, the material of the isolation structure 114 and the material of the isolation structure 116 are, for example, silicon oxide.
[0057] The transistor structure 10 may further include a body region 118. The body region 118 is located in the substrate 100. The doped region 106 may be located between the body region 118 and the gate 104. In some embodiments, the body region 118 may be connected to the doped region 106. In some embodiments, the body region 118 may have a first conductivity type (eg, P type).
[0058] The transistor structure 10 may further include a drift region 120. The drift region 120 is located in the substrate 100 on the other side of the gate 104. The doped region 106 may be located in the drift region 120. In some embodiments, a portion of the drift region 120 may be located directly below the first portion P1. In some embodiments, a portion of the drift region 120 may be located directly below the gate 104. In some embodiments, the drift region 120 may have a second conductivity type (e.g., N-type).
[0059] The transistor structure 10 may further include a well region 122 and a well region 124. The well region 122 is located in the substrate 100. The doped region 106, the doped region 108, the drift region 110, the body region 118, and the drift region 120 may be located in the well region 122. The well region 124 is located in the substrate 100. The well region 122 may be located in the well region 124. In some embodiments, the well region 122 may have a first conductivity type (e.g., P-type), and the well region 124 may have a second conductivity type (e.g., N-type).
[0060] The transistor structure 10 may further include a metal silicide layer 126 and a metal silicide layer 128. The metal silicide layer 126 is located on the doped region 106. The metal silicide layer 126 may also be located on the body region 118. The metal silicide layer 128 is located on the doped region 108. In some embodiments, the material of the metal silicide layer 126 and the material of the metal silicide layer 128 are, for example, cobalt silicide (CoSi) or nickel silicide (NiSi).
[0061] The transistor structure 10 may further include a dielectric layer 130. The dielectric layer 130 is located on the substrate 100 and covers the gate dielectric layer 102, the gate 104, the dummy gate 112, the isolation structure 114, the isolation structure 116, the metal silicide layer 126, and the metal silicide layer 128. In some embodiments, the dielectric layer 130 may be a multi-layer structure. In some embodiments, the material of the dielectric layer 130 is, for example, silicon oxide, silicon nitride, or a combination thereof.
[0062] The transistor structure 10 may further include an interconnect structure 132, an interconnect structure 134, and an interconnect structure 136. The interconnect structure 132 is electrically connected to the dummy gate 112 and the doped region 108. In some embodiments, the interconnect structure 132 may be electrically connected to the doped region 108 through the metal silicide layer 128. In some embodiments, the dummy gate 112 may be electrically connected to the doped region 108 through the interconnect structure 132 and the metal silicide layer 128. The interconnect structure 134 is electrically connected to the gate 104. The interconnect structure 136 is electrically connected to the doped region 106 and the body region 118. In some embodiments, the interconnect structure 136 may be electrically connected to the doped region 106 and the body region 118 through the metal silicide layer 126. In some embodiments, the interconnect structures 132, 134, and 136 may include contacts, wires, or a combination thereof. In some embodiments, the material of the interconnect structure 132 , the material of the interconnect structure 134 , and the material of the interconnect structure 136 are, for example, tungsten, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.
[0063] Based on the above embodiments, it can be known that in the transistor structure 10, the gate dielectric layer 102 includes a first portion P1 and a second portion P2, and the thickness T2 of the second portion P2 is greater than the thickness T1 of the first portion P1. In addition, the dummy gate 112 is located on the second portion P2 between the gate 104 and the doped region 108. Therefore, the size of the transistor structure 10 can be effectively reduced, and the electrical performance of the transistor structure 10 can be effectively improved (e.g., increasing the breakdown voltage, increasing the turn-on current, and reducing the Kirk effect).
[0064] Figure 2 are cross-sectional views of transistor structures according to some other embodiments of the present invention.
[0065] Please refer to Figure 2 and Figure 1 , Figure 2 The transistor structure 20 and Figure 1 The differences in the transistor structure 10 are as follows. Figure 2As shown, in the transistor structure 20, the top surface S4 of the second portion P2 may be higher than the top surface S3 of the first portion P1. In the transistor structure 20, the bottom surface S2 of the second portion P2 and the bottom surface S1 of the first portion P1 may be coplanar. In the transistor structure 20, the top surface S6 of the gate dielectric layer 102 may include a stepped profile. In the transistor structure 20, the bottom surface S5 of the gate dielectric layer 102 may be a flat surface. In the transistor structure 20, the bottom surface S7 of the gate 104 may include a stepped profile. In the transistor structure 20, the gate 104 may be a polysilicon gate. In the transistor structure 20, the dummy gate 112 may be a polysilicon gate.
[0066] Based on the above embodiments, it can be known that in the transistor structure 20, the gate dielectric layer 102 includes a first portion P1 and a second portion P2, and the thickness T2 of the second portion P2 is greater than the thickness T1 of the first portion P1. In addition, in the transistor structure 20, the dummy gate 112 is located on the second portion P2 between the gate 104 and the doped region 108. Therefore, the size of the transistor structure 20 can be effectively reduced, and the electrical performance of the transistor structure 20 can be effectively improved (e.g., increasing the breakdown voltage, increasing the on-current, and reducing the Kirk effect).
[0067] In summary, in the transistor structure of the above embodiment, the gate dielectric layer includes a first portion and a second portion, and the thickness of the second portion is greater than the thickness of the first portion. In addition, the virtual gate is located on the second portion between the gate and the second doped region. Therefore, the size of the transistor structure can be effectively reduced, and the electrical performance of the transistor structure can be effectively improved.
[0068] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.
Claims
1. A transistor structure, characterized in that: include: substrate; A gate dielectric layer, located on the substrate, and comprising: Part I; and a second portion connected to the first portion, wherein a thickness of the second portion is greater than a thickness of the first portion; a gate, located on the first portion and the second portion; A first doping region and a second doping region are located in the substrate on both sides of the gate dielectric layer; a first drift region located in the substrate at one side of the gate, wherein the second doped region is located in the first drift region; and A virtual gate is located on the second portion between the gate and the second doping region.
2. The transistor structure according to claim 1, characterized in that: The second portion is embedded in the substrate.
3. The transistor structure according to claim 1, characterized in that: The bottom surface of the second portion is lower than the bottom surface of the first portion, and The top surface of the second portion is coplanar with the top surface of the first portion.
4. The transistor structure according to claim 1, characterized in that: The bottom surface of the gate dielectric layer comprises a stepped profile, The bottom surface of the gate includes a flat surface, and The gate includes a metal gate.
5. The transistor structure according to claim 1, characterized in that: The top surface of the second portion is higher than the top surface of the first portion, and The bottom surface of the second portion is coplanar with the bottom surface of the first portion.
6. The transistor structure according to claim 1, characterized in that: The top surface of the gate dielectric layer comprises a stepped profile, The bottom surface of the gate comprises a stepped profile, and The gate includes a polysilicon gate.
7. The transistor structure according to claim 1, characterized in that: The first part and the second part are integrally formed.
8. The transistor structure according to claim 1, characterized in that: A portion of the first drift region is located directly below the second portion.
9. The transistor structure according to claim 1, characterized in that: A portion of the first drift region is located directly below the dummy gate.
10. The transistor structure according to claim 1, characterized in that: A portion of the first drift region is located directly below the gate.
11. The transistor structure according to claim 1, characterized in that: The dummy gate is electrically connected to the second doped region.
12. The transistor structure according to claim 1, characterized in that: The dummy gate is separated from the gate.
13. The transistor structure according to claim 1, characterized in that: Also includes: A first isolation structure is located in the substrate, wherein the first doped region is located between the first isolation structure and the gate; as well as The second isolation structure is located in the substrate, wherein the second doped region is located between the second isolation structure and the dummy gate.
14. The transistor structure according to claim 13, characterized in that: A bottom surface of the first drift region is lower than a bottom surface of the second isolation structure.
15. The transistor structure according to claim 1, characterized in that: Also includes: A main body region is located in the substrate, wherein the first doped region is located between the main body region and the gate.
16. The transistor structure according to claim 15, characterized in that: The body region is connected to the first doped region.
17. The transistor structure according to claim 1, characterized in that: Also includes: A second drift region is located in the substrate at the other side of the gate, wherein the first doped region is located in the second drift region.
18. The transistor structure according to claim 1, characterized in that: Also includes: A first well region is located in the substrate, wherein the first doped region, the second doped region and the first drift region are located in the first well region; as well as The second well region is located in the substrate, wherein the first well region is located in the second well region.
19. The transistor structure according to claim 18, characterized in that: The first well region has a first conductivity type, and the first doped region, the second doped region, the first drift region, and the second well region have a second conductivity type.
20. The transistor structure according to claim 1, characterized in that Also includes: A first metal silicide layer, located on the first doped region; as well as The second metal silicide layer is located on the second doped region.