Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; an initial first mask layer and a first dielectric layer located on the initial first mask layer are formed on the substrate, an initial opening is formed in the first dielectric layer, and the initial opening exposes the surface of the initial first mask layer; forming a first micro groove in the initial first mask layer exposed out of the initial opening by adopting a first etching process, wherein the distance from the first micro groove to the two opposite side walls of the initial opening is greater than zero; thinning the height of the first dielectric layer; forming a second micro groove in the initial first mask layer exposed out of the initial opening by adopting a second etching process, wherein the second micro groove is positioned at the bottoms of the two opposite side walls of the initial opening; and etching the initial first mask layer at the bottoms of the first micro-groove and the second micro-groove to form a mask opening, and enabling the initial first mask layer to become a first mask layer. According to the forming method of the semiconductor structure, the forming steps of a small-size structure are simplified, and the cost of a small-size etching process is saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices continues to decrease. In the process of preparing semiconductor devices, the exposure and etching technology used are important factors that determine the final structure and performance of the device. For small-sized semiconductor devices, as their size continues to shrink, the requirements for exposure and etching technology are getting higher and higher.

[0003] In current technology, double exposure technology can be used to break through the size limit of traditional photolithography process and realize the preparation of small-size structures. Among them, the mainstream double exposure technology mainly includes litho-etch-litho-etch (LELE) and self-aligned double exposure (SADP).

[0004] However, in the prior art, the process that can realize the formation of small-sized devices often has complicated steps and high process costs. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which simplifies the steps for forming a small-size structure and saves the cost of a small-size etching process.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial first mask layer and a first dielectric layer located on the initial first mask layer on the substrate, wherein the first dielectric layer has an initial opening, and the initial opening exposes the surface of the initial first mask layer; using a first etching process to form a first micro groove in the initial first mask layer exposed by the initial opening, and the distance from the first micro groove to the opposite side walls of the initial opening is greater than zero; thinning the height of the first dielectric layer; using a second etching process to form a second micro groove in the initial first mask layer exposed by the initial opening, and the second micro groove is located at the bottom of the opposite side walls of the initial opening; etching the initial first mask layer at the bottom of the first micro groove and the second micro groove to form a mask opening, the width of the mask opening is greater than the width of the first micro groove and the second micro groove, and the mask opening penetrates the initial first mask layer, and the initial first mask layer becomes the first mask layer.

[0007] Optionally, when forming the first micro groove, the aspect ratio of the initial opening is greater than 2:1.

[0008] Optionally, the aspect ratio of the initial opening is in the range of 100:1 to 2:1.

[0009] Optionally, the number of the first micro grooves is equal to 1.

[0010] Optionally, the first micro groove is located at the center of the bottom surface of the initial opening.

[0011] Optionally, the first etching process includes a plasma etching process.

[0012] Optionally, the process parameters of the plasma etching process include: the etching gas used includes chlorine-based gas or fluorine-based gas; the input radio frequency power used is 1kW to 10kW; the electron temperature of the plasma is 1eV to 10eV; the density of the plasma is 10 15 ions / m 3 ~10 18 ions / m 3 The ionization rate of the plasma is 10 -7 ~10 -4 .

[0013] Optionally, an angle between a side wall of the initial opening and the surface of the substrate is 30 degrees to 90 degrees.

[0014] Optionally, the method for forming the first dielectric layer includes: forming an initial first dielectric material layer and an initial top mask layer located on the initial first dielectric material layer on the initial first mask layer; etching the initial top mask layer to form a top mask opening, wherein the top mask opening exposes a portion of the surface of the initial first dielectric material layer, and the initial top mask layer becomes the top mask layer; using the top mask layer as a mask, etching the initial first dielectric material layer to form an initial opening, and the initial first dielectric material layer becomes the first dielectric layer.

[0015] Optionally, the etching selectivity ratio of the initial top mask layer to the initial first dielectric material layer is in the range of 1:1 to 1:3.

[0016] Optionally, the number of the second micro grooves is equal to 2.

[0017] Optionally, after the height of the first dielectric layer is thinned, the aspect ratio of the initial opening in the first dielectric layer is 1:2 to 1:1.

[0018] Optionally, the process of reducing the height of the first dielectric layer includes a chemical mechanical polishing process or an etch-back process.

[0019] Optionally, the second etching process includes a plasma etching process.

[0020] Optionally, after forming the second micro groove and before forming the mask opening, the method further includes: removing the first dielectric layer.

[0021] Optionally, the material of the initial first mask layer includes titanium nitride, silicon oxide, silicon nitride or aluminum oxide.

[0022] Optionally, there is an initial bottom dielectric material layer between the substrate and the first mask layer; after forming the first mask layer, it also includes: using the first mask layer as a mask, etching the initial bottom dielectric material layer, forming a groove structure in the initial bottom dielectric material layer, and the initial bottom dielectric material layer becomes the bottom dielectric layer.

[0023] Optionally, the width of the groove structure is less than half of the width of the initial opening.

[0024] Optionally, the width of the groove structure ranges from 25 nanometers to 1000 nanometers.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, in the etching process for forming the first micro-grooves and the second micro-grooves, after the etching gas particles contact the sidewalls of the initial opening, they are reflected and reach the initial first mask layer at the bottom of the initial opening, thereby achieving an etching effect. Therefore, the formation positions of the first micro-grooves and the second micro-grooves are related to the depth-to-width ratio of the initial opening. After forming the first micro-grooves, the height of the first dielectric layer is thinned to reduce the depth-to-width ratio of the initial opening in the first dielectric layer. Therefore, the contact range and concentration of the etching gas on the surface of the initial first mask layer are adjusted, so that the position of the second micro-grooves is different from that of the first micro-grooves. Thus, through the etching of the micro-grooves twice, the number of mask openings of the first mask layer formed subsequently is increased, and the flexibility of the pattern is increased. At the same time, by etching the first micro-grooves and the second micro-grooves to open the initial first mask layer, the formation of the mask opening and the groove structure breaks through the size limit of the traditional photolithography process, and eliminates the material layer required for multiple transfers of the pattern in the traditional double exposure process, saving costs.

[0027] Furthermore, when forming the first microgroove, the aspect ratio of the initial opening is greater than 2:1. By controlling the aspect ratio of the initial opening, the contact range of the etching gas on the surface of the initial first mask layer is controlled, so that the distance from the formed first microgroove to the side walls on both sides of the initial opening is greater than zero, thereby increasing the flexibility of the subsequently formed first mask layer pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 7It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background technology, the existing mainstream double exposure technology mainly includes exposure-etching-exposure-etching process and self-aligned double exposure process. However, such process usually requires additional graphic material layer or mask for graphic transfer or etching, and each additional exposure process doubles the cost of graphic processing, which makes the etching process steps of small-size devices complicated and the process cost is high.

[0030] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure. After forming a first dielectric layer with an initial opening and a first micro-groove located at the bottom of the initial opening, the height of the first dielectric layer is thinned to reduce the aspect ratio of the initial opening in the first dielectric layer, and then a second micro-groove is formed. Thus, by adjusting the aspect ratio of the initial opening, the contact range and concentration of the etching gas are adjusted, so that the position of the second micro-groove is different from that of the first micro-groove. Therefore, through the etching of the micro-grooves twice, the number of mask openings of the first mask layer formed subsequently is increased, and the flexibility of the pattern is increased.

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 7 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 1 , providing a substrate 100.

[0034] The material of the substrate 100 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc. Specifically, in this embodiment, the material of the substrate 100 is silicon.

[0035] Please refer to Figure 2 An initial bottom dielectric material layer 101 , an initial first mask layer 102 on the initial bottom dielectric material layer 101 , an initial first dielectric material layer 103 on the initial first mask layer 102 , and an initial top mask layer 104 on the initial first dielectric material layer 103 are formed on the substrate 100 .

[0036] In this embodiment, the material of the initial bottom dielectric material layer 101 includes silicon oxide. The initial bottom dielectric material layer 101 provides space for the trench structure formed subsequently.

[0037] In this embodiment, the material of the initial first mask layer 102 includes titanium nitride, silicon nitride, silicon oxide or aluminum oxide.

[0038] In this embodiment, the material of the initial first dielectric material layer 103 includes silicon oxide.

[0039] In this embodiment, the material of the initial top mask layer 104 includes titanium nitride, silicon nitride, silicon oxide or aluminum oxide.

[0040] Please refer to Figure 3 , an initial opening 120 is formed in the initial first dielectric material layer 103 , the initial opening 120 exposes a portion of the surface of the initial first mask layer 102 , and the initial first dielectric material layer 103 becomes the first dielectric layer 113 .

[0041] Specifically, the method for forming the initial opening 120 and the first dielectric layer 113 includes: etching the initial top mask layer 104 to form an initial top mask opening (not marked), wherein the initial top mask opening exposes a portion of the surface of the initial first dielectric material layer 103, and the initial top mask layer 104 becomes the top mask layer 114; using the top mask layer 114 as a mask, etching the initial first dielectric material layer 103 to form the initial opening 120, and the initial first dielectric material layer 103 becomes the first dielectric layer 113.

[0042] In this embodiment, the process of etching the surface of the initial top mask layer 104 and the initial first dielectric material layer 103 includes a dry etching process. In the etching process, the etching selectivity ratio of the initial top mask layer 104 to the initial first dielectric material layer 103 ranges from 1:1 to 1:3.

[0043] In this embodiment, the aspect ratio of the initial opening 120 is greater than 2: 1. The aspect ratio of the initial opening 120 determines the position and number of the first micro grooves formed after the initial first mask layer 102 is subsequently etched.

[0044] Specifically, in this embodiment, the aspect ratio of the initial opening 120 is in the range of 100: 1 to 2: 1. The width of the initial opening 120 is the dimension of the initial opening 120 parallel to the surface of the substrate 100, and the depth of the initial opening 120 is the dimension of the initial opening 120 perpendicular to the surface of the substrate 100.

[0045] In this embodiment, the angle between the sidewall of the initial opening 120 and the surface of the substrate 100 is 30 degrees to 90 degrees.

[0046] In this embodiment, the width of the initial opening 120 ranges from 50 nanometers to 2000 nanometers.

[0047] In this embodiment, the structure of the initial opening 120 includes a groove. In other embodiments, the structure of the initial opening also includes a circular through hole.

[0048] Please refer to Figure 4 A first etching process is used to form a first micro groove 121 in the initial first mask layer 102 exposed by the initial opening 120 , and the distance between the first micro groove 121 and the opposite side walls of the initial opening 120 is greater than zero.

[0049] In this embodiment, the bottom surface of the first micro groove 121 is higher than the bottom surface of the initial first mask layer 102, that is, the existence of the first micro groove 121 only carves the surface of the initial first mask layer 102, but the first micro groove 121 does not penetrate the initial first mask layer 102. In addition, the width of the first micro groove 121 is less than 1 / 3 of the width of the initial opening 120.

[0050] In this embodiment, the first micro groove 121 provides conditions for the subsequent formation of a mask opening. The mask opening is subsequently formed by etching the initial first mask layer 102 at the bottom of the first micro groove 121, thereby defining the pattern and position of the groove structure.

[0051] Specifically, in this embodiment, the number of the first micro groove 121 is equal to 1; the first micro groove 121 is located at the center of the bottom surface of the initial opening 120 .

[0052] In this embodiment, the first etching process includes a plasma etching process.

[0053] In the plasma etching process, after the etching gas particles contact the side walls of the initial opening 120, they are reflected and reach the initial first mask layer 102 at the bottom of the initial opening 120, thereby etching the initial first mask layer 102 to form a first micro-groove 121. Therefore, the formation position of the first micro-groove 121 is related to the aspect ratio of the initial opening 120. The aspect ratio of the initial opening 120 affects the contact point of the etching gas particles on the side walls of the initial opening 120 and the position reflected on the initial first mask layer 102 at the bottom of the initial opening 120, thereby affecting the position and number of the first micro-grooves 121.

[0054] In this embodiment, when forming the first micro-groove 121, the aspect ratio of the initial opening 120 is 100:1 to 2:1. By controlling the aspect ratio of the initial opening 120, the contact range of the etching gas on the surface of the initial first mask layer 102 is controlled, so that the formed first micro-groove 121 is located at the center of the bottom surface of the initial opening 120. At the same time, since the contact range of the etching gas on the surface of the initial first mask layer 102 is relatively concentrated, the number of the first micro-grooves 121 formed is equal to 1.

[0055] Specifically, in this embodiment, the process parameters of the plasma etching process include: the etching gas used includes chlorine-based gas or fluorine-based gas; the input radio frequency power used is 1kW to 10kW; the electron temperature of the plasma is 1eV to 10eV; the density of the plasma is 10 15 ions / m 3 ~10 18 ions / m 3 The ionization rate of the plasma is 10 -7 ~10 -4 The above process parameters combined with the aspect ratio of the initial opening 120 together ensure the formation of the first micro groove 121 .

[0056] Please refer to Figure 5 , the height of the first dielectric layer 113 is thinned; a second etching process is used to form a second micro groove 122 in the initial first mask layer 102 exposed by the initial opening 120, and the second micro groove 122 is located at the bottom of the side walls on both sides of the initial opening 120.

[0057] In this embodiment, after the height of the first dielectric layer 113 is thinned, the aspect ratio of the initial opening 120 in the first dielectric layer 113 is 1:2 to 1:1.

[0058] In this embodiment, the number of the formed second micro grooves 122 is equal to two.

[0059] In this embodiment, the second etching process includes a plasma etching process.

[0060] After forming the first micro-groove 121, the height of the first dielectric layer 113 is thinned to reduce the aspect ratio of the initial opening 120 in the first dielectric layer 113. Since the aspect ratio of the initial opening 120 affects the contact position of the etching gas particles on the initial first mask layer 102 at the bottom of the initial opening 120, the contact range and concentration of the etching gas on the surface of the initial first mask layer 102 are adjusted, so that the position of the second micro-groove 122 formed by etching is different from the position of the first micro-groove 121. Therefore, through the etching of the micro-grooves twice, the number of mask openings of the first mask layer 112 formed subsequently is increased, and the flexibility of the pattern is increased.

[0061] In this embodiment, the specific process parameters of the second etching process are: the etching gas used includes chlorine-based gas or fluorine-based gas; the input RF power used is 1kW to 10kW; the electron temperature of the plasma is 1eV to 10eV; the density of the plasma is 10 15 ions / m 3 ~10 18 ions / m 3 The ionization rate of the plasma is 10 -7 ~10 -4 The above process parameters combined with the aspect ratio of the initial opening 120 after the first dielectric layer 113 is thinned together ensure the formation of the second micro groove 122 .

[0062] In this embodiment, the shape, structure and size of the second micro groove 122 are the same as those of the first micro groove 121, and the second micro groove 122 is located on both sides of the first micro groove 121. The first micro groove 121 and the second micro groove 122 together provide conditions for the formation of subsequent mask openings, and subsequently, the mask openings are formed by etching the initial first mask layer 102 at the bottom of the first micro groove 121 and the second micro groove 122, thereby defining the pattern and position of the subsequent groove structure.

[0063] In this embodiment, the process of reducing the height of the first dielectric layer 113 includes a chemical mechanical polishing process.

[0064] In this embodiment, after the height of the first dielectric layer 113 is thinned, the aspect ratio of the initial opening 120 in the first dielectric layer 113 is reduced to 1:2 to 1:1. The chemical mechanical polishing process first removes the top mask layer 114 on the first dielectric layer 113, and then thins the height of the first dielectric layer 113. The degree of thinning of the height of the first dielectric layer 113 depends on the thickness of the initial first dielectric material layer 103 and the initial top mask layer 104.

[0065] In another embodiment, the process of reducing the height of the first dielectric layer includes an etch-back process.

[0066] Please refer to Figure 6 , remove the first dielectric layer 113; etch the initial first mask layer 102 at the bottom of the first micro groove 121 and the second micro groove 122 to form a mask opening 130, the width of the mask opening 130 is greater than the width of the first micro groove 121 and the second micro groove 122, the mask opening 130 exposes the surface of the initial bottom dielectric material layer 101, and the initial first mask layer 102 becomes the first mask layer 112.

[0067] In this embodiment, the process of etching the initial first mask layer 102 at the bottom of the first micro groove 121 and the second micro groove 122 includes a plasma etching process.

[0068] In this embodiment, the width of the bottom of each mask opening 130 ranges from 25 nanometers to 1000 nanometers.

[0069] Due to the existence of the first microgrooves 121 and the second microgrooves 122, the initial first mask layer 102 is opened by etching the first microgrooves 121 and the second microgrooves 122, so that the formation of the mask opening 130 breaks through the size limit of the traditional photolithography process, and eliminates the material layer required for multiple transfers of the pattern in the traditional double exposure process, and can directly achieve the reduction of the feature size through the etching of the microgrooves, saving costs. In addition, the pattern of the mask opening 130 can be adjusted by adjusting the aspect ratio of the initial opening 120, adjusting the number and position of the microgrooves, and thus more flexibly realizing the design of a variety of small-size mask patterns.

[0070] Please refer to Figure 7 , using the first mask layer 112 as a mask, etching the initial bottom dielectric material layer 101 to form a trench structure 140 in the initial bottom dielectric material layer 101 , and the initial bottom dielectric material layer 101 becomes a bottom dielectric layer 111 .

[0071] In this embodiment, the width of the groove structure 140 is less than half of the width of the initial opening 120, thereby realizing the preparation of a small-sized groove structure 140. Specifically, the width of the groove structure 140 ranges from 25 nanometers to 1000 nanometers.

[0072] In this embodiment, the process of etching the initial bottom dielectric material layer 101 includes a dry etching process.

[0073] Among them, by etching the first micro groove 121 and the second micro groove 122 to open the initial first mask layer 102, the formation of the mask opening 130 and the groove structure 140 breaks through the size limit of the traditional photolithography process, and eliminates the material layer required for multiple transfers of the pattern in the traditional double exposure process, and can directly achieve the reduction of the characteristic size of the groove structure 140 through the etching of the micro groove, saving costs. In addition, by forming the micro groove twice, the pattern defined by the first mask layer 112 is adjusted, which can ensure that the groove structure 140 of small size is formed, so that it has higher flexibility and diversity.

[0074] In other embodiments, after the initial bottom dielectric material layer is etched using the first mask layer as a mask, a circular through-hole structure is formed in the initial bottom dielectric material layer.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming an initial first mask layer and a first dielectric layer on the initial first mask layer on the substrate, wherein the first dielectric layer has an initial opening, and the initial opening exposes a surface of the initial first mask layer; Using a first etching process to form a first micro-groove in the initial first mask layer exposed by the initial opening, wherein the distance between the first micro-groove and the opposite side walls of the initial opening is greater than zero; Reducing the height of the first dielectric layer; Using a second etching process to form a second micro-groove in the initial first mask layer exposed by the initial opening, the second micro-groove being located at the bottom of the sidewalls on opposite sides of the initial opening; The initial first mask layer at the bottom of the first micro groove and the second micro groove is etched to form a mask opening, wherein the width of the mask opening is greater than the width of the first micro groove and the second micro groove, and the mask opening penetrates the initial first mask layer, and the initial first mask layer becomes a first mask layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: When forming the first micro groove, the aspect ratio of the initial opening is greater than 2:

1.

3. The method for forming a semiconductor structure according to claim 2, wherein: The initial opening has a depth-to-width ratio ranging from 100:1 to 2:

1.

4. The method for forming a semiconductor structure according to claim 1, wherein: The number of the first micro grooves is equal to 1.

5. The method for forming a semiconductor structure according to claim 1, wherein: The first micro groove is located at the center of the bottom surface of the initial opening.

6. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes a plasma etching process.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process parameters of the plasma etching process include: the etching gas used includes chlorine-based gas or fluorine-based gas; the input radio frequency power used is 1kW to 10kW; the electron temperature of the plasma is 1eV to 10eV; the density of the plasma is 10 15 ions / m 3 ~10 18 ions / m 3 ; The ionization rate of the plasma is 10 -7 ~10 -4 .

8. The method for forming a semiconductor structure according to claim 1, wherein: The included angle between the side wall of the initial opening and the surface of the substrate is 30 degrees to 90 degrees.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first dielectric layer includes: forming an initial first dielectric material layer and an initial top mask layer located on the initial first dielectric material layer on the initial first mask layer; etching the initial top mask layer to form a top mask opening, wherein the top mask opening exposes a portion of the surface of the initial first dielectric material layer, and the initial top mask layer becomes the top mask layer; using the top mask layer as a mask, etching the initial first dielectric material layer to form an initial opening, and the initial first dielectric material layer becomes the first dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The etching selectivity ratio of the initial top mask layer to the initial first dielectric material layer is in the range of 1:1 to 1:

3.

11. The method for forming a semiconductor structure according to claim 1, wherein: The number of the second micro grooves is equal to 2.

12. The method for forming a semiconductor structure according to claim 1, wherein: After the height of the first dielectric layer is thinned, the aspect ratio of the initial opening in the first dielectric layer is 1:2 to 1:

1.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of reducing the height of the first dielectric layer includes a chemical mechanical polishing process or an etch-back process.

14. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process includes a plasma etching process.

15. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second micro groove and before forming the mask opening, the method further includes: removing the first dielectric layer.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial first mask layer includes titanium nitride, silicon oxide, silicon nitride or aluminum oxide.

17. The method for forming a semiconductor structure according to claim 1, wherein: An initial bottom dielectric material layer is also provided between the substrate and the first mask layer; After forming the first mask layer, the method further comprises: The initial bottom dielectric material layer is etched using the first mask layer as a mask to form a trench structure in the initial bottom dielectric material layer, and the initial bottom dielectric material layer becomes a bottom dielectric layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The width of the trench structure is less than half of the width of the initial opening.

19. The method for forming a semiconductor structure according to claim 17, wherein: The width of the groove structure ranges from 25 nanometers to 1000 nanometers.

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