Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a first stop layer on the first dielectric layer, wherein a first opening is formed in the first stop layer; forming a second dielectric layer on the first dielectric layer and the first stop layer; forming a mask structure on the second dielectric layer, wherein the mask structure is internally provided with a second opening; the second dielectric layer is etched with the second opening as a mask, a first groove is formed in the second dielectric layer, and a part of the surface of the first stop layer is exposed out of the first groove; the first dielectric layer is etched with the first groove and the first stop layer as masks, a second groove is formed in the first dielectric layer, the second groove is communicated with the first groove, the second groove is exposed out of the surface of the substrate, and the projection range of the second groove on the substrate is located in the projection range of the first groove on the substrate; and forming a metal structure in the first groove and the second groove. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor back-end metal interconnection process, the Damascus structure is often used for copper metal interconnection.

[0003] The existing back-end metal interconnection process needs to be improved. Summary of the invention

[0004] The technical problem solved by the invention is to provide a method for forming a semiconductor structure to improve the back-end metal interconnection process.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first dielectric layer on the substrate; forming a first stop layer on the first dielectric layer, wherein the first stop layer has a first opening, and the first opening exposes a portion of the surface of the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the first stop layer; forming a mask structure on the second dielectric layer, wherein the mask structure has a second opening, and the projection range of the first opening on the substrate is located within the projection range of the second opening on the substrate; etching the second dielectric layer using the second opening as a mask to form a first groove in the second dielectric layer, wherein the first groove exposes a portion of the surface of the first stop layer; etching the first dielectric layer using the first groove and the first stop layer as masks to form a second groove in the first dielectric layer, wherein the second groove is connected to the first groove, the second groove exposes the substrate surface, and the projection range of the second groove on the substrate is located within the projection range of the first groove on the substrate; forming a metal structure in the first groove and in the second groove.

[0006] Optionally, the mask structure includes: an underlying structure and a photoresist layer located on the underlying structure, the second opening is located in the photoresist layer, and the second opening exposes a portion of the surface of the underlying structure.

[0007] Optionally, the underlying structure includes: a liner layer and an anti-reflection layer located on the liner layer.

[0008] Optionally, the material of the liner layer includes amorphous carbon; and the material of the anti-reflection layer includes a dielectric anti-reflection layer.

[0009] Optionally, the material of the underlying structure includes metal oxide or metal nitride; the metal oxide includes aluminum oxide or titanium oxide; and the metal nitride includes titanium nitride.

[0010] Optionally, the material of the underlying structure includes an inorganic non-metallic material; the inorganic non-metallic material includes silicon nitride.

[0011] Optionally, in a process of etching the second dielectric layer using the second opening as a mask, an etching rate of the second dielectric layer is greater than an etching rate of the underlying structure.

[0012] Optionally, the process of etching the second dielectric layer using the second opening as a mask includes a dry etching process; parameters of the dry etching process include: etching gas includes a fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

[0013] Optionally, the material of the second dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

[0014] Optionally, in a process of etching the first dielectric layer using the first groove and the first stop layer as a mask, an etching rate of the first stop layer is lower than an etching rate of the first dielectric layer.

[0015] Optionally, the process of etching the first dielectric layer using the first groove and the first stop layer as a mask includes a dry etching process; parameters of the dry etching process include: the etching gas includes a fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

[0016] Optionally, the material of the first stop layer includes nitrogen-doped silicon carbide, oxygen-doped silicon carbide or silicon nitride.

[0017] Optionally, the material of the first dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

[0018] Optionally, a process of etching the second dielectric layer using the second opening as a mask and a process of etching the first dielectric layer using the first groove and the first stop layer as a mask are the same process.

[0019] Optionally, before forming the first dielectric layer on the substrate, the method further includes: forming a second stop layer on the substrate.

[0020] Optionally, the material of the second stop layer includes nitrogen-doped silicon carbide, oxygen-doped silicon carbide or silicon nitride.

[0021] Optionally, the substrate includes: a base; a device layer located on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; a third dielectric layer located on the device layer; a conductive layer located within the third dielectric layer, the conductive layer being electrically connected to the device structure.

[0022] Optionally, the second groove exposes the surface of the conductive layer; and the metal structure is electrically connected to the conductive layer.

[0023] Optionally, the method for forming the first stop layer includes: forming a stop material layer on the first dielectric layer; forming a patterned mask layer on the stop material layer, wherein the patterned mask layer exposes a portion of the stop material layer surface on the conductive layer; etching the stop material layer using the patterned mask layer as a mask until the surface of the first dielectric layer is exposed, thereby forming the first stop layer and a first opening located in the first stop layer.

[0024] Optionally, the material of the metal structure includes copper.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] The technical solution of the present invention is to first form a first stop layer on a first dielectric layer, wherein the first stop layer has a first opening, and then form a second dielectric layer on the first dielectric layer and the first stop layer. Under the blocking effect of the first stop layer, when the second dielectric layer is etched with the mask structure as a mask to form a first groove, the first dielectric layer will not be etched directly. Subsequently, the first dielectric layer can be etched with the first groove and the first stop layer as masks to form a second groove connected to the first groove, so that the projection range of the formed second groove on the substrate is located within the projection range of the first groove on the substrate. The method can form a first groove and a second groove connected in one process flow, and the process flow is simple, reducing process damage, so that the metal structure can be filled into the first groove and the second groove at one time, and the ultra-thick metal structure formed is more compact and has a smaller resistance, thereby improving the performance of the semiconductor structure.

[0027] Furthermore, the mask structure includes an underlying structure and a photoresist layer located on the underlying structure, and the etching rate of the second dielectric layer in the process of etching the second opening as a mask is greater than the etching rate of the underlying structure. Therefore, the process of etching the second dielectric layer has a large etching selectivity ratio between the second dielectric layer and the underlying structure, and in the case of a large depth-width ratio of the first groove at an advanced technology node, the underlying structure is consumed slowly, plays a good masking role, and can form a first groove with a good morphology and a large depth-width ratio.

[0028] Furthermore, the etching rate of the first stop layer in the process of etching the first dielectric layer using the first groove and the first stop layer as a mask is lower than the etching rate of the first dielectric layer. Therefore, the process of etching the first dielectric layer has a larger etching selectivity ratio between the first stop layer and the first dielectric layer, so that the first dielectric layer can continue to be etched using the first stop layer and the first groove as a mask, so that the projection range of the formed second groove on the substrate is located within the projection range of the first groove on the substrate, so as to meet the device requirements.

[0029] Furthermore, the process of etching the second dielectric layer using the second opening as a mask is the same as the process of etching the first dielectric layer using the first groove and the first stop layer as a mask, so that the first groove and the second groove connected to each other can be formed by one process, meeting the device requirements, simplifying the process flow, and reducing process damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 and Figure 2 is a schematic structural diagram of a semiconductor structure forming process in one embodiment;

[0031] Figures 3 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the existing back-end metal interconnection process needs to be improved.

[0033] Figure 1 and Figure 2 It is a structural schematic diagram of a semiconductor structure forming process in one embodiment.

[0034] Please refer to Figure 1 , providing a substrate, the substrate comprising: a base 100; a device layer (not shown) located on the base, the device layer comprising an isolation structure and a device structure located in the isolation structure; a first dielectric layer 101 located on the device layer; a conductive layer 102 located in the first dielectric layer 101, the conductive layer 102 being electrically connected to the device structure; a second dielectric layer 103 being formed on the substrate; a first metal layer 104 being formed in the second dielectric layer 103, the first metal layer 104 being electrically connected to the conductive layer 102.

[0035] Please refer to Figure 2 , forming a third dielectric layer 105 on the second dielectric layer 103 and the first metal layer 104; forming a second metal layer 106 in the third dielectric layer 105, and the projection range of the first metal layer 104 on the substrate is located within the projection range of the second metal layer 106 on the substrate.

[0036] The semiconductor structure, the first metal layer 104 and the second metal layer 106 on the first metal layer 104 form a Damascus structure, the Damascus structure is located in a multi-layer dielectric layer, and is an ultra-thick Damascus structure. Since the first metal layer 104 and the ultra-thick Damascus structure formed by the first metal layer 104 have a large aspect ratio, the existing etching process cannot form a groove of the Damascus structure in the dielectric layer in one step while ensuring a good morphology. Therefore, it is necessary to form the first metal layer 104 first, and then form the second metal layer 106.

[0037] During the formation of the semiconductor structure, the second dielectric layer 103 and the first metal layer 104 located in the second dielectric layer 103 are first formed, and then an opening is formed in the third dielectric layer 105 to expose the first metal layer 104, and the second metal layer 106 is formed in the opening. In the process of forming the opening, the surface of the first metal layer 104 is easily damaged, so that the surface roughness of the first metal layer 104 increases, and the contact resistance between the first metal layer 104 and the second metal layer 106 increases, which affects the performance of the semiconductor structure; in addition, the formation of the first metal layer 104 and the second metal layer 106 requires two etching processes and two copper planarization processes, which takes a long time to produce and is costly.

[0038] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by first forming a first stop layer on a first dielectric layer, wherein the first stop layer has a first opening, and then forming a second dielectric layer on the first dielectric layer and the first stop layer. Under the blocking effect of the first stop layer, when the second dielectric layer is etched with the mask structure as a mask to form a first groove, the first dielectric layer will not be etched directly. Subsequently, the first dielectric layer can be etched with the first groove and the first stop layer as a mask to form a second groove connected to the first groove, so that the projection range of the formed second groove on the substrate is located within the projection range of the first groove on the substrate. The method can form a first groove and a second groove connected in one process flow, and the process flow is simple, which reduces process damage, so that the metal structure can be filled into the first groove and the second groove at one time, and the structure of the metal structure is more compact, has a smaller resistance, and improves the performance of the semiconductor structure.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 3 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0041] Please refer to Figure 3 , providing a substrate.

[0042] The substrate includes: a base 200; a device layer (not shown) located on the base 200, the device layer including an isolation structure and a device structure located in the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; a third dielectric layer 201 located on the device layer; and a conductive layer 202 located in the third dielectric layer 201, the conductive layer 202 being electrically connected to the device structure.

[0043] In this embodiment, the material of the substrate 200 is silicon.

[0044] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] Please continue to refer to Figure 3 , a second stop layer 203 is formed on the substrate.

[0046] The second stop layer 203 is used as an etching stop layer when the first dielectric layer is subsequently etched.

[0047] The material of the second stop layer 203 includes nitrogen-doped silicon carbide (NDC), oxygen-doped silicon carbide (ODC) or silicon nitride.

[0048] In this embodiment, the material of the second stop layer 203 includes oxygen-doped silicon carbide. The oxygen-doped silicon carbide has a smaller dielectric constant, and the parasitic capacitance generated when it is subsequently located between two metal layers is smaller.

[0049] Please continue to refer to Figure 3 , a first dielectric layer 204 is formed on the second stop layer 203 .

[0050] The material of the first dielectric layer 203 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0051] In this embodiment, the material of the first dielectric layer 203 includes silicon oxide. The silicon oxide material has a relatively small dielectric constant, and the parasitic capacitance generated when it is subsequently located between two metal layers is relatively small.

[0052] Next, a first stop layer is formed on the first dielectric layer 204, wherein the first stop layer has a first opening, and the first opening exposes a portion of the surface of the first dielectric layer. Figure 3 and Figure 4.

[0053] Please continue to refer to Figure 3 , forming a stop material layer 205 on the first dielectric layer 204 ; forming a patterned mask layer 206 on the stop material layer 205 , wherein the patterned mask layer 206 exposes a portion of the stop material layer 205 surface on the conductive layer 202 .

[0054] The material of the stop material layer 205 includes nitrogen-doped silicon carbide (NDC), oxygen-doped silicon carbide (ODC) or silicon nitride.

[0055] In this embodiment, the material of the stop material layer 205 includes oxygen-doped silicon carbide. The oxygen-doped silicon carbide has a smaller dielectric constant, and the parasitic capacitance generated when it is subsequently located between two metal layers is smaller.

[0056] In this embodiment, the material of the patterned mask layer 206 includes photoresist.

[0057] Please refer to Figure 4 The stop material layer 205 is etched using the patterned mask layer 206 as a mask until the surface of the first dielectric layer 204 is exposed, thereby forming a first stop layer 207 and a first opening 208 located in the first stop layer 207 .

[0058] The process of etching the stop material layer 205 using the patterned mask layer 206 as a mask includes a dry etching process.

[0059] Please refer to Figure 5 A second dielectric layer 209 is formed on the first dielectric layer 204 and the first stop layer 207 .

[0060] The material of the second dielectric layer 209 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0061] In this embodiment, the material of the second dielectric layer 209 includes silicon oxide. The silicon oxide material has a relatively small dielectric constant, and the parasitic capacitance generated when it is subsequently located between two metal layers is relatively small.

[0062] Please continue to refer to Figure 5 A mask structure is formed on the second dielectric layer 209 , wherein the mask structure has a second opening 213 , and a projection range of the first opening 208 on the substrate is within a projection range of the second opening 213 on the substrate.

[0063] The mask structure includes: an underlying structure and a photoresist layer 212 on the underlying structure, wherein the second opening 213 is located in the photoresist layer 212, and the second opening 213 exposes a portion of the surface of the underlying structure. The material of the underlying structure and the material of the second dielectric layer 209 have a large etching selectivity in the subsequent etching process.

[0064] In this embodiment, the underlying structure includes: a liner layer 210 and an anti-reflection layer 211 located on the liner layer 210 .

[0065] The material of the liner layer 210 includes amorphous carbon; the material of the anti-reflection layer 211 includes a dielectric anti-reflection layer.

[0066] In other embodiments, the material of the underlying structure includes metal oxide or metal nitride; the metal oxide includes aluminum oxide or titanium oxide; and the metal nitride includes titanium nitride.

[0067] In other embodiments, the material of the underlying structure includes an inorganic non-metallic material; and the inorganic non-metallic material includes silicon nitride.

[0068] Next, the second dielectric layer 209 is etched using the second opening 213 as a mask to form a first groove in the second dielectric layer, wherein the first groove exposes a portion of the surface of the first stop layer. For the formation process of the first groove, please refer to Figure 6 and Figure 7 .

[0069] Please refer to Figure 6 , using the second opening 213 as a mask to etch the underlying structure, to form a third opening 214 in the underlying structure.

[0070] During the process of forming the third opening 214 , the photoresist layer 212 is naturally consumed.

[0071] Please refer to Figure 7 The second dielectric layer 209 is etched using the third opening 214 as a mask to form a first groove 215 in the second dielectric layer 209 . The first groove 215 exposes a portion of the surface of the first stop layer 207 .

[0072] In this embodiment, the etching rate of the second dielectric layer 209 in the process of etching the second dielectric layer 209 using the third opening 214 as a mask is greater than the etching rate of the underlying structure. Therefore, the process of etching the second dielectric layer 209 has a large etching selectivity ratio between the second dielectric layer 209 and the underlying structure. In the case of a first groove 215 with a large depth-width ratio at an advanced technology node, the underlying structure is consumed slowly and plays a good masking role, so that a first groove 215 with a good morphology and a large depth-width ratio can be formed.

[0073] In this embodiment, the process of etching the second dielectric layer 209 using the third opening 214 as a mask includes a dry etching process; parameters of the dry etching process include: etching gas includes fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

[0074] Please refer to Figure 8 , using the first groove 215 and the first stop layer 207 as masks, the first dielectric layer 204 is etched to form a second groove 216 in the first dielectric layer 204, the second groove 216 is connected to the first groove 215, the second groove 216 exposes the substrate surface, and the projection range of the second groove 216 on the substrate is within the projection range of the first groove 215 on the substrate.

[0075] The etching rate of the first stop layer 207 in the process of etching the first dielectric layer 204 using the first groove 215 and the first stop layer 207 as a mask is lower than the etching rate of the first dielectric layer 204. Therefore, the process of etching the first dielectric layer 204 has a large etching selectivity ratio between the first stop layer 207 and the first dielectric layer 204, so that the first dielectric layer 204 can be etched continuously using the first stop layer 207 and the first groove 215 as a mask, so that the projection range of the formed second groove 216 on the substrate is located within the projection range of the first groove 215 on the substrate, so as to meet the device requirements.

[0076] In this embodiment, the process of etching the first dielectric layer 204 using the first groove 215 and the first stop layer 207 as a mask includes a dry etching process; parameters of the dry etching process include: the etching gas includes a fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

[0077] In this embodiment, the second groove 216 exposes the surface of the conductive layer 202 .

[0078] In this embodiment, the process of etching the second dielectric layer 209 using the second opening 213 as a mask is the same as the process of etching the first dielectric layer 204 using the first groove 215 and the first stop layer 207 as a mask. Thus, the first groove 215 and the second groove 216 connected to each other can be formed by one process, which meets the device requirements, simplifies the process flow, and reduces process damage.

[0079] Please refer to Fig. 9 A metal structure 217 is formed in the first groove 215 and the second groove 216 .

[0080] The metal structure 217 is electrically connected to the conductive layer 202 .

[0081] The material of the metal structure 217 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0082] In this embodiment, the material of the metal structure 217 includes copper.

[0083] The method for forming the metal structure 217 includes: forming a metal material layer (not shown) in the core of the first groove 215 and the second groove 216 ; planarizing the metal material layer until the surface of the second dielectric layer 209 is exposed, and forming the metal structure 217 in the first groove 215 and the second groove 216 .

[0084] In this embodiment, the process of forming the metal material layer includes an electroplating process.

[0085] During the formation of the semiconductor structure, a first stop layer 207 is first formed on the first dielectric layer 204, wherein the first stop layer 207 has a first opening, and then a second dielectric layer 209 is formed on the first dielectric layer 204 and the first stop layer 207. Under the blocking effect of the first stop layer 207, when the second dielectric layer 209 is etched with the mask structure as a mask to form the first groove 215, the etching will not be directly etched to the first dielectric layer 204. Subsequently, the first dielectric layer 204 can be etched with the first groove and the first stop layer 207 as masks to form a second groove 216 connected to the first groove 215, so that the projection range of the formed second groove 216 on the substrate is located within the projection range of the first groove 215 on the substrate. The method can form the connected first groove 215 and the second groove 216 in one process flow, the process flow is simple, and the process damage is reduced, so that the metal structure 217 can be filled into the first groove 215 and the second groove 216 at one time, and the formed ultra-thick metal structure 217 has a more compact structure and a smaller resistance, thereby improving the performance of the semiconductor structure.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate; forming a first stop layer on the first dielectric layer, wherein the first stop layer has a first opening, and the first opening exposes a portion of the surface of the first dielectric layer; forming a second dielectric layer on the first dielectric layer and on the first stop layer; forming a mask structure on the second dielectric layer, wherein the mask structure has a second opening, and a projection range of the first opening on the substrate is located within a projection range of the second opening on the substrate; Using the second opening as a mask, etching the second dielectric layer to form a first groove in the second dielectric layer, wherein the first groove exposes a portion of the surface of the first stop layer; The first dielectric layer is etched using the first groove and the first stop layer as masks to form a second groove in the first dielectric layer, wherein the second groove is connected to the first groove, the second groove exposes the substrate surface, and the projection range of the second groove on the substrate is within the projection range of the first groove on the substrate; A metal structure is formed in the first recess and in the second recess.

2. The method for forming a semiconductor structure according to claim 1, wherein: The mask structure includes: an underlying structure and a photoresist layer located on the underlying structure, the second opening is located in the photoresist layer, and the second opening exposes a portion of the surface of the underlying structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The bottom layer structure includes a liner layer and an anti-reflection layer located on the liner layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the liner layer includes amorphous carbon; the material of the anti-reflection layer includes a dielectric anti-reflection layer.

5. The method for forming a semiconductor structure according to claim 2, wherein: The material of the underlying structure includes metal oxide or metal nitride; the metal oxide includes aluminum oxide or titanium oxide; the metal nitride includes titanium nitride.

6. The method for forming a semiconductor structure according to claim 2, wherein: The material of the underlying structure includes an inorganic non-metal material; the inorganic non-metal material includes silicon nitride.

7. The method for forming a semiconductor structure according to claim 2, wherein: In the process of etching the second dielectric layer using the second opening as a mask, the etching rate of the second dielectric layer is greater than the etching rate of the underlying structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of etching the second dielectric layer using the second opening as a mask includes a dry etching process; parameters of the dry etching process include: etching gas includes fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

9. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

10. The method for forming a semiconductor structure according to claim 1, wherein: In the process of etching the first dielectric layer using the first groove and the first stop layer as a mask, the etching rate of the first stop layer is lower than the etching rate of the first dielectric layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of etching the first dielectric layer using the first groove and the first stop layer as a mask includes a dry etching process; parameters of the dry etching process include: etching gas includes fluorine-containing gas, and the fluorine-containing gas includes carbon tetrafluoride.

12. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first stop layer includes nitrogen-doped silicon carbide, oxygen-doped silicon carbide or silicon nitride.

13. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first dielectric layer includes a dielectric material, and the dielectric material includes silicon oxide.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the second dielectric layer by using the second opening as a mask is the same as the process of etching the first dielectric layer by using the first groove and the first stop layer as a mask.

15. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first dielectric layer on the substrate, the method further includes: forming a second stop layer on the substrate.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the second stop layer includes nitrogen-doped silicon carbide, oxygen-doped silicon carbide or silicon nitride.

17. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes: a base; a device layer located on the base, the device layer includes an isolation structure and a device structure located in the isolation structure, the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure; a third dielectric layer located on the device layer; and a conductive layer located in the third dielectric layer, the conductive layer being electrically connected to the device structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The second groove exposes the surface of the conductive layer; and the metal structure is electrically connected to the conductive layer.

19. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the first stop layer includes: forming a stop material layer on the first dielectric layer; forming a patterned mask layer on the stop material layer, wherein the patterned mask layer exposes a portion of the stop material layer surface on the conductive layer; etching the stop material layer using the patterned mask layer as a mask until the surface of the first dielectric layer is exposed, thereby forming the first stop layer and a first opening located in the first stop layer.

20. The method for forming a semiconductor structure according to claim 1, wherein: The material of the metal structure includes copper.

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