Charge pump circuit and high-side switching circuit

Abstract

The embodiment of the invention provides a charge pump circuit and a high-side switch circuit. Wherein the first end of the charge pump circuit is connected with the gate end of the switch transistor, the second end of the charge pump circuit and the second end of the switch transistor are both connected with the input end of the load circuit, and the first end of the switch transistor is connected with a first power supply; the voltage of the grid end of the switching transistor is grid voltage, the voltage of the input end of the load circuit is load voltage, and the charge pump circuit is used for adjusting the grid voltage according to load voltage feedback, so that the difference value between the load voltage and the grid voltage is preset voltage, and the switching transistor is switched on. Therefore, the switching transistor can adopt an NMOS tube with smaller volume and stable switching resistance as a high-side switch, the area of a high-side switching circuit is reduced, and the switching resistance is stable.

Description

Technical Field

[0001] The present disclosure relates to the technical field of switching power supplies, and relates to but is not limited to a charge pump circuit and a high-side switch circuit. Background Art

[0002] Metal Oxide Semiconductor (MOS) high-side switches are currently widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy driving, high reliability, and near-ideal switching characteristics.

[0003] In the related art, P-type MOS tubes (PMOS tubes) are usually used as high-side switches. However, PMOS tubes have two disadvantages as high-side switches: first, the carrier mobility of PMOS tubes is low, and more area is needed to achieve the same on-resistance requirement; second, when PMOS tubes are used as high-side switches, the gate-source voltage is greatly affected by power supply fluctuations, making the on-resistance of the high-side switch unstable. Summary of the invention

[0004] Embodiments of the present disclosure provide a charge pump circuit and a high-side switch circuit.

[0005] In a first aspect, an embodiment of the present disclosure provides a charge pump circuit, wherein a first end of the charge pump circuit is connected to a gate end of a switching transistor, a second end of the charge pump circuit and a second end of the switching transistor are both connected to an input end of a load circuit, and a first end of the switching transistor is connected to a first power supply; a voltage at the gate end of the switching transistor is a gate voltage, and a voltage at the input end of the load circuit is a load voltage, wherein:

[0006] The charge pump circuit is used to adjust the gate voltage according to the load voltage feedback so that the difference between the load voltage and the gate voltage is a preset voltage to turn on the switch transistor.

[0007] In some embodiments, the charge pump circuit includes a first capacitor and a second capacitor;

[0008] The first plate of the first capacitor is coupled to the second power supply, the second plate of the first capacitor is coupled to the gate terminal of the switching transistor, the first plate of the second capacitor is coupled to the third power supply, and the second plate of the second capacitor is coupled to the input terminal of the load circuit; and\or,

[0009] The first plate of the first capacitor is coupled to a fourth power source, the second plate of the first capacitor is coupled to an input terminal of the load circuit, the first plate of the second capacitor is coupled to a fifth power source, and the second plate of the second capacitor is coupled to a gate terminal of the switch transistor;

[0010] The voltage of the second power supply is greater than the voltage of the fourth power supply, and the voltage of the fifth power supply is greater than the voltage of the third power supply.

[0011] In some embodiments, the voltage difference between the second power supply and the fourth power supply is greater than or equal to the preset voltage;

[0012] A voltage difference between the fifth power source and the third power source is greater than or equal to the preset voltage;

[0013] The voltages of the second power supply and the fifth power supply are the same or different; the voltages of the third power supply and the fourth power supply are the same or different.

[0014] In some embodiments, the charge pump circuit further includes: a first switch circuit and a second switch circuit;

[0015] A first terminal of the first switch circuit is connected to the second plate of the first capacitor, a second terminal of the first switch circuit is connected to the second plate of the second capacitor, and a third terminal of the first switch circuit is coupled to the gate terminal of the switch transistor;

[0016] A first end of the second switch circuit is connected to the second plate of the first capacitor, a second end of the second switch circuit is connected to the second plate of the second capacitor, and a third end of the second switch circuit is coupled to the input end of the load circuit;

[0017] The first switch circuit is used to connect the second plate of the first capacitor or the second plate of the second capacitor to the gate terminal of the switch transistor when in operation;

[0018] The second switch circuit is used to connect the second plate of the first capacitor or the second plate of the second capacitor to the input end of the load circuit during initialization.

[0019] In some embodiments, the charge pump circuit further includes: a third switch circuit and a fourth switch circuit;

[0020] A first end of the third switch circuit is connected to the first plate of the first capacitor, a second end of the third switch circuit is connected to the second power supply, and a third end of the third switch circuit is connected to the fourth power supply;

[0021] The first end of the fourth switch circuit is connected to the first plate of the second capacitor, the second end of the fourth switch circuit is connected to the fifth power supply, and the third end of the fourth switch circuit is connected to the third power supply;

[0022] The third switch circuit is used to connect the fourth power supply to the first plate of the first capacitor when the first capacitor is initialized, and to connect the second power supply to the first plate of the first capacitor when the first capacitor is working;

[0023] The fourth switch circuit is used to connect the third power supply to the first plate of the second capacitor when the second capacitor is initialized, and to connect the fifth power supply to the first plate of the second capacitor when the second capacitor is working.

[0024] In some embodiments, the third switch circuit includes a first transistor and a second transistor; the fourth switch circuit includes a third transistor and a fourth transistor;

[0025] The first ends of the first transistor and the second transistor are connected to the second power supply and the fourth power supply respectively; the second ends of the first transistor and the second transistor are connected to the first plate of the first capacitor; the first ends of the third transistor and the fourth transistor are connected to the fifth power supply and the third power supply respectively; the second ends of the third transistor and the fourth transistor are connected to the first plate of the second capacitor.

[0026] In some embodiments, the first switch circuit and the second switch circuit are both cross-coupled circuits, the first switch circuit includes a fifth transistor and a sixth transistor, and the second switch circuit includes a seventh transistor and an eighth transistor;

[0027] The first end of the fifth transistor and the first end of the sixth transistor are both coupled to the gate end of the switch transistor, the gate end of the fifth transistor and the second end of the sixth transistor are both connected to the second plate of the second capacitor, and the second end of the fifth transistor and the gate end of the sixth transistor are both connected to the second plate of the first capacitor;

[0028] The first end of the seventh transistor and the gate end of the eighth transistor are both connected to the second plate of the first capacitor, the gate end of the seventh transistor and the first end of the eighth transistor are both connected to the second plate of the second capacitor, and the second end of the seventh transistor and the second end of the eighth transistor are both coupled to the input end of the load circuit.

[0029] In some embodiments, the charge pump circuit further includes a first resistor, a second resistor, and a third capacitor;

[0030] One end of the first resistor is connected to the gate terminal of the switch transistor, and the other end of the first resistor is connected to the first end of the fifth transistor and the first end of the sixth transistor;

[0031] One end of the second resistor is connected to the second end of the seventh transistor and the second end of the eighth transistor, and the other end of the second resistor is connected to the input end of the load circuit;

[0032] One section of the third capacitor is connected to the second end of the seventh transistor, the second end of the eighth transistor and one end of the second resistor, and the other end of the third capacitor is connected to the ground.

[0033] In some embodiments, the charge pump circuit further includes a fourth capacitor and a fifth capacitor;

[0034] The fourth capacitor is connected between the first terminal of the switch transistor and the gate terminal of the switch transistor;

[0035] The fifth capacitor is connected between the second terminal of the switch transistor and the gate terminal of the switch transistor; wherein:

[0036] The fourth capacitor includes a parasitic capacitor or a metal plate capacitor; the fifth capacitor includes a parasitic capacitor or a metal plate capacitor.

[0037] In some embodiments, the switch transistor, the second transistor, the fourth transistor, the seventh transistor and the eighth transistor are NMOS transistors;

[0038] The first transistor, the third transistor, the fifth transistor, and the sixth transistor are PMOS transistors.

[0039] In a second aspect, an embodiment of the present disclosure provides a high-side switch circuit, comprising a charge pump circuit as described in any one of the above embodiments.

[0040] The embodiment of the present disclosure provides a charge pump circuit and a high-side switch circuit, wherein the first end of the charge pump circuit is connected to the gate end of the switch transistor, the second end of the charge pump circuit and the second end of the switch transistor are both connected to the input end of the load circuit, and the first end of the switch transistor is connected to the first power supply; the voltage of the gate end of the switch transistor is the gate voltage, and the voltage of the input end of the load circuit is the load voltage, wherein: the charge pump circuit is used to adjust the gate voltage according to the load voltage feedback, so that the difference between the load voltage and the gate voltage is a preset voltage to turn on the switch transistor. Since the charge pump circuit is connected to the gate end and the second end of the switch transistor, the difference between the voltage of the gate end and the second end of the switch transistor can be controlled by the charge pump circuit to be greater than or equal to the preset voltage, so that the switch transistor can use a small NMOS tube with stable switch resistance as a high-side switch, so that not only the area of ​​the high-side switch circuit can be reduced, but also the switch resistance can be stabilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 1 ;

[0042] Figure 2 A schematic diagram of the voltage waveform of the VCC port under the ET mode and APT provided in the embodiment of the present disclosure;

[0043] Figure 3 A schematic diagram of the structure of a load circuit provided in an embodiment of the present disclosure;

[0044] Figure 4 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 2 ;

[0045] Figure 5 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 3 ;

[0046] Figure 6 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 1

[0047] Figure 7 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 2 ;

[0048] Figure 8 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 3 ;

[0049] Fig. 9 A schematic diagram of the structure of a switch locking circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0054] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0056] At present, MOS high-side switches are widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy drive, high reliability, and near-ideal switching characteristics, and cover the control and protection of currents within tens of amperes. However, for high-frequency application environments (GHz level), due to parasitic resistance and capacitance and coupling crosstalk, the control and protection of high-side switches are complex, and the industry generally uses PMOS tubes (i.e. MPS) as high-side switch devices.

[0057] Furthermore, when the PMOS tube is used as a high-side switch device, it is relatively easy to control the gate terminal voltage to turn the PMOS tube on or off. However, there are two disadvantages of using the PMOS tube as a high-side switch device: first, the carrier mobility of the PMOS tube is low, and more area is required to achieve the same on-resistance requirement; second, the gate-source voltage of the PMOS tube used as a high-side switch device is greatly affected by power supply fluctuations, so the on-resistance of the switch is unstable. In the related art, N-type MOS tubes (NMOS tubes) are usually not used as high-side switch devices. This is because when the N-type MOS tube is used for high-side switching, there will be two problems due to the source being connected to the load: the source is suspended and the gate voltage is higher than the drain supply voltage.

[0058] Based on this, the embodiment of the present disclosure provides a charge pump circuit and a high-side switch circuit, wherein the first end of the charge pump circuit is connected to the gate end of the switch transistor, the second end of the charge pump circuit and the second end of the switch transistor are both connected to the input end of the load circuit, and the first end of the switch transistor is connected to the first power supply; the voltage of the gate end of the switch transistor is the gate voltage, and the voltage of the input end of the load circuit is the load voltage, wherein: the charge pump circuit is used to adjust the gate voltage according to the load voltage feedback, so that the difference between the load voltage and the gate voltage is a preset voltage to turn on the switch transistor. Since the charge pump circuit is connected to the gate end and the second end of the switch transistor, the difference between the voltage of the gate end and the second end of the switch transistor can be controlled by the charge pump circuit to be greater than or equal to the preset voltage, so that the switch transistor can use a small NMOS tube with stable switch resistance as a high-side switch, so that not only the area of ​​the high-side switch circuit can be reduced, but also the switch resistance can be stabilized.

[0059] The charge pump circuit and the high-side switch circuit in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0060] Figure 1A charge pump circuit 200 is provided in an embodiment of the present disclosure, wherein a first end of the charge pump circuit 200 is connected to a gate end of a switching transistor 120, a second end of the charge pump circuit 200 and a second end of the switching transistor 120 are both connected to an input end of a load circuit 140, and a first end of the switching transistor 120 is connected to a first power supply 110; a voltage at a gate end of the switching transistor 120 is a gate voltage, and a voltage at an input end of the load circuit 140 is a load voltage, wherein: the charge pump circuit 200 is used to adjust the gate voltage according to load voltage feedback so that the difference between the load voltage and the gate voltage is a preset voltage to turn on the switching transistor 120.

[0061] Here, the first power supply 110 is used to output a first voltage, and the first voltage can be a voltage that supplies power to the load circuit 140. The first voltage can be VCC_PS1 ( Figure 1 In other embodiments, the first voltage may also be other voltages.

[0062] It should be noted that the first voltage can be a fixed voltage or a variable voltage. The first power supply 110 supplies power and operates in either of two modes: an envelope tracking mode (ET mode) and an average power tracking mode (APT mode). The voltage waveform diagram of the first voltage in the ET mode and the APT mode is shown in FIG. Figure 2 shown.

[0063] In addition, the structural diagram of the load circuit 140 is as follows Figure 3 As shown, the load circuit 140 may include a power amplifier 141 (Power Amplifier, PA). The first end of the power amplifier 141 is connected to the second end of the switch transistor 120 through the port 142; the second end of the power amplifier 141 is grounded; the input end of the power amplifier 141 is used to receive the RF input signal RF_in; the output end of the power amplifier 141 is used to output the RF output signal RF_out. It should be noted that Figure 3 The load circuit 140 in FIG. 1 is a simplified structural diagram. In fact, the load circuit 140 can be any achievable circuit structure.

[0064] In some embodiments, the switch transistor 120 is an NMOS transistor, and the switch transistor 120 may also be other N-type field effect transistors, which are not limited here. The charge pump circuit 200 may be a QPUMP (gate drive charge pump).

[0065] In the embodiment of the present disclosure, the charge pump circuit 200 obtains the load voltage, and after raising the load voltage by at least a preset voltage, outputs it to the gate terminal of the switching transistor 120; so that the difference between the voltage at the gate terminal of the switching transistor 120 and the voltage at the second terminal of the switching transistor 120 (i.e., the load voltage) is greater than or equal to the turn-on voltage of the first transistor, where the preset voltage can be 5V.

[0066] In the embodiment of the present disclosure, since the charge pump circuit is connected to the gate terminal and the second terminal of the switching transistor, the difference between the voltages at the gate terminal and the second terminal of the switching transistor can be controlled by the charge pump circuit to be greater than or equal to a preset voltage, thereby enabling the switching transistor to adopt a small NMOS tube with stable switch resistance as a high-side switch. In this way, not only the area of ​​the high-side switching circuit can be reduced, but also the switch resistance can be stabilized.

[0067] Next, please refer to Figure 4 and Figure 5 , the charge pump circuit 200 provided in the embodiment of the present disclosure is further described.

[0068] In some embodiments, please refer to Figure 4 , the charge pump circuit 200 may include a first capacitor 210 and a second capacitor 220. The first plate of the first capacitor 210 is coupled to the second power supply 230, the second plate of the first capacitor 210 is coupled to the gate terminal of the switch transistor 120, the first plate of the second capacitor 220 is coupled to the third power supply 240, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit (i.e., port 142). In addition, the first plate of the first capacitor 210 is coupled to the fourth power supply 250, the second plate of the first capacitor 210 is coupled to the input terminal of the load circuit 140, the first plate of the second capacitor 220 is coupled to the fifth power supply 260, and the second plate of the second capacitor 220 is coupled to the gate terminal of the switch transistor 120. The voltage of the second power supply 230 is greater than the voltage of the fourth power supply 250, and the voltage of the fifth power supply 260 is greater than the voltage of the third power supply 240.

[0069] It should be noted that the voltage output by the second power supply 230 and / or the voltage output by the fifth power supply 260 may be the voltage output by the first charge pump circuit 131 in the subsequent high-side switch circuit 100 .

[0070] It should also be noted that the first plate of the first capacitor 210 is coupled to the second power source 230: it means that the first plate of the first capacitor 210 and the second power source 230 can be directly connected or indirectly connected, that is, "coupling" includes direct connection or indirect connection. The "coupling" that appears in the subsequent description can be understood with reference to the above explanation.

[0071] Next, the operating principle of the charge pump circuit is explained.

[0072] The charge pump circuit can turn on the switch transistor 120 through the first capacitor 210 and the second capacitor 220 .

[0073] When the switch transistor 120 is turned on by the first capacitor 210, please continue to refer to Figure 4 , the first capacitor 210 is used to charge the second plate of the first capacitor 210 to the load voltage, and then boost the second plate of the first capacitor to a preset voltage through the second power supply 230 to obtain a gate voltage, and apply the gate voltage to the gate terminal of the switching transistor. Specifically, when the first capacitor 210 is initialized, the first plate of the first capacitor 210 is coupled to the fourth power supply 250 so that the first plate voltage is the fourth voltage, and the second plate of the first capacitor 210 is coupled to the load circuit so that the second plate is the load voltage; when the first capacitor 210 is working, the first plate of the first capacitor 210 is coupled to the second power supply 230 so that the first plate voltage changes from the fourth voltage to the second voltage, and the second plate of the first capacitor 210 is coupled to the gate terminal of the switching transistor 120 so that the second plate voltage changes from the load voltage to the gate voltage. At this time, since the voltage difference of the two plates changes in the same way, both are the difference between the second voltage and the fourth voltage, that is, the preset voltage, the voltage difference between the gate voltage and the load voltage is maintained at the preset voltage.

[0074] When the switch transistor 120 is turned on by the second capacitor 220, please continue to refer to Figure 4 , the second capacitor 220 is used to charge the second plate of the second capacitor 220 to the load voltage, and then boost the second plate of the second capacitor 220 to a preset voltage through the fifth power supply 260 to obtain a gate voltage, and apply the gate voltage to the gate terminal of the switching transistor 120. Specifically, when the second capacitor 220 is initialized, the first plate of the second capacitor 220 is coupled to the third power supply 240 so that the first plate voltage is the third voltage, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit so that the second plate is the load voltage; when the second capacitor 220 is working, the first plate of the second capacitor 220 is coupled to the fifth power supply 260 so that the first plate voltage changes from the third voltage to the fifth voltage, and the second plate of the second capacitor 220 is coupled to the gate terminal of the switching transistor 120 so that the second plate voltage changes from the load voltage to the gate voltage. At this time, since the voltage difference of the two plates changes in the same way, both are the difference between the fifth voltage and the third voltage, that is, the preset voltage, the voltage difference between the gate voltage and the load voltage is maintained at the preset voltage.

[0075] The first boost capacitor and the second capacitor can work alternately. Specifically, when the first capacitor 210 is in the initial state, the second capacitor 220 is in the working state; when the first capacitor 210 is in the working state, the second capacitor 220 is in the initial state. In this way, not only the voltage difference between the gate terminal and the second terminal of the switching transistor 120 is relatively stable, but also the charge pump circuit 200 can be prevented from overheating and affecting the circuit performance.

[0076] The charge pump circuit can adjust the gate voltage according to the load voltage feedback through the first capacitor 210 and the second capacitor 220, so that the difference between the load voltage and the gate voltage remains greater than or equal to the turn-on voltage of the switching transistor, thereby keeping the switching transistor 120 turned on.

[0077] It should be noted that, in the embodiment of the present disclosure, only the first capacitor 210 and its corresponding connection circuit, or the second capacitor 220 and its corresponding connection circuit can be set; thus, the difference between the load voltage and the gate voltage can be adjusted only by the first capacitor 210 or the second capacitor 220, thereby reducing the area of ​​the charge pump circuit 200. For example, when only the first capacitor 210 and its corresponding connection circuit are set, the first plate of the first capacitor 210 is coupled to the second power supply 230 and the fourth power supply 250, and the second plate of the first capacitor 210 is coupled to the gate terminal of the switching transistor 120 and the input terminal of the load circuit (i.e., port 142). For another example, when only the second capacitor 220 and its corresponding connection circuit are set, the first plate of the second capacitor 220 is coupled to the third power supply 240 and the fifth power supply 260, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit and the gate terminal of the switching transistor 120.

[0078] It should also be noted that Figure 4 and Figure 5 The first power supply and the load circuit are not shown in FIG. For the connection relationship between the first power supply and the load circuit, please refer to Figure 1 To understand.

[0079] In some embodiments, the voltages of the second power source 230 and the fifth power source 260 are the same or different; the voltages of the third power source 240 and the fourth power source 250 are the same or different. Furthermore, the difference between the second voltage and the fourth voltage, and the difference between the fifth voltage and the third voltage, can be the same or different.

[0080] For example, the voltages of the second voltage and the fifth voltage may both be 5V, and the voltages of the fourth voltage and the third voltage may both be ground voltage, i.e., 0V. For another example, the voltage of the second voltage is 5V, and the voltage of the fourth voltage is 0V; the voltage of the fifth voltage is 8V, and the voltage of the third voltage is 2V. In this way, the preset voltage for turning on the switch transistor of the first capacitor 210 is 5V, and the preset voltage for turning on the switch transistor of the second capacitor 220 is 6V. In addition, when the voltage difference between the second voltage and the fourth voltage is equal to the voltage difference between the fifth voltage and the third voltage, the voltage difference between the gate terminal and the second terminal of the switch transistor 120 is relatively stable.

[0081] In some embodiments, please refer to Figure 4 The charge pump circuit 200 also includes: a first switch circuit 271 and a second switch circuit 272; a first end of the first switch circuit 271 is connected to the second plate of the first capacitor 210, a second end of the first switch circuit 271 is connected to the second plate of the second capacitor 220, and a third end of the first switch circuit 271 is coupled to the gate terminal of the switching transistor 120; a first end of the second switch circuit 272 is connected to the second plate of the first capacitor 210, a second end of the second switch circuit 272 is connected to the second plate of the second capacitor 220, and a third end of the second switch circuit 272 is coupled to the input end of the load circuit.

[0082] In some embodiments, the second switching circuit 272 is used to connect the second plate of the first capacitor 210 or the second plate of the second capacitor 220 to the input end of the load circuit during initialization; the first switching circuit 271 is used to connect the second plate of the first capacitor 210 or the second plate of the second capacitor 220 to the gate end of the switching transistor 120 during operation.

[0083] In some embodiments, please refer to Figure 4 The charge pump circuit 200 also includes: a third switch circuit 273 and a fourth switch circuit 274; a first end of the third switch circuit 273 is connected to the first plate of the first capacitor 210, a second end of the third switch circuit 273 is connected to the second power supply 230, and a third end of the third switch circuit 273 is connected to the fourth power supply 250; a first end of the fourth switch circuit 274 is connected to the first plate of the second capacitor 220, a second end of the fourth switch circuit 274 is connected to the fifth power supply 260, and a third end of the fourth switch circuit 274 is connected to the third power supply 240.

[0084] In some embodiments, the third switching circuit 273 is used to connect the fourth power supply 250 to the first plate of the first capacitor 210 when the first capacitor 210 is initialized; and is also used to connect the second power supply 230 to the first plate of the first capacitor 210 when the first capacitor 210 is in a working state; the fourth switching circuit 274 is used to connect the third power supply 240 to the first plate of the second capacitor when the second capacitor 220 is initialized; and is also used to connect the fifth power supply 260 to the first plate of the second capacitor 220 when the second capacitor 220 is in a working state.

[0085] It should be noted that when the voltage pump circuit has only one capacitor, the related structure of the other capacitor in the above embodiment is omitted and will not be described in detail here.

[0086] In some embodiments, please refer to Figure 5 The third switch circuit 273 includes a first transistor MP1 and a second transistor MN1; the fourth switch circuit 274 includes a third transistor MP2 and a fourth transistor MN2. The first ends of the first transistor MP1 and the second transistor MN1 are connected to the second power supply 230 and the fourth power supply 250 respectively; the second ends of the first transistor MP1 and the second transistor MN1 are connected to the first plate of the first capacitor 210; the first ends of the third transistor MP2 and the fourth transistor MN2 are connected to the fifth power supply 260 and the third power supply 240 respectively; the second ends of the third transistor MP2 and the fourth transistor MN2 are connected to the first plate of the second capacitor 220.

[0087] The gate terminals of the transistors in the third switch circuit 273 and the fourth switch circuit 274 are connected to the control circuit. The third switch circuit 273 obtains the first clock signal and the second clock signal, and the fourth switch circuit 274 obtains the third clock signal and the fourth clock signal. When the first capacitor 210 and the second capacitor 220 are initialized, the four clock signals are all in the first level state; when in the working state, the four clock signals are all in the second level state. Figure 5 , the first clock signal can be represented by CLK_P1, the second clock signal can be represented by CLK_N1, the third clock signal can be represented by CLK_P2, and the fourth clock signal can be represented by CLK_N2.

[0088] It should be noted that the first level state is 1 (logical high level) and the second level state is 0 (logical low level). The “first level state” and “second level state” that appear in the subsequent specifications can be understood with reference to the above explanation.

[0089] In some embodiments, please refer to Figure 5, the first switch circuit 271 and the second switch circuit 272 are both cross-coupled circuits, the first switch circuit 271 includes a fifth transistor MP3 and a sixth transistor MP4, and the second switch circuit 272 includes a seventh transistor MN3 and an eighth transistor MN4. The first end of the fifth transistor MP3 and the first end of the sixth transistor MP4 are both coupled to the gate end of the switch transistor 120, the gate end of the fifth transistor MP3 and the second end of the sixth transistor MP4 are both connected to the second plate of the second capacitor 220, and the second end of the fifth transistor MP3 and the gate end of the sixth transistor MP4 are both connected to the second plate of the first capacitor 210; the first end of the seventh transistor MN3 and the gate end of the eighth transistor MN4 are both connected to the second plate of the first capacitor 210, the gate end of the seventh transistor MN3 and the first end of the eighth transistor MN4 are both connected to the second plate of the second capacitor 220, and the second end of the seventh transistor MN3 and the second end of the eighth transistor MN4 are both coupled to the input end of the load circuit.

[0090] In some embodiments, please refer to Figure 5 The charge pump circuit 200 also includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the gate terminal of the switching transistor 120, and the other end of the first resistor R1 is connected to the first end of the fifth transistor MP3 and the first end of the sixth transistor MP4; one end of the second resistor R2 is connected to the second end of the seventh transistor MN3 and the second end of the eighth transistor MN4, and the other end of the second resistor R2 is connected to the input end of the load circuit.

[0091] In this disclosure, please continue to refer to Figure 5 The charge pump circuit 200 further includes a third capacitor C3; one end of the third capacitor C3 is connected to the second end of the seventh transistor MN3, the second end of the eighth transistor MN4 and one end of the second resistor R2, and the other end of the third capacitor C3 is connected to the ground.

[0092] In the disclosed embodiment, the first resistor R1, the second resistor R2 and the third capacitor C3 are used for filtering, so that the output signal of the charge pump circuit 200 is more stable.

[0093] In some embodiments, the second transistor MN1, the fourth transistor MN2, the seventh transistor MN3 and the eighth transistor MN4 are NMOS transistors; the first transistor MP1, the third transistor MP2, the fifth transistor MP3 and the sixth transistor MP4 are PMOS transistors.

[0094] Next, take the example that the voltages of the second power supply 230 and the fifth power supply 260 are both set to 5V, and the voltages of the fourth power supply 250 and the third power supply 240 are both set to 0V, and Figure 5The circuit shown provides a detailed description of the operation of the charge pump circuit 200 .

[0095] like Figure 5 In the solid arc path, within half a clock cycle, the first transistor MP1, the first capacitor 210 and the fifth transistor MP3 form a path, and the fourth transistor MN2, the second capacitor 220 and the eighth transistor MN4 form a path. Figure 5 In the dotted arc path, in the other half cycle, the second transistor MN1, the first capacitor 210 and the seventh transistor MN3 form a path, and the third transistor MP2, the second capacitor 220 and the sixth transistor MP4 form a path; in this way, the voltage difference between the gate-source voltage of the switching transistor 120 is stabilized at 5V, thereby realizing the high-side turning on of the switching transistor 120.

[0096] In other embodiments, the second power supply 230 and the fifth power supply 260 can be set to other voltages, for example, 6V, 4V, etc.; the fourth power supply 250 and the third power supply 240 can also be set to other voltages, for example, 1V, 1.5V, 2V, etc.

[0097] In some embodiments, please refer to Figure 5 The charge pump circuit 200 also includes a fourth capacitor 281 and a fifth capacitor 282; the fourth capacitor 281 is connected between the first end of the switching transistor 120 and the gate end of the switching transistor 120; the fifth capacitor 282 is connected between the second end of the switching transistor 120 and the gate end of the switching transistor 120; wherein: the fourth capacitor 281 includes a parasitic capacitor or a metal plate capacitor; the fifth capacitor 282 includes a parasitic capacitor or a metal plate capacitor.

[0098] In this way, the coupling characteristics of the fourth capacitor 281 and the fifth capacitor 282 can be used to realize the ET / APT dual-mode automatic switching and the wide-band ET mode operation. Figure 1 ) is a changing value, since the switching transistor 120 is not an ideal switch, the parasitic capacitance (the fourth capacitor 281 and the fifth capacitor 282) can be used to make the load voltage change better with the first power supply 110; when the capacity of the parasitic capacitance (the fourth capacitor 281 and the fifth capacitor 282) is not large enough, it can also be achieved by adding additional capacitance, that is, setting the fourth capacitor 281 and / or the fifth capacitor 282 as a metal plate capacitor.

[0099] In order to improve the working efficiency of the chip, the width-to-length ratio of the switching transistor 120 is relatively large, so that the drain-source voltage of the switching transistor 120 is basically equal. In the APT mode, the voltage of the first power supply 110 is basically maintained stable. In the ET mode, in order to improve the working efficiency of the load circuit, the voltage of the first power supply 110 changes within a certain frequency and amplitude range. Under the action of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the switching transistor 120 (i.e., the fourth capacitor 281 and the fifth capacitor 282), the gate-source voltage difference of the switching transistor 120 always remains stable, and the final load voltage changes synchronously with the voltage of the first power supply 110, and no additional distortion is introduced to the load circuit.

[0100] The embodiment of the present disclosure also provides a high-side switch circuit 100, including a charge pump circuit 200 as any one of the above embodiments. Below, the high-side switch circuit in the embodiment of the present disclosure is described in detail in conjunction with the accompanying drawings. It should be noted that the switch transistor 120 can be the first switch transistor 121 in the following embodiments, or the second switch transistor 160; the charge pump circuit 200 can be the second charge pump circuit 132, or the third charge pump circuit 133.

[0101] Figure 6 A schematic diagram of the structure of a high-side switch circuit 100 provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the high-side switch circuit 100 includes: a first power supply 110, a first switch transistor 121 and a drive circuit 130, wherein the first end of the first switch transistor 121 is connected to the first power supply 110, the second end of the first switch transistor 121 is connected to the load circuit 140, and the gate end of the first switch transistor 121 is connected to the drive circuit 130; wherein: the first power supply 110 is used to provide a first voltage to the first switch transistor 121; the drive circuit 130 is used to receive a sixth voltage, and to raise the sixth voltage to obtain a bias voltage, and to turn on the first switch transistor 121 according to the bias voltage; wherein the raising process makes the difference between the voltage at the gate end of the first switch transistor 121 and the voltage at the second end of the first switch transistor 121 greater than a preset difference; when the first switch transistor 121 is turned on, the first switch transistor 121 transmits the first voltage to the load circuit 140. Here, the bias voltage is the gate voltage in the above embodiment.

[0102] In some embodiments, the first switch transistor 121 is an NMOS transistor. The first switch transistor 121 may also be other N-type field effect transistors, which is not limited here.

[0103] In some embodiments, the driving circuit 130 cannot stably drive the sixth voltage of the first switch transistor to be raised. Here, the sixth voltage may be, for example, 2.5V, and the preset difference may be, for example, 5V. In actual implementation, the preset difference may also be other values ​​that can realize the conduction of the first switch transistor 121, such as 6V, 6.5V, 7V, etc. Since the sixth voltage is raised by the driving circuit 130, the first switch transistor 121 in the high-side switch circuit 100 may adopt an NMOS tube (i.e., MNS), so as to realize the conduction of the first switch transistor 121 by setting the voltage of the gate terminal of the first switch transistor 121 to be greater than the voltage of the second terminal thereof.

[0104] In the embodiment of the present disclosure, since the driving circuit raises the received sixth voltage, the gate voltage of the first switching transistor is higher. In this way, the first switching transistor can adopt an NMOS tube with a smaller size and stable switch resistance as a high-side switch, which not only reduces the area of ​​the high-side switching circuit but also stabilizes the switch resistance.

[0105] Next, please refer to Figure 7 , the high-side switch circuit 100 provided in the embodiment of the present disclosure is further described.

[0106] In some embodiments, please refer to Figure 7 The high-side switch circuit 100 also includes a sixth power supply 151, and the drive circuit 130 includes: a first charge pump circuit 131 and a second charge pump circuit 132; the first end of the first charge pump circuit 131 is coupled to the sixth power supply 151, and the second end of the first charge pump circuit 131 is connected to the first end of the second charge pump circuit 132; the second end of the second charge pump circuit 132 is connected to the gate end of the first switching transistor 121; wherein: the sixth power supply 151 is used to provide a sixth voltage; the first charge pump circuit 131 is used to raise the sixth voltage to obtain a preset voltage; the second charge pump circuit 132 is used to further raise the preset voltage to obtain a bias voltage.

[0107] In the embodiment of the present disclosure, the value of the sixth voltage output by the sixth power supply 151 is within a certain range, where the certain range may be 2.5V-3V, and the sixth voltage may be, for example, 2.5V, 2.6V, etc. In some embodiments, the sixth power supply 151 may be a voltage stabilizing circuit, wherein the voltage stabilizing circuit is used to convert the battery voltage VBAT to output the sixth voltage. In other embodiments, the voltage stabilizing circuit may also convert the voltage of other power supplies.

[0108] Here, the first charge pump circuit 131 may be a VX2 CP (twice charge pump), which is used to increase the sixth voltage by two times to obtain a preset voltage; for example, the sixth voltage is 3V, and the first charge pump circuit 131 increases the sixth voltage V2 of 3V by two times to output a preset voltage of 6V. The second charge pump circuit 132 may be a QPUMP (gate drive charge pump), which is used to further increase the preset voltage to obtain a bias voltage, for example, 8V. It should be noted that the first charge pump circuit 131 may also increase the sixth voltage V2 to other voltage values, for example, by 1.5 times.

[0109] It should also be noted that in Figure 7 In the embodiment, the first power supply supplies power to the first switch transistor 121 through the port 111, the load circuit is connected to the first switch transistor 121 through the port 142, and the sixth power supply 151 is connected to the battery voltage VBAT through the port 152. In addition, the high-side switch circuit 100 further includes a port GND connected to the ground terminal, and some components in the high-side switch circuit 100 are grounded through the port GND.

[0110] In the disclosed embodiment, since the driving circuit performs a lifting process on the received sixth voltage, the gate voltage of the first switch transistor 121 is stably increased, so that when the first switch transistor 121 is an NMOS transistor, the first switch transistor 121 can be turned on or off; in addition, since the NMOS transistor has a higher carrier mobility characteristic, the high-side switch circuit can have a stronger driving current capability, thereby improving the current density and efficiency.

[0111] In some embodiments, the third terminal of the second charge pump circuit 132 is connected to the second terminal of the first switch transistor 121, and the second charge pump circuit 132 is further used to receive the second terminal voltage of the first switch transistor 121, and raise the preset voltage according to the voltage of the second terminal of the first switch transistor 121 to obtain the bias voltage. In this way, the gate voltage of the first switch transistor 121 can be adjusted according to the voltage feedback of the input terminal of the load circuit, so that the difference between the gate voltage of the first switch transistor 121 and the second terminal voltage is greater than or equal to the preset difference, so as to turn on the first switch transistor 121; it should be noted that the preset voltage and the preset difference are equal in value.

[0112] Specifically, the second charge pump circuit 132 is used to increase the voltage of the second end of the first switching transistor 121 (i.e., the voltage output by the port 142) by a preset difference (i.e., the value of the preset voltage) to obtain a bias voltage, and apply the bias voltage to the gate end of the first switching transistor 121; for example, the voltage of the second end of the first switching transistor 121 is 3V, the second charge pump circuit 132 increases the voltage of 3V by 5V, and the obtained bias voltage is 8V, and the bias voltage of 8V is applied to the gate end of the first switching transistor 121.

[0113] In the disclosed embodiment, since the first switch transistor 121 includes an NMOS tube, the turn-on voltage of the NMOS is usually less than 5V under low voltage conditions, so the preset difference can be greater than 5V, such as 6V, 6.5V, 7V, etc. In other embodiments, it can also be set according to actual conditions, and when the sixth voltage V2 is small, more charge pump circuits can be set to increase the sixth voltage.

[0114] In the embodiment of the present disclosure, since a driving circuit (i.e., the second charge pump circuit 132) is connected to the gate terminal and the second terminal of the first switching transistor, the voltages at the gate terminal and the second terminal of the first switching transistor can be controlled by the driving circuit to turn on the first switching transistor.

[0115] In the embodiment of the present disclosure, when the high-side switch circuit 100 is turned off, the sixth power supply 151, the drive circuit 130 and other circuits are all turned off. When the high-side switch circuit 100 is turned on, the sixth power supply and the first charge pump circuit 131 in the drive circuit 130 are both kept turned on; at this time, when the high-side switch circuit 100 needs to be turned on, the second charge pump circuit 132 in the drive circuit 130 is turned on to drive the high-side switch circuit 100 to work.

[0116] In this way, the first switch transistor 121 can be turned on or off only by turning on or off the second charge pump circuit 132. That is to say, during the operation of the high-side switch circuit 100, the sixth power supply 151 and the first charge pump circuit 131 will not cause any delay, thereby improving the response speed of the high-side switch circuit 100.

[0117] In some embodiments, please refer to Figure 7 The high-side switch circuit 100 further includes a first body-end switch circuit 190, wherein a first terminal and a second terminal of the first body-end switch circuit 190 are respectively connected to a gate terminal and a second terminal of the first switch transistor 121, so as to ensure that the first switch transistor 121 is reliably turned on and off.

[0118] In some embodiments, please refer to Figure 8, the high-side switch circuit 100 further includes a second switch transistor 160; the first end of the second switch transistor 160 is used to connect to the seventh power supply (not shown) through the port 170, the second end of the second switch transistor 160 is connected to the load circuit (not shown) through the port 142, and the gate end of the second switch transistor 160 and the second end of the second switch transistor 160 are connected to the drive circuit 130. Wherein: the seventh power supply is used to provide the seventh voltage to the second switch transistor 160; the drive circuit 130 is also used to perform a lifting process on the sixth voltage, and after obtaining the bias voltage, control the second switch transistor 160 to turn on according to the bias voltage; wherein the lifting process also makes the difference between the voltage at the gate end of the second switch transistor 160 and the voltage at the second end of the second switch transistor 160 greater than the preset difference; when the second switch transistor 160 is turned on, the second switch transistor 160 transmits the seventh voltage to the load circuit.

[0119] It should be noted that the load circuit, the first power supply, the sixth power supply and the switch circuit can also be set on one IC, or part of them and the switch circuit can be set on one IC. In this case, no external interface is required for connection and they can be directly connected.

[0120] In the embodiment of the present disclosure, the seventh voltage can be represented by VCC_PS2. Please continue to refer to Figure 8 The seventh power supply supplies power to the load circuit through the port 170 when the second switch transistor 160 is turned on. The seventh voltage can be a fixed voltage or a variable voltage; the seventh power supply and the load circuit can be powered and operated in either of the ET and APT modes.

[0121] In some embodiments, the first power supply and the seventh power supply have different working modes. For example, the working mode of the first power supply is ET mode, and the working mode of the seventh power supply is APT mode; or, the working mode of the first power supply is APT mode, and the working mode of the seventh power supply is ET mode. In this way, the power supply mode of the load circuit can be switched by the first switch transistor 121 and the second switch transistor 160, thereby broadening the application scenario of the high-side switch circuit 100.

[0122] In some embodiments, the structure and function of the second switch transistor 160 are similar to those of the first switch transistor 121 , and are not described in detail herein.

[0123] In some embodiments, the driving circuit 130 also includes a third charge pump circuit 133; the first end of the third charge pump circuit 133 is connected to the second end of the first charge pump circuit 131, the second end of the third charge pump circuit 133 is connected to the gate end of the second switching transistor 160, and the third end of the third charge pump circuit 133 is connected to the second end of the second switching transistor 160; wherein: the structure and function of the third charge pump circuit 133 are similar to those of the second charge pump, and will not be repeated here.

[0124] In some embodiments, please refer to Figure 7 , Figure 8 The high-side switch circuit 100 further includes a logic control circuit 180, which is connected to the second charge pump circuit 132 (see Figure 7 ), or connected to the control terminals of the second charge pump circuit 132 and the third charge pump circuit 133 at the same time (please refer to Figure 8 ). Wherein: the logic control circuit 180 is used to generate a first control signal and transmit the first control signal to the second charge pump circuit 132; when the first control signal is in an enabled state, the second charge pump circuit 132 is turned on and the first switch transistor 121 is turned on; when the first control signal is in a disabled state, the second charge pump circuit 132 is turned off and the first switch transistor 121 is turned off. The logic control circuit 180 is also used to generate a second control signal and transmit the second control signal to the third charge pump circuit 133; when the second control signal is in an enabled state, the third charge pump circuit 133 is turned on and the second switch transistor 160 is turned on; when the second control signal is in a disabled state, the third charge pump circuit 133 is turned off and the second switch transistor 160 is turned off.

[0125] Here, the output signal of the logic control circuit 180 can be represented by CTRL_IN<1:0>, which includes the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> .

[0126] In some embodiments, the logic control circuit 180 is also used to control the opening and closing of the sixth power supply 151 and the first charge pump circuit 131 .

[0127] In some embodiments, the logic control circuit 180 is also used to receive the initial control signal output by the port 182, such as Figure 7 , Figure 8 The VCC_Ctrl signal is logically processed by the initial control signal VCC_Ctrl, and generates a first control signal in an enabled state when the initial control signal indicates to turn on the first switch transistor 121; and generates a second control signal in an enabled state when the initial control signal indicates to turn on the second switch transistor 160. Wherein, VCC_Ctrl is a 2-bit signal.

[0128] In some disclosed embodiments, Figure 7 , Figure 8As shown, the initial control signal VCC_Ctrl<1:0> of the logic control circuit 180 has four working states, namely 00, 01, 10, and 11. Specifically, when the initial control signal VCC_Ctrl<1:0>=00, the high-side switch circuit 100 is in the off state as a whole, that is, all circuits in the high-side switch circuit 100 have no static current; when the initial control signal VCC_Ctrl<1:0>=01, the sixth power supply 151, the first charge pump circuit 131 and the third charge pump circuit 133 are turned on, and the first control signal CTRL_IN <0> In the disabled state, the first switch transistor 121 is turned off, and the second control signal CTRL_IN <1> In the enabled state, the second switch transistor 160 is turned on. At this time, the seventh power supply supplies power to the load circuit 140. When the initial control signal VCC_Ctrl<1:0>=10, the first control signal CTRL_IN <0> In the enabled state, the first switch transistor is turned on, and the second control signal CTRL_IN <1> In the disabled state, the second switch transistor 160 is turned off. At this time, the first power supply 110 supplies power to the load circuit through the first switch transistor 121. When the initial control signal VCC_Ctrl<1:0>=11, the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> The first switch transistor 121 and the second switch transistor 160 are both turned off, but the sixth power supply 151 and the first charge pump circuit 131 remain turned on. It should be noted that when the high-side switch circuit does not have the second switch transistor 160, the control signal related thereto is omitted.

[0129] In the embodiment of the present disclosure, the high-side switch circuit 100 can realize the opening or closing of the second charge pump circuit 132 and the third charge pump circuit 133 under the control of the input first control signal and the second control signal, thereby switching the first power supply 110 and the seventh power supply, so that the load circuit can operate in APT mode or ET mode; thereby broadening the application scenarios of the high-side switch circuit 100.

[0130] In the embodiment of the present disclosure, in order to avoid the problem that the first switch transistor 121 and the second switch transistor 160 are turned on at the same time during the operation of the high-side switch circuit 100, resulting in excessive transient current and burning the load circuit. In some embodiments, please continue to refer to Figure 8The high-side switch circuit 100 further includes: a dead time control circuit 181; a first output terminal of the dead time control circuit 181 is connected to the control terminal of the second charge pump circuit 132, and a second output terminal of the dead time control circuit 181 is connected to the control terminal of the third charge pump circuit 133; wherein: the dead time control circuit 181 is used to control the first control signal CTRL_IN <0> and / or the second control signal CTRL_IN <1> After the delay processing is performed, the third charge pump circuit 133 is delayed to be turned on after the second charge pump circuit 132 is turned off, or the second charge pump circuit 132 is delayed to be turned on after the third charge pump circuit 133 is turned off.

[0131] Here, please continue to refer to Figure 8 , the first control signal CTRL_IN after delay processing <0> For the first target control signal, use CTRL_OUT <0> Indicates that the second control signal CTRL_IN after delay processing <1> For the second target control signal, use CTRL_OUT <1> express.

[0132] In the disclosed embodiment, since the high-side switch circuit 100 includes a first switch transistor 121 and a second switch transistor 160, during the operation of the high-side switch circuit 100, the first switch transistor 121 and the second switch transistor 160 are turned on at the same time, which may cause the transient current of the input load circuit 140 to be too large and burn the chip. Therefore, by setting a dead time control circuit 181, the first control signal and / or the second control signal are delayed and transmitted to the second charge pump circuit 132 and the third charge pump circuit 133 respectively, thereby avoiding the first switch transistor 121 and the second switch transistor 160 from being turned on at the same time, thereby making the reliability of the high-side switch circuit 100 higher.

[0133] In some embodiments, please refer to Figure 8 The high-side switch circuit 100 further includes a second body-end switch circuit 191, a first end and a second end of the second body-end switch circuit 191 are respectively connected to the gate end and the second end of the second switch transistor 160. The body end of the second switch transistor 160 is used to control the body end of the second switch transistor 160 to ensure that the second switch transistor 160 is reliably turned on and off.

[0134] It should be noted that the first switch transistor 121 in the embodiment of the present disclosure can be a depletion-type NMOS tube or an enhancement-type NMOS tube, and the second switch transistor 160 can be a depletion-type NMOS tube or an enhancement-type NMOS tube; among them, the manufacturing process of the depletion-type NMOS tube is simple; the enhancement-type NMOS tube has a fast switching speed and a stronger driving capability, and can be selected as needed during implementation.

[0135] The embodiments of the present disclosure provide Figure 8 The high-side switch circuit shown is similar to the above Figure 7 The high-side switch circuit in the embodiment is similar. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0136] In the embodiment of the present disclosure, since the driving circuit performs two lifting processes on the received sixth voltage, the gate voltages of the first switch transistor and the second switch transistor are relatively high, so that the first switch transistor and the second switch transistor can use NMOS tubes as high-side switches, which can not only reduce the area of ​​the high-side switch circuit, but also stabilize the switch resistance. In addition, the high-side switch circuit can realize the opening or closing of the second charge pump circuit 132 and the third charge pump circuit 133 under the control of the input first control signal and the second control signal, thereby switching the first power supply 110 and the seventh power supply, so that the high-side switch circuit 100 can work in APT mode or ET mode; thereby broadening the application scenario of the high-side switch circuit 100.

[0137] In some embodiments, such as Figure 8 As shown, multiple functional modules, the sixth power supply (i.e., low voltage difference linear regulator), a double charge pump (VX2 CP, i.e., the first charge pump circuit), a logic control circuit (Logic), a dead time control circuit (DeadTime Control), a gate drive charge pump (QPUMP1 / QPUMP2, i.e., the second charge pump circuit / the third charge pump circuit), and a body control (Body control) are integrated into a chip, and connected to other modules or chips through ports 152, 111, 142, 170, 182 and GND.

[0138] In addition, the embodiment of the present disclosure also provides a switch locking circuit 300. The switch locking circuit in the embodiment of the present disclosure is described in detail below in conjunction with the accompanying drawings. The switch protection circuit can be connected to the switch transistor 120 (i.e., the first switch transistor 121 and / or the second switch transistor 160). Next, the connection between the switch transistor and the first switch transistor 121 is used as an example for description.

[0139] Fig. 9 A switch locking circuit 300 is provided in an embodiment of the present disclosure, such as Fig. 9As shown, the switch locking circuit 300 is connected to the gate terminal of the first switch transistor 121, the first terminal of the first switch transistor 121 is connected to the first power supply through the port 111, and the second terminal of the first switch transistor 121 is connected to the load circuit through the port 142; wherein: the switch locking circuit 300 is used to turn on when the first switch transistor 121 is turned off, and limit the gate terminal of the first switch transistor 121 to the off voltage to maintain the off state of the first switch transistor 121, and the switch locking circuit 300 is also used to turn off when the first switch transistor 121 is turned on.

[0140] In the embodiment of the present disclosure, by adding a switch protection circuit, the voltage at the gate terminal of the first switch transistor can be maintained at a shutdown voltage when the first switch transistor is turned off, thereby avoiding the problem of unreliable shutdown of the first switch transistor and improving the reliability of the first switch transistor when it is turned off.

[0141] In some embodiments, please refer to Fig. 9 The switch locking circuit 300 includes a first locking circuit 310; a first end of the first locking circuit 310 is connected to the gate end of the first switch transistor 121, and a second end of the first locking circuit 310 is connected to a first shutdown power supply 330; wherein: the first locking circuit 310 is used to turn on when the first switch transistor 121 is turned off, and limit the gate end of the first switch transistor 121 to a shutdown voltage to maintain the shutdown state of the first switch transistor 121, and the first locking circuit 310 is also used to turn off when the first switch transistor 121 is turned on; the first shutdown power supply 330 is used to provide a shutdown voltage.

[0142] In some embodiments, please refer to Fig. 9 The first locking circuit 310 includes a first locking switch 311 and an attenuation module 312; one end of the attenuation module 312 is connected to the gate end of the first switch transistor 121 as the first end of the first locking circuit 310; the other end of the attenuation module 312 is connected to the first shutdown power supply 330 through the first locking switch 311; the attenuation module 312 is a resistor and / or inductor ( Fig. 9 shown as a resistor).

[0143] The attenuation module 312 is provided in the first locking circuit 310 to prevent excessive discharge current through the first locking switch 311 at the moment when the first switch transistor 121 is turned off, thereby ensuring reliable turn-off of the first switch transistor 121 .

[0144] Since the voltage of the attenuation module 312 in the first locking circuit 310 may fluctuate, causing the shutdown voltage to be unstable, in order to further ensure that the first switch transistor is stably turned off, some embodiments further include a second locking circuit 320. Please continue to refer to Fig. 9, a first end of the second locking circuit 320 is connected to the gate end of the first switch transistor 121, and a second end of the second locking circuit 320 is connected to the second shutdown power supply 340. Wherein: the second locking circuit 320 is used to turn on after a preset time after the first switch transistor 121 is turned off, so as to limit the gate end of the first switch transistor 121 to the shutdown voltage to maintain the first switch transistor 121 in the off state, and the second locking circuit 320 is also used to turn off when the first switch transistor 121 is turned on; the second shutdown power supply 340 is used to provide a shutdown voltage.

[0145] In some embodiments, please refer to Fig. 9 The second locking circuit 320 includes a second locking switch 321; the first end of the second locking switch 321 serves as the first end of the second locking circuit 320 and is connected to the gate end of the first switching transistor 121, and the second end of the second locking switch 321 serves as the second end of the second locking circuit 320 and is connected to the second shutdown power supply 340.

[0146] In some embodiments, the first locking switch 311 and / or the second locking switch 321 may be a transistor, for example, a field effect transistor, or a bipolar transistor. In the embodiment of the present disclosure, the first locking switch 311 and the second locking switch 321 are both NMOS transistors. The first locking switch 311 and the second locking switch 321 may be controlled to be turned on or off by clock signals CTRL1 and CTRL2, respectively.

[0147] When the first switch transistor 121 is turned off, the first locking circuit 310 is turned on, and then the second locking circuit 320 is turned on after a preset time. In this way, not only can the problem of excessive discharge current generated at the moment when the first switch transistor 121 is turned off, which causes the switch locking circuit 300 to burn out, but also the voltage of the first switch transistor 121 can be quickly maintained at the off voltage through the second locking switch 321, thereby improving the working efficiency of the switch locking circuit 300.

[0148] In some embodiments, the preset time is greater than or equal to 20 nanoseconds and less than or equal to 2 microseconds. For example, the preset time may be 40 or 100 nanoseconds.

[0149] In some embodiments, the first shutdown power supply and the second shutdown power supply are both ground. In other embodiments, the first shutdown power supply and the second shutdown power supply may also provide other voltages; for example, a voltage less than 300 millivolts.

[0150] In summary, the first switch transistor 121 is prevented from leaking electricity through two parasitic capacitors when it is turned off, namely, the capacitance between the first end and the gate end of the first switch transistor 121 (e.g., the fourth capacitor 281), and the capacitance between the second end and the gate end of the first switch transistor 121 (e.g., the fifth capacitor 282); by adding the switch locking circuit 300, namely, the first locking circuit 310 and the second locking circuit 320, the gate end voltage of the first switch transistor can be kept at the turn-off voltage, thereby ensuring that the first switch transistor 121 is closed more reliably. In addition, since the instantaneous current is too large when the first switch transistor 121 is turned off, directly closing the second locking circuit 320 may burn the second locking circuit 320. Therefore, after a preset time has passed after the first switch transistor 121 is closed, the second locking circuit 320 is turned on again, thereby reducing the damage of the instantaneous current to the second locking circuit 320 and improving the service life of the switch locking circuit. In addition, the attenuation module 312 in the first locking circuit 310 consumes the instantaneous current when the first switching transistor 121 is turned off. Furthermore, since the voltage of the attenuation module 312 swings with the voltage of the first power supply 110, after a preset time, the voltage at the gate end of the first switching transistor needs to be maintained stable at a turn-off voltage through the second locking circuit 320.

[0151] In the embodiment of the present disclosure, a second locking circuit 320 is added, and when the first switch transistor 121 is turned off, the gate terminal of the second locking circuit 320 is placed at a shutdown voltage. At the same time, in order to avoid excessive discharge current of the first switch transistor 121 through the second locking circuit 320 at the moment of turning off, the second locking circuit 320 is delayed to open relative to the first locking circuit 310, and at the same time, an attenuation module 312 is provided in the first locking circuit 310 to limit the discharge current when the first switch transistor 121 is turned off. In this way, when the first switch transistor 121 is turned off, the charge at the gate terminal of the first switch transistor 121 flows into the first shutdown power supply 330 via the first locking circuit 310, ensuring that the first switch transistor 121 is reliably turned off. At the same time, after the first switch transistor 121 is turned off, the second locking circuit 320 stably maintains the gate terminal of the first switch transistor 121 at the shutdown voltage, so that when the first power supply 110 is in the ET mode, the first switch transistor 121 has no leakage current, and the first switch transistor 121 can be reliably turned off.

[0152] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0153] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0154] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0155] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0156] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0157] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0158] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A charge pump circuit, characterized in that: The first end of the charge pump circuit is connected to the gate end of the switch transistor, the second end of the charge pump circuit and the second end of the switch transistor are both connected to the input end of the load circuit, the first end of the switch transistor is connected to the first power supply; the voltage at the gate end of the switch transistor is the gate voltage, and the voltage at the input end of the load circuit is the load voltage, wherein: The charge pump circuit is used to adjust the gate voltage according to the load voltage feedback so that the difference between the load voltage and the gate voltage is a preset voltage to turn on the switch transistor.

2. The charge pump circuit according to claim 1, characterized in that: The charge pump circuit includes a first capacitor and a second capacitor; The first plate of the first capacitor is coupled to the second power supply, the second plate of the first capacitor is coupled to the gate terminal of the switch transistor, the first plate of the second capacitor is coupled to the third power supply, and the second plate of the second capacitor is coupled to the input terminal of the load circuit; and\or, The first plate of the first capacitor is coupled to a fourth power source, the second plate of the first capacitor is coupled to an input terminal of the load circuit, the first plate of the second capacitor is coupled to a fifth power source, and the second plate of the second capacitor is coupled to a gate terminal of the switch transistor; The voltage of the second power supply is greater than the voltage of the fourth power supply, and the voltage of the fifth power supply is greater than the voltage of the third power supply.

3. The charge pump circuit according to claim 2, characterized in that: A voltage difference between the second power supply and the fourth power supply is greater than or equal to the preset voltage; A voltage difference between the fifth power source and the third power source is greater than or equal to the preset voltage; The voltages of the second power supply and the fifth power supply are the same or different; the voltages of the third power supply and the fourth power supply are the same or different.

4. The charge pump circuit according to claim 2 or 3, characterized in that: The charge pump circuit further includes: a first switch circuit and a second switch circuit; A first terminal of the first switch circuit is connected to the second plate of the first capacitor, a second terminal of the first switch circuit is connected to the second plate of the second capacitor, and a third terminal of the first switch circuit is coupled to the gate terminal of the switch transistor; A first end of the second switch circuit is connected to the second plate of the first capacitor, a second end of the second switch circuit is connected to the second plate of the second capacitor, and a third end of the second switch circuit is coupled to the input end of the load circuit; The first switch circuit is used to connect the second plate of the first capacitor or the second plate of the second capacitor to the gate terminal of the switch transistor when in operation; The second switch circuit is used to connect the second plate of the first capacitor or the second plate of the second capacitor to the input end of the load circuit during initialization.

5. The charge pump circuit according to claim 4, characterized in that: The charge pump circuit further includes: a third switch circuit and a fourth switch circuit; A first end of the third switch circuit is connected to the first plate of the first capacitor, a second end of the third switch circuit is connected to the second power supply, and a third end of the third switch circuit is connected to the fourth power supply; The first end of the fourth switch circuit is connected to the first plate of the second capacitor, the second end of the fourth switch circuit is connected to the fifth power supply, and the third end of the fourth switch circuit is connected to the third power supply; The third switch circuit is used to connect the fourth power supply to the first plate of the first capacitor when the first capacitor is initialized, and to connect the second power supply to the first plate of the first capacitor when the first capacitor is working; The fourth switch circuit is used to connect the third power supply to the first plate of the second capacitor when the second capacitor is initialized, and to connect the fifth power supply to the first plate of the second capacitor when the second capacitor is working.

6. The charge pump circuit according to claim 5, characterized in that: The third switch circuit includes a first transistor and a second transistor; the fourth switch circuit includes a third transistor and a fourth transistor; The first ends of the first transistor and the second transistor are connected to the second power supply and the fourth power supply respectively; the second ends of the first transistor and the second transistor are connected to the first plate of the first capacitor; the first ends of the third transistor and the fourth transistor are connected to the fifth power supply and the third power supply respectively; the second ends of the third transistor and the fourth transistor are connected to the first plate of the second capacitor.

7. The charge pump circuit according to claim 6, characterized in that: The first switch circuit and the second switch circuit are both cross-coupled circuits, the first switch circuit includes a fifth transistor and a sixth transistor, and the second switch circuit includes a seventh transistor and an eighth transistor; The first end of the fifth transistor and the first end of the sixth transistor are both coupled to the gate end of the switch transistor, the gate end of the fifth transistor and the second end of the sixth transistor are both connected to the second plate of the second capacitor, and the second end of the fifth transistor and the gate end of the sixth transistor are both connected to the second plate of the first capacitor; The first end of the seventh transistor and the gate end of the eighth transistor are both connected to the second plate of the first capacitor, the gate end of the seventh transistor and the first end of the eighth transistor are both connected to the second plate of the second capacitor, and the second end of the seventh transistor and the second end of the eighth transistor are both coupled to the input end of the load circuit.

8. The charge pump circuit according to claim 7, characterized in that: The charge pump circuit also includes a first resistor, a second resistor and a third capacitor; One end of the first resistor is connected to the gate terminal of the switch transistor, and the other end of the first resistor is connected to the first end of the fifth transistor and the first end of the sixth transistor; One end of the second resistor is connected to the second end of the seventh transistor and the second end of the eighth transistor, and the other end of the second resistor is connected to the input end of the load circuit; One section of the third capacitor is connected to the second end of the seventh transistor, the second end of the eighth transistor and one end of the second resistor, and the other end of the third capacitor is connected to the ground.

9. The charge pump circuit according to claim 8, characterized in that: The charge pump circuit also includes a fourth capacitor and a fifth capacitor; The fourth capacitor is connected between the first terminal of the switch transistor and the gate terminal of the switch transistor; The fifth capacitor is connected between the second terminal of the switch transistor and the gate terminal of the switch transistor; wherein: The fourth capacitor includes a parasitic capacitor or a metal plate capacitor; the fifth capacitor includes a parasitic capacitor or a metal plate capacitor.

10. The charge pump circuit according to claim 9, characterized in that: The switch transistor, the second transistor, the fourth transistor, the seventh transistor and the eighth transistor are NMOS transistors; The first transistor, the third transistor, the fifth transistor, and the sixth transistor are PMOS transistors.

11. A high side switch circuit, characterized in that: The invention comprises a charge pump circuit as claimed in any one of claims 1 to 10.

Images