Level shifter

Abstract

A level shifter includes an inverter, first to fourth N-type transistors, first / second P-type transistors, and a buffer. The inverter inverts an input voltage to generate an inverted input voltage, a gate of the first N-type transistor receives the input voltage, a gate of the second N-type transistor receives the inverted input voltage, a source of the third N-type transistor is coupled to a drain of the first N-type transistor, and a drain of the third N-type transistor is coupled to a drain of the second N-type transistor. A source of the fourth N-type transistor is coupled to a drain of the second N-type transistor, and gates of the first / second P-type transistors are respectively coupled to drains of the first / second N-type transistors. The level shifter generates an output voltage according to a shift voltage on a drain electrode of the third N-type transistor or a drain electrode of the fourth N-type transistor. According to the invention, the cross coupling voltage can be controlled under the condition that the size of the pull-down element is not greatly increased, so that the overall circuit area is reduced.

Description

Technical Field

[0001] The present invention relates to an extremely low input voltage design, and more particularly to a level shifter applicable to an extremely low input voltage. Background Art

[0002] In a level shifter that supports a wide signal range using an ultra-low voltage design (e.g., using a supply voltage of less than 0.5 volts (V)), native input / output (IO) devices are used to achieve the requirement of operating at an ultra-low voltage. However, existing manufacturing processes do not always provide native IO devices, so thick-oxide devices can be used to achieve the purpose of ultra-low voltage operation when native IO devices cannot be used.

[0003] However, the circuit design techniques proposed in the related art to achieve the requirements of ultra-low voltage operation typically significantly increase the circuit area of ​​the level shifter, and these techniques cannot achieve sufficient reliability under high standard deviation variations. Therefore, a novel level shifter architecture is needed to solve the problems of the related art. Summary of the invention

[0004] The present invention aims to provide a level shifter which can be realized with a smaller circuit area by using only thick oxide layer elements and can achieve sufficiently good reliability under high standard deviation process variation.

[0005] At least one embodiment of the present invention provides a level shifter. The level shifter includes an inverter, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a first P-type transistor, and a second P-type transistor. The inverter is used to invert an input voltage of the level shifter based on a first reference voltage to generate an inverted input voltage. A gate terminal of the first N-type transistor is used to receive the input voltage, and a source terminal of the first N-type transistor is coupled to a third reference voltage. A gate terminal of the second N-type transistor is used to receive the inverted input voltage, and a source terminal of the second N-type transistor is coupled to the third reference voltage. A source terminal of the third N-type transistor is coupled to a drain terminal of the first N-type transistor, and a gate terminal of the third N-type transistor is used to receive a bias voltage. A source terminal of the fourth N-type transistor is coupled to a drain terminal of the second N-type transistor, and a gate terminal of the fourth N-type transistor is used to receive the bias voltage. A gate terminal of the first P-type transistor is coupled to the drain terminal of the second N-type transistor, a drain terminal of the first P-type transistor is coupled to a drain terminal of the third N-type transistor, and a source terminal of the first P-type transistor is used to receive a second reference voltage. A gate terminal of the second P-type transistor is coupled to the drain terminal of the first N-type transistor, a drain terminal of the second P-type transistor is coupled to a drain terminal of the fourth N-type transistor, and a source terminal of the second P-type transistor is used to receive the second reference voltage. In particular, the level shifter generates an output voltage according to a first shift voltage on the drain terminal of the third N-type transistor or a second shift voltage on the drain terminal of the fourth N-type transistor.

[0006] The level shifter provided by the embodiment of the present invention can reduce the upper limit of a cross-coupling voltage on the cross-coupling node by isolating the output node and the cross-coupling node. Since the cross-coupling voltage is reduced, the cross-coupling voltage can be pulled down without significantly increasing the size of the pull-down element, thereby reducing the overall circuit area. Therefore, the problems of the related art are solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of a level shifter according to an embodiment of the present invention.

[0008] Figure 2 According to an embodiment of the present invention, Figure 1 Schematic diagram of some voltage waveforms in the level shifter shown.

[0009] Figure 3 FIG. 4 is a schematic diagram of a level shifter according to an embodiment of the present invention.

[0010] Figure 4 According to an embodiment of the present invention, Figure 3 Schematic diagram of some voltage waveforms in the level shifter shown.

[0011] The reference numerals are described as follows:

[0012] 10,30 Level Shifter

[0013] 110 Inverter

[0014] 120 Buffer

[0015] 121,122 Inverter

[0016] N1~N4 N-type transistor

[0017] P1~P5,P61,P62,P71,P72 P-type transistor

[0018] VDD1, VDD2, VSS reference voltage

[0019] VI Input Voltage

[0020] VIB Inverting input voltage

[0021] VIN,VIBN Cross-coupling voltage

[0022] VIP,VIBP shift voltage

[0023] VOUT Output voltage

[0024] Vtn34 N-type threshold voltage

[0025] Vtp5 P-type threshold voltage

[0026] T1, T2 time points

[0027] trd rising delay

[0028] tfd falling delay DETAILED DESCRIPTION

[0029] Figure 1 FIG. 1 is a schematic diagram of a level shifter 10 according to an embodiment of the present invention. Figure 1As shown, the level shifter 10 may include an inverter 110 operating at a first reference voltage such as a reference voltage VDD1, a first N-type transistor such as an N-type transistor N1, a second N-type transistor such as an N-type transistor N2, a third N-type transistor such as an N-type transistor N3, a fourth N-type transistor such as an N-type transistor N4, a first P-type transistor such as a P-type transistor P1, a second P-type transistor such as a P-type transistor P2, and a buffer 120 operating at a second reference voltage such as a reference voltage VDD2. The inverter 110 is used to invert an input voltage VI of the level shifter 10 based on the reference voltage VDD1 to generate an inverted input voltage VIB. The gate terminal of the N-type transistor N1 is used to receive the input voltage VI, and the source terminal of the N-type transistor N1 is coupled to a third reference voltage such as a reference voltage VSS. The gate terminal of the N-type transistor N2 is used to receive the inverted input voltage VIB, and the source terminal of the N-type transistor N2 is coupled to the third reference voltage such as the reference voltage VSS. The source terminal of the N-type transistor N3 is coupled to the drain terminal of the N-type transistor N1, and the source terminal of the N-type transistor N4 is coupled to the drain terminal of the N-type transistor N2. The gate terminal of the P-type transistor P1 is coupled to the drain terminal of the N-type transistor N2, the drain terminal of the P-type transistor P1 is coupled to the drain terminal of the N-type transistor N3, and the source terminal of the P-type transistor P1 is used to receive the reference voltage VDD2. The gate terminal of the P-type transistor P2 is coupled to the drain terminal of the N-type transistor N1, the drain terminal of the P-type transistor P2 is coupled to the drain terminal of the N-type transistor N4, and the source terminal of the P-type transistor P2 is used to receive the reference voltage VDD2. In particular, the level shifter 10 can generate an output voltage VOUT according to a first shift voltage (e.g., VIP) at the drain terminal of the N-type transistor N3 or a second shift voltage (e.g., VIBP) at the drain terminal of the N-type transistor N4. For example, the buffer 120 is driven by the shift voltage VIP or the shift voltage VIBP to generate the output voltage VOUT of the level shifter 10 .

[0030] In the present embodiment, the buffer 120 may include one or more inverters connected in series. For example, the buffer 120 may include an even number of inverters connected in series (e.g., inverters 121 and 122 operating at the reference voltage VDD2), wherein the buffer 120 is driven by the shift voltage VIBP at the drain terminal of the N-type transistor N4 to generate the output voltage VOUT. For another example, the buffer 120 may include an even number of inverters connected in series, wherein the buffer 120 is driven by the shift voltage VIP at the drain terminal of the N-type transistor N3 to generate the output voltage VOUT.

[0031] It should be noted that the reference voltage VDD1 may be an extremely low voltage below 0.55 volts (V), which is very close to the N-type threshold voltage Vtn12 of the N-type transistors N1 and N2. In order to properly enable the state conversion of the level shifter 10, the pull-down current of the N-type transistor N1 needs to be greater than the pull-up current of the P-type transistor P1 to ensure that the transistor N1 can pull down the cross-coupling voltage VIN when the input voltage VI is pulled up from VSS to VDD1, and the pull-down current of the N-type transistor N2 needs to be greater than the pull-up current of the P-type transistor P2 to ensure that the transistor N2 can pull down the cross-coupling voltage VIBN when the input voltage VI is pulled down from VDD1 to VSS. In this embodiment, the level shifter 10 may further include a third P-type transistor such as a P-type transistor P3 and a fourth P-type transistor such as a P-type transistor P4 to limit the pull-up current of any one of the P-type transistors P1 and P2. The P-type transistor P3 is coupled between the drain terminal of the P-type transistor P1 and the drain terminal of the N-type transistor N3, so that the drain terminal of the P-type transistor P1 is coupled to the drain terminal of the N-type transistor N3 through the P-type transistor P3, wherein the gate terminal of the P-type transistor P3 is used to receive the input voltage VI. The P-type transistor P4 is coupled between the drain terminal of the P-type transistor P2 and the drain terminal of the N-type transistor N4, so that the drain terminal of the P-type transistor P2 is coupled to the drain terminal of the N-type transistor N4 through the P-type transistor P4, wherein the gate terminal of the P-type transistor P4 is used to receive the inverting input voltage VIB. When the input voltage VI is pulled up from the third reference voltage such as the reference voltage VSS to the reference voltage VDD1 (which means that the inverting input voltage VIB is pulled down from the reference voltage VDD1 to the reference voltage VSS), the pull-up current of the P-type transistor P1 can be limited by the P-type transistor P3 (the P-type transistor P3 is turned off by the input signal VI). When the input voltage VI is pulled down from the reference voltage VDD1 to the reference voltage VSS (which means the inverting input voltage VIB is pulled up from the reference voltage VSS to the reference voltage VDD1 ), the pull-up current of the P-type transistor P2 can be limited by the P-type transistor P4 (by the inverting input signal VIB being turned off).

[0032] Therefore, the pull-up current of the P-type transistor P3 (or the pull-up current of the P-type transistor P1) can be smaller than the pull-down current of the N-type transistor N1, and the pull-up current of the P-type transistor P4 (or the pull-up current of the P-type transistor P2) can be smaller than the pull-down current of the N-type transistor N2. In particular, by minimizing the channel width of the P-type transistor P3 and the P-type transistor P4 and maximizing the channel length of the P-type transistor P3 and the P-type transistor P4 according to the design rules of the semiconductor process used to manufacture the level shifter 10, the pull-up current of each of the P-type transistors P3 and P4 can be minimized.

[0033] In the present embodiment, the gate terminals of the N-type transistors N3 and N4 are used to receive a bias voltage and the N-type transistors N3 and N4 are turned on by the bias voltage control, wherein the upper limit of the cross-coupling voltage (e.g., each of the cross-coupling voltages VIN and VIBN) at each of the drain terminals of the N-type transistors N1 and N2 is controlled according to the bias voltage and the N-type threshold voltage Vtn34 of each of the N-type transistors N3 and N4. In particular, the upper limit of the cross-coupling voltages VIN and VIBN is equal to the bias voltage minus the N-type threshold voltage Vtn34, wherein the upper limit of the cross-coupling voltages VIN and VIBN is preferably lower than the reference voltage VDD2. In the present embodiment, the bias voltage is equal to the reference voltage VDD2, which means that the gate terminals of the N-type transistors N3 and N4 are used to receive the reference voltage VDD2, so that the upper limit of the cross-coupling voltages VIN and VIBN is equal to (VDD2-Vtn34).

[0034] Figure 2 According to an embodiment of the present invention, Figure 1 The waveform diagram of some voltages (e.g., input voltage VI, inverting input voltage VIB, cross-coupling voltages VIN and VIBN, shift voltages VIBP and VIP, and output voltage VOUT) in the level shifter 10 is shown. When the input signal VI is pulled up from VSS to VDD1 at time point T1, the inverting input voltage VIB is pulled down from VDD1 to VSS, wherein the N-type transistor N2 is turned off, and the P-type transistor P3 is turned off to limit the pull-up current of the P-type transistors P1 and P3, allowing the N-type transistor N1 to be turned on to start pulling the cross-coupling voltage VIN at the drain terminal of the N-type transistor N1 from (VDD2-Vtn34) to VSS. Since the cross-coupling voltage VIN and the inverting input voltage VIB are pulled down to VSS, the P-type transistors P2 and P4 are both turned on to pull the shift voltage VIBP from VSS to VDD2. In addition, since the N-type transistor N4 is turned on, the cross-coupling voltage VIBN at the drain terminal of the N-type transistor N2 is pulled up from VSS to (VDD2-Vtn34) when the shift voltage VIBP is pulled up to VDD2, and the P-type transistor P1 is turned off. In addition, since the N-type transistor N3 is turned on, the shift voltage VIP at the drain terminal of the N-type transistor N3 can be pulled down from VDD2 to VSS when the cross-coupling voltage VIN is pulled down to VSS. As described above, the shift voltage VIP at the drain terminal of the N-type transistor N3 can be pulled down from VDD2 to VSS and the shift voltage VIBP at the drain terminal of the N-type transistor N4 can be pulled up from VSS to VDD2, so that the output voltage VOUT is pulled up from VSS to VDD2 after a rising delay trd from the time point T1, and the rising delay trd is caused by the buffer 120.

[0035] When the input voltage VI is pulled down from VDD1 to VSS at time point T2, the inverting input voltage VIBN is pulled up from VSS to VDD1, wherein the N-type transistor N1 is turned off, and the P-type transistor P4 is turned off to limit the pull-up current of the P-type transistors P2 and P4, allowing the N-type transistor N2 to be turned on to start pulling down the cross-coupling voltage VIBN at the drain terminal of the N-type transistor N2 from (VDD2-Vtn34) to VSS. Since the cross-coupling voltage VIBN and the input voltage VI are pulled down to VSS, the P-type transistors P1 and P3 are both turned on to pull up the shift voltage VIP from VSS to VDD2. In addition, since the N-type transistor N3 is turned on, the cross-coupling voltage VIN at the drain terminal of the N-type transistor N1 is pulled up from VSS to (VDD2-Vtn34) when the shift voltage VIP is pulled up to VDD2, and the P-type transistor P2 is therefore turned off. In addition, since the N-type transistor N4 is turned on, the shift voltage VIBP at the drain terminal of the N-type transistor N4 can be pulled down from VDD2 to VSS when the cross-coupling voltage VIBN is pulled down to VSS. As described above, the shift voltage VIP at the drain terminal of the N-type transistor N3 can be pulled up from VSS to VDD2 and the shift voltage VIBP at the drain terminal of the N-type transistor N4 can be pulled down from VDD2 to VSS, so that the output voltage VOUT is pulled down from VDD2 to VSS after a falling delay tfd from the time point T2, and the falling delay tfd is caused by the buffer 120.

[0036] It should be noted that, since the upper bounds of the shift voltages VIN and VIBN are (VDD2-Vtn34) rather than VDD2, if (VDD2-Vtn34)<(VDD2-Vtp12), the P-type transistors P1 and P2 may derive a direct current (DC current), wherein Vtp12 represents the P-type threshold voltage of the P-type transistors P1 and P2. In some embodiments, the size of the P-type transistors P1 and P2 and / or the size of the N-type transistors N3 and N4 may be determined based on ensuring that (VDD2-Vtn34) is not less than (VDD2-Vtp12) to minimize the DC current.

[0037] Figure 3 FIG. 1 is a schematic diagram of a level shifter 30 according to an embodiment of the present invention. Figure 3 As shown, the level shifter 30 may include an inverter 110, N-type transistors N1, N2, N3 and N4, P-type transistors P1, P2, P3 and P4, and a buffer 120, wherein the operation of these components is similar to Figure 1The contents described in the embodiment of are the same, and are not repeated here for the sake of simplicity. In the present embodiment, the level shifter 30 may further include a fifth P-type transistor such as a P-type transistor P5, at least one sixth P-type transistor such as P-type transistors P61 and P62, and at least one seventh P-type transistor such as P-type transistors P71 and P72. The gate terminal of the P-type transistor P5 is coupled to the drain terminal of the P-type transistor P5, and the source terminal of the P-type transistor P5 is used to receive the reference voltage VDD2. The P-type transistors P61 and P62 are coupled between the drain terminal of the P-type transistor P5 and the drain terminal of the N-type transistor N1, wherein the P-type transistor P61 is coupled between the drain terminal of the P-type transistor P5 and the source terminal of the P-type transistor P62, and the P-type transistor P62 is coupled between the drain terminal of the P-type transistor P61 and the drain terminal of the N-type transistor N1. The P-type transistors P71 and P72 are coupled between the drain terminal of the P-type transistor P5 and the drain terminal of the N-type transistor N2, wherein the P-type transistor P71 is coupled between the drain terminal of the P-type transistor P5 and the source terminal of the P-type transistor P72, and the P-type transistor P72 is coupled between the drain terminal of the P-type transistor P71 and the drain terminal of the N-type transistor N2. In addition, the gate terminals of the P-type transistors P61 and P62 are coupled to the drain terminal of the N-type transistor N2, and the gate terminals of the P-type transistors P71 and P72 are coupled to the drain terminal of the N-type transistor N1. In some embodiments, the P-type transistors P61 and P62 may be combined into one P-type transistor, and the P-type transistors P71 and P72 may be combined into one P-type transistor, but the present invention is not limited thereto.

[0038] It should be noted that the pull-up current of the P-type transistor P1 (or the pull-up current of the P-type transistor P3) plus the pull-up current of the P-type transistors P61 and P62 can be less than the pull-down current of the N-type transistor N1, so as to ensure that the N-type transistor N1 can pull down the cross-coupling voltage VIN when the input voltage VI is pulled up from VSS to VDD1. Similarly, the pull-up current of the P-type transistor P2 (or the pull-up current of the P-type transistor P4) plus the pull-up current of the P-type transistors P71 and P72 can be less than the pull-down current of the N-type transistor N2, so as to ensure that the N-type transistor N2 can pull down the cross-coupling voltage VIBN when the input voltage VI is pulled down from VDD1 to VSS. Therefore, the P-type transistors P61, P62, P71 and P72 are preferably weak elements. In particular, by minimizing the channel width of P-type transistors P61, P62, P71 and P72 and maximizing the channel length of P-type transistors P61, P62, P71 and P72 according to the design rules of the semiconductor process used to manufacture the level shifter 30, the pull-up current of P-type transistors P61 and P62 and the pull-up current of P-type transistors P71 and P72 can be minimized.

[0039] In this embodiment, the sizes (ie, dimensions) of the P-type transistors P5, P1, and P2 are the same, so that the P-type threshold voltage Vtp5 of the P-type transistor P5 is equal to the P-type threshold voltage Vtp12 of the P-type transistors P1 and P2. Figure 3 In the structure of the level shifter 30 shown, the upper limit of each of the cross-coupling voltage VIN at the drain terminal of the N-type transistor N1 and the cross-coupling voltage VIBN at the drain terminal of the N-type transistor N2 can be controlled according to the reference voltage VDD2 and the P-type threshold voltage Vtp5 of the P-type transistor P5. In particular, the upper limits of the cross-coupling voltages VIN and VIBN can be equal to (VDD2-Vtp5).

[0040] It should be noted that since the upper limit of the cross-coupling voltage VIN and VIBN is (VDD2-Vtp5) (equal to (VDD2-Vtp12) rather than (VDD2-Vtn34)), the P-type transistors P1 and P2 can be turned off or the P-type transistors P1 and P2 can enter the sub-threshold region. Figure 1 The DC current derived from the P-type transistors P1 and P2 of the level shifter 10 shown in FIG. Figure 3 The DC current derived from the P-type transistors P1 and P2 of the level shifter 30 can be reduced.

[0041] Figure 4 According to an embodiment of the present invention, Figure 3 The waveform diagram of some voltages (such as input voltage VI, inverting input voltage VIB, cross-coupling voltages VIN and VIBN, shift voltages VIBP and VIP, and output voltage VOUT) in the level shifter 30 is shown. It should be noted that Figure 2 as well as Figure 4The difference between the embodiments is only the upper limit of the cross-coupling voltage VIN and VIBN. When the input voltage VI is pulled up from VSS to VDD1 at time point T1, the N-type transistor N1 is turned on, and the cross-coupling voltage VIN at the drain terminal of the N-type transistor N1 is pulled down from (VDD2-Vtp5) to VSS. Since the cross-coupling voltage VIN is pulled down to VSS, the P-type transistors P71 and P72 are turned on, wherein the P-type transistors P71 and P72 are weak elements, so that the P-type transistor P5 operates in the sub-critical region, so that the gate terminal and the drain terminal of the P-type transistor P5 are self-biased at (VDD2-Vtp5). Since the P-type transistors P71 and P72 are turned on, the cross-coupling voltage VIBN at the drain terminal of the N-type transistor N2 and the drain terminal of the P-type transistor P72 is pulled up from VSS to (VDD2-Vtp5), and the P-type transistors P61 and P62 are turned off, wherein the shift voltage VIP at the drain terminal of the N-type transistor N3 is pulled down from VDD2 to VSS and the shift voltage VIBP at the drain terminal of the N-type transistor N4 is pulled up from VSS to VDD2. Other details such as the bias conditions of other transistors can be based on Figure 2 By analogy with the embodiments of Figure 2 as well as Figure 4 The difference between the embodiments is that the cross-coupling voltage VIBN is pulled up to (VDD2-Vtp5) at the time point T1, so that the P-type transistor P1 can be turned off or enter the sub-critical region to reduce the DC current.

[0042] When the input voltage VI is pulled down from VDD1 to VSS at time point T2 (which means that the inverting input voltage VIB is pulled up from VSS to VDD1), the N-type transistor N2 is turned on, and the cross-coupling voltage VIBN at the drain terminal of the N-type transistor N2 is pulled down from (VDD2-Vtp5) to VSS. Since the cross-coupling voltage VIBN is pulled down to VSS, the P-type transistors P61 and P62 are turned on, wherein the P-type transistors P61 and P62 are weak elements, so that the P-type transistor P5 operates in the sub-critical region, so that the gate terminal and the drain terminal of the P-type transistor P5 are self-biased at (VDD2-Vtp5). Since the P-type transistors P61 and P62 are turned on, the cross-coupling voltage VIN at the drain terminal of the N-type transistor N1 and the drain terminal of the P-type transistor P62 is pulled up from VSS to (VDD2-Vtp5), and the P-type transistors P71 and P72 are turned off, wherein the shift voltage VIBP at the drain terminal of the N-type transistor N4 is pulled down from VDD2 to VSS and the shift voltage VIP at the drain terminal of the N-type transistor N3 is pulled up from VSS to VDD2. Other details such as the bias conditions of other transistors can be based on Figure 2 By analogy with the embodiments of Figure 2 as well as Figure 4 The difference between the embodiments is that the cross-coupling voltage VIN is pulled up to (VDD2-Vtp5) at the time point T2, so that the P-type transistor P2 can be turned off or enter the sub-critical region to reduce the DC current.

[0043] In summary, the level shifters 10 and 30 can both reduce the upper limits of the cross-coupling voltages VIN and VIBN, which enables the sizes of the N-type transistors N1 and N2 to be significantly reduced when operating at very low voltages compared to the related art. Figure 1 The level shifter 10 shown aims to achieve the smallest circuit area and the best performance (eg, the least delay), and Figure 3 The illustrated level shifter 30 aims to achieve the minimum DC current and the best reliability (e.g., the highest tolerance to process variations). In particular, compared to the related art, the level shifters 10 and 30 can have a smaller circuit area, better performance, lower power consumption, and better reliability. Therefore, the embodiments of the present invention can solve the problems of the related art without or with less side effects.

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A level shifter, characterized in that: Include: an inverter, configured to invert an input voltage of the level shifter based on a first reference voltage to generate an inverted input voltage; a first N-type transistor, wherein a gate terminal of the first N-type transistor is used to receive the input voltage, and a source terminal of the first N-type transistor is coupled to a third reference voltage; a second N-type transistor, wherein a gate terminal of the second N-type transistor is used to receive the inverting input voltage, and a source terminal of the second N-type transistor is coupled to the third reference voltage; a third N-type transistor, wherein a source terminal of the third N-type transistor is coupled to a drain terminal of the first N-type transistor, and a gate terminal of the third N-type transistor is used to receive a bias voltage; a fourth N-type transistor, wherein a source terminal of the fourth N-type transistor is coupled to a drain terminal of the second N-type transistor, and a gate terminal of the fourth N-type transistor is used to receive the bias voltage; a first P-type transistor, wherein a gate terminal of the first P-type transistor is coupled to the drain terminal of the second N-type transistor, a drain terminal of the first P-type transistor is coupled to a drain terminal of the third N-type transistor, and a source terminal of the first P-type transistor is used to receive a second reference voltage; as well as a second P-type transistor, wherein a gate terminal of the second P-type transistor is coupled to the drain terminal of the first N-type transistor, a drain terminal of the second P-type transistor is coupled to a drain terminal of the fourth N-type transistor, and a source terminal of the second P-type transistor is used to receive the second reference voltage; The level shifter generates an output voltage according to a first shift voltage on the drain terminal of the third N-type transistor or a second shift voltage on the drain terminal of the fourth N-type transistor.

2. The level shifter according to claim 1, wherein: A pull-down current of each of the first N-type transistor and the second N-type transistor is greater than a pull-up current of each of the first P-type transistor and the second P-type transistor.

3. The level shifter according to claim 1, wherein: Also includes: a third P-type transistor coupled between a drain terminal of the first P-type transistor and the drain terminal of the third N-type transistor, wherein a gate terminal of the third P-type transistor is used to receive the input voltage; as well as A fourth P-type transistor is coupled between a drain terminal of the second P-type transistor and the drain terminal of the fourth N-type transistor, wherein a gate terminal of the fourth P-type transistor is used to receive the inverted input voltage.

4. The level shifter according to claim 3, wherein: The third N-type transistor and the fourth N-type transistor are turned on by the bias control. When the input voltage is pulled up from the third reference voltage to the first reference voltage, the first N-type transistor is turned on, the third P-type transistor is turned off, the second N-type transistor is turned off, the fourth P-type transistor is turned on, the voltage at the drain terminal of the first N-type transistor is pulled down to turn on the second P-type transistor, the second shift voltage is pulled up to the second reference voltage, and the voltage at the drain terminal of the second N-type transistor is pulled up to turn off the first P-type transistor.

5. The level shifter according to claim 4, wherein: When the input voltage is pulled down from the first reference voltage to the third reference voltage, the first N-type transistor is turned off, the third P-type transistor is turned on, the second N-type transistor is turned on, the fourth P-type transistor is turned off, the voltage at the drain terminal of the second N-type transistor is pulled down to turn on the first P-type transistor, the first shift voltage is pulled up to the second reference voltage, and the voltage at the drain terminal of the first N-type transistor is pulled up to turn off the second P-type transistor.

6. The level shifter according to claim 3, wherein: A pull-up current of each of the third P-type transistor and the fourth P-type transistor is smaller than a pull-down current of each of the first N-type transistor and the second N-type transistor.

7. The level shifter according to claim 6, wherein: The pull-up current is minimized by minimizing the channel width of the third P-type transistor and the fourth P-type transistor and maximizing the channel length of the third P-type transistor and the fourth P-type transistor according to the design rules of the semiconductor process used to manufacture the level shifter.

8. The level shifter according to claim 1, wherein: An upper limit of a cross-coupling voltage at each of the drain terminal of the first N-type transistor and the drain terminal of the second N-type transistor is controlled according to the bias voltage and an N-type threshold voltage of each of the third N-type transistor and the fourth N-type transistor.

9. The level shifter according to claim 8, wherein: The bias voltage is equal to the second reference voltage, the upper limit of the cross-coupling voltage is equal to the bias voltage minus the N-type threshold voltage, and the upper limit of the cross-coupling voltage is less than the second reference voltage.

10. The level shifter according to claim 8, wherein: When the input voltage is pulled up from the third reference voltage to the first reference voltage, the cross-coupling voltage at the drain terminal of the first N-type transistor is pulled down to the third reference voltage, and the cross-coupling voltage at the drain terminal of the second N-type transistor is pulled up from the third reference voltage to the second reference voltage minus the N-type threshold voltage, so that the first shift voltage at the drain terminal of the third N-type transistor is pulled down from the second reference voltage to the third reference voltage and the second shift voltage at the drain terminal of the fourth N-type transistor is pulled up from the third reference voltage to the second reference voltage.

11. The level shifter according to claim 1, wherein: Also includes: a buffer, configured to be driven by the first shift voltage or the second shift voltage to generate the output voltage of the level shifter.

12. The level shifter according to claim 1, wherein: Also includes: a fifth P-type transistor, wherein a gate terminal of the fifth P-type transistor is coupled to a drain terminal of the fifth P-type transistor, and a source terminal of the fifth P-type transistor is used to receive the second reference voltage; at least one sixth P-type transistor coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the first N-type transistor; as well as at least one seventh P-type transistor coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the second N-type transistor; A gate terminal of the at least one sixth P-type transistor is coupled to the drain terminal of the second N-type transistor, and a gate terminal of the at least one seventh P-type transistor is coupled to the drain terminal of the first N-type transistor.

13. The level shifter according to claim 12, wherein: A first pull-up current of each of the first P-type transistor and the second P-type transistor plus a second pull-up current of each of the at least one sixth P-type transistor and the at least one seventh P-type transistor is less than a pull-down current of each of the first N-type transistor and the second N-type transistor.

14. The level shifter according to claim 13, wherein: The second pull-up current is minimized by minimizing the channel width of the at least one sixth P-type transistor and the at least one seventh P-type transistor and maximizing the channel length of the at least one sixth P-type transistor and the at least one seventh P-type transistor according to the design rules of the semiconductor process used to manufacture the level shifter.

15. The level shifter according to claim 12, wherein: The fifth P-type transistor, the first P-type transistor, and the second P-type transistor are all the same in size.

16. The level shifter according to claim 12, wherein: An upper limit of a cross-coupling voltage at each of the drain terminal of the first N-type transistor and the drain terminal of the second N-type transistor is controlled according to the second reference voltage and a P-type threshold voltage of the fifth P-type transistor.

17. The level shifter according to claim 16, wherein: The upper limit of the cross-coupling voltage is equal to the second reference voltage minus the P-type threshold voltage.

18. The level shifter according to claim 17, wherein: When the input voltage is pulled up from the third reference voltage to the first reference voltage, the cross-coupling voltage at the drain terminal of the first N-type transistor is pulled down from the second reference voltage minus the P-type threshold voltage to the third reference voltage, and the cross-coupling voltage at the drain terminal of the second N-type transistor is pulled up from the third reference voltage to the second reference voltage minus the P-type threshold voltage, so that the first shift voltage at the drain terminal of the third N-type transistor is pulled down from the second reference voltage to the third reference voltage and the second shift voltage at the drain terminal of the fourth N-type transistor is pulled up from the third reference voltage to the second reference voltage.

19. The level shifter according to claim 1, wherein: Also includes: a third P-type transistor coupled between a drain terminal of the first P-type transistor and the drain terminal of the third N-type transistor, wherein a gate terminal of the third P-type transistor is used to receive the input voltage; a fourth P-type transistor coupled between a drain terminal of the second P-type transistor and the drain terminal of the fourth N-type transistor, wherein a gate terminal of the fourth P-type transistor is used to receive the inverted input voltage; a fifth P-type transistor, wherein a gate terminal of the fifth P-type transistor is coupled to a drain terminal of the fifth P-type transistor, and a source terminal of the fifth P-type transistor is used to receive the second reference voltage; at least one sixth P-type transistor coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the first N-type transistor; as well as at least one seventh P-type transistor coupled between the drain terminal of the fifth P-type transistor and the drain terminal of the second N-type transistor; A gate terminal of the at least one sixth P-type transistor is coupled to the drain terminal of the second N-type transistor, and a gate terminal of the at least one seventh P-type transistor is coupled to the drain terminal of the first N-type transistor.

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