Signal generator, signal generation method and integrated circuit chip

Abstract

The invention provides a signal generator, a signal generation method and an integrated circuit chip. The signal generator comprises an interface module, a register module, a signal generation module and a storage module, the interface module is connected with the register module and the signal generation module and is used for receiving configuration information and original data outside the signal generator, transmitting the configuration information to the register module and transmitting the original data to the signal generation module; the register module is connected with the signal generation module and is used for storing the configuration information and providing the configuration information for the signal generation module; the signal generation module comprises at least one signal generation unit; and the signal generation unit is used for performing pulse modulation and / or delay processing on the original data according to the original data and the configuration information, and outputting a waveform signal corresponding to the original data. The device is used for improving the flexibility of signal generation.

Description

Technical Field

[0001] The present application relates to digital circuits, and more particularly to a signal generator, a signal generating method and an integrated circuit chip. Background Art

[0002] A signal generator is a device that generates specific signals. It can generate corresponding waveform signals based on serial data. The generated signals can be used as synchronization signals, address codes, data, control signals, etc. It can not only be used in ultrasound, radar, medical imaging, laser control, communication and other fields, but also widely used in cutting-edge scientific fields such as quantum computing, quantum communication, and quantum precision measurement.

[0003] In the prior art, signal generators often only support the generation of a single type of waveform signal, which is difficult to meet the various needs of actual production. Summary of the invention

[0004] The present application provides a signal generator, a signal generating method and an integrated circuit chip, so as to improve the flexibility of signal generation.

[0005] In one aspect, the present application provides a signal generator, comprising: an interface module, a register module, a signal generation module and a storage module;

[0006] The interface module is connected to the register module and the signal generating module, and is used to receive configuration information and original data outside the signal generator, transmit the configuration information to the register module, and transmit the original data to the signal generating module;

[0007] The register module is connected to the signal generating module, and is used to store configuration information and provide the configuration information to the signal generating module;

[0008] The signal generating module includes at least one signal generating unit; the signal generating unit is used to perform pulse modulation and / or delay processing on the original data according to the original data and the configuration information, and output a waveform signal corresponding to the original data.

[0009] In a possible implementation, the signal generating unit includes: a trigger signal generating module, a pulse modulation module and a delay interpolation module;

[0010] The trigger signal generating module is used to receive a trigger signal and output an enabling signal according to the trigger signal;

[0011] The pulse modulation module is connected to the trigger signal generating module and receives configuration information and original data. The pulse modulation module is used to, according to the configuration information, perform pulse modulation of a corresponding mode type on the original data after receiving the enabling signal to obtain a modulation signal corresponding to the original data; wherein the configuration information includes the type of pulse modulation;

[0012] The delay interpolation module is connected to the pulse modulation module and is used to perform delay processing on the modulation signal to obtain a waveform signal corresponding to the original data.

[0013] In a possible implementation, the delay interpolation module includes: a delay chain and selection module;

[0014] The delay chain is connected to the pulse modulation module and is used to delay the modulation signal to obtain a delayed signal;

[0015] The selection module is connected to the delay chain and is used to select and output a part of the delayed signal.

[0016] In a possible implementation, the delay chain includes: a plurality of delay units connected in series; the plurality of delay units are used to perform multi-stage delay on the modulated signal.

[0017] In a possible implementation manner, the delay unit includes an inverter.

[0018] In a possible implementation, the selection module receives a start signal and an end signal, a start time of the partial signal is the same as a rising edge time of the start signal, and an end time of the partial signal is the same as a rising edge time of the end signal.

[0019] In a possible implementation, the selection module includes a latch, a pulse counter and a calculation module;

[0020] The latch receives a start signal, an end signal and the delay signal, and is used to sample the delay signal when a rising edge of the start signal is detected, and stop sampling when a first rising edge of the delay signal is detected, so as to obtain a first signal segment; and, sample the delay signal when a rising edge of the end signal is detected, and stop sampling when a second rising edge of the delay signal is detected, so as to obtain a second signal segment;

[0021] The pulse counter is used to receive the start signal, the end signal and the delay signal, and is used to count the delay signal according to the start signal and the end signal when a first rising edge of the delay signal is detected to obtain a third signal segment and a fourth signal segment;

[0022] The calculation module is connected to the latch and the pulse counter, and is used to calculate a partial signal in the delayed signal as the waveform signal based on the first signal segment, the second signal segment, the third signal segment and the fourth signal segment; wherein the partial signal is the difference between the fourth signal segment and the second signal segment minus the difference between the third signal segment and the first signal segment.

[0023] In a possible implementation, the calculation module includes: a first calculation unit, a second calculation unit, and a third calculation unit;

[0024] The first calculation unit is connected to the latch and the pulse counter, and is used to receive the first signal segment and the third signal segment, and calculate the difference between the third signal segment and the first signal segment as the fifth signal segment;

[0025] The second calculation unit is connected to the latch and the pulse counter, and is used to receive the second signal segment and the fourth signal segment, and calculate the difference between the fourth signal segment and the second signal segment as a sixth signal segment;

[0026] The third calculation unit is connected to the first calculation unit and the second calculation unit, and is used to calculate the difference between the sixth signal segment and the fifth signal segment to obtain the partial signal.

[0027] In a possible implementation, the signal generating unit further includes: a de-jitter module;

[0028] The de-jitter module is connected to the delay interpolation module and is used to detect whether jitter occurs in the waveform signal. If jitter occurs, an interrupt signal is generated.

[0029] In a possible implementation, the trigger signal generating module is specifically used to:

[0030] After receiving the trigger signal, the enabling signal is output after a predetermined time delay.

[0031] In a possible implementation, the signal generating unit further includes: a data buffer;

[0032] The data buffer is connected to the pulse modulation module and is used to receive and store original data;

[0033] The pulse modulation module is further used to send a read enable signal to the data buffer, and configure the read enable signal to be enabled when the enable signal is received; and read original data from the data buffer when the read enable signal is enabled.

[0034] In a possible implementation, the signal generating unit further includes: a request module;

[0035] The request module is connected to the data buffer and is used to obtain the data volume of the data buffer. When the data volume is lower than a preset value, a storage transfer request is initiated to a direct memory access controller so that the direct memory access controller transfers original data to the data buffer.

[0036] In a possible implementation, the configuration information further includes the frequency, length, phase, and number of repetitions of the signal; and the pulse modulation module is further used to:

[0037] A corresponding modulation signal is generated according to the signal configuration information.

[0038] In a possible implementation, the signal generator further includes: a combination module;

[0039] The combining module is used to combine the signals output by the at least one signal generating unit.

[0040] In a possible implementation, the register data further includes a channel enable signal, and the register module is further used for:

[0041] Sending a channel enable signal to the at least one signal generating unit respectively;

[0042] The signal generating unit is further configured to output a signal to the combining module when the received channel enabling signal is enabled.

[0043] In a possible implementation, the signal generator further includes: an interrupt module;

[0044] The interrupt module is used to detect the number of signals output by the at least one signal generating unit within a predetermined time, and output an interrupt signal after the number of signals reaches a set upper limit.

[0045] On the other hand, an embodiment of the present application provides a signal generating method, the method comprising:

[0046] When the data volume of the signal transmitted by the interface module received by the signal generating module is less than the preset value, the preset data in the storage module is transmitted to the signal generating unit to realize automatic handling of the waveform generating data and form an output signal of a custom waveform; when the data volume of the signal transmitted by the interface module received by the signal generating module is greater than or equal to the preset value, the signal generating unit in the signal generating module performs delay adjustment on the signal transmitted by the interface module to obtain an output signal; the delay adjustment includes controlling the enable signal to delay a preset effective time to realize coarse delay control and / or realizing fine delay control by delay interpolation; transmitting configuration information to the signal generating module, the configuration information is stored in the register module, including a trigger mode; when the signal generating unit receives a trigger signal matching the trigger mode, the output signal is output.

[0047] On the other hand, an embodiment of the present application provides an integrated circuit chip, comprising the signal generator as described above.

[0048] The present application provides a signal generator, a signal generating method and an integrated circuit chip. The signal generator includes: an interface module, a register module, a signal generating module and a storage module; the interface module is connected to the register module and the signal generating module, receives configuration information and original data outside the signal generator and transmits them to the register module and the signal generating module respectively; the register module is connected to the signal generating module, stores the configuration information and provides the configuration information to the signal generating module; the signal generating module includes at least one signal generating unit; the signal generating unit performs pulse modulation and / or delay processing on the original data according to the original data and the configuration information, and outputs a waveform signal corresponding to the original data, so that the signal generating unit can be controlled to output a custom type of waveform signal according to the original data by configuring the mode information, which can effectively improve the flexibility of signal generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0050] Figure 1 exemplarily shows a structural schematic diagram of a signal generator provided in an embodiment of the present application;

[0051] Figure 2 The structural diagram of the signal generating unit provided in the embodiment of the present application is exemplarily shown in FIG.

[0052] Figure 3 The structural schematic diagram of the rectifier circuit provided in the embodiment of the present application and the structural schematic diagram of the delay interpolation module are exemplarily shown in FIG.

[0053] Figure 4A schematic diagram of the signal timing provided by an embodiment of the present application is exemplarily shown in FIG.

[0054] Figure 5 exemplarily shows a structural schematic diagram of another signal generating unit provided in an embodiment of the present application;

[0055] Figure 6 The structural diagram of the de-jitter circuit provided in the embodiment of the present application is exemplarily shown in FIG.

[0056] Figure 7 exemplarily shows a structural schematic diagram of another signal generator provided in an embodiment of the present application;

[0057] Figure 8 Schematic diagram of the structure of another signal generator provided in an embodiment of the present application is shown in FIG.

[0058] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0059] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0060] The module in this application refers to a functional module or a logical module. It can be in software form, and its functions are realized by executing program code by a processor; it can also be in hardware form. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0061] A signal generator is a device that generates specific signals. It can generate corresponding waveform signals based on serial data. The generated signals can be used as synchronization signals, address codes, data, control signals, etc. It can not only be used in ultrasound, radar, medical imaging, laser control, communication and other fields, but also widely used in cutting-edge scientific fields such as quantum computing, quantum communication, and quantum precision measurement.

[0062] In the prior art, signal generators often only support the generation of a single type of waveform signal, which is difficult to meet the various needs of actual production.

[0063] The technical solution of the present application is illustrated below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0064] Embodiment 1

[0065] Figure 1 This is a schematic diagram of the structure of the signal generator provided in the embodiment of the present application. Figure 1 As shown, the embodiment of the present application further provides a signal generator 1, comprising: a signal generating module 11, a register module 12 and an interface module 13,

[0066] The interface module 13 is connected to the register module 12 and the signal generating module 11, and is used to receive configuration information and original data outside the signal generator 1, transmit the configuration information to the register module 12, and transmit the original data to the signal generating module 11;

[0067] The register module 12 is connected to the signal generating module 11 and is used to store configuration information and provide configuration information to the signal generating module 11 .

[0068] The signal generating module 11 includes at least one signal generating unit 110 ; the signal generating unit 110 is used to perform pulse modulation and / or delay processing on the original data according to the original data and configuration information, and output a waveform signal corresponding to the original data.

[0069] In a specific implementation, external signals are received through an interface module and transmitted to a corresponding module, so that data transmission can be carried out in an orderly and reliable manner, which is beneficial to improving the efficiency of signal generation.

[0070] Exemplarily, the interface module 13 may receive data from an Advanced Peripheral Bus (APB) interface.

[0071] The register module 12 stores register data, which may specifically be configuration information, including but not limited to mode information, signal configuration information, preset delay time of the trigger signal generating module, etc. The register module 12 may transmit the configuration information to the signal generating module 11, thereby configuring the signal generating unit 110. The configuration information may include the format of the modulation signal, and the signal generating unit 110 may generate a modulation signal of a corresponding format according to the configuration information.

[0072] It is understandable that the pulse modulation type of at least one signal generating unit 110 can be different, so as to flexibly output multiple signals. Generating signals in parallel by multiple signal generating units can greatly improve the efficiency of signal generation, which is beneficial to the data transmission of the system.

[0073] In an embodiment of the present application, the signal generator includes: an interface module, a register module, a signal generating module and a storage module; the interface module is connected to the register module and the signal generating module, receives configuration information and original data outside the signal generator and transmits them to the register module and the signal generating module respectively; the register module is connected to the signal generating module, stores the configuration information and provides the configuration information to the signal generating module; the signal generating module includes at least one signal generating unit; the signal generating unit performs pulse modulation and / or delay processing on the original data according to the original data and the configuration information, and outputs a waveform signal corresponding to the original data, so that the signal generating unit can be controlled to output a custom type of waveform signal according to the original data by configuring the mode information, which can effectively improve the flexibility of signal generation.

[0074] Figure 2 This is a schematic diagram of the structure of the signal generating unit provided in the embodiment of the present application. Figure 2 As shown, the signal generating unit 110 provided in the embodiment of the present application may include: a trigger signal generating module 111, a pulse modulation module 112, and a delay interpolation module 113;

[0075] A trigger signal generating module 111, configured to receive a trigger signal and output an enable signal (also referred to as a pm_enable signal) according to the trigger signal;

[0076] The pulse modulation (PM) module 112 is connected to the trigger signal generating module 111 and receives the mode information and the original data. The pulse modulation module 112 is used to perform pulse modulation of the corresponding mode type on the original data after receiving the enabling signal according to the mode information to obtain a modulation signal corresponding to the original data; wherein the mode information includes the type of pulse modulation;

[0077] The delay interpolation module 113 is connected to the pulse modulation module 112 and is used to perform delay processing on the modulated signal to obtain a waveform signal corresponding to the original data.

[0078] In a specific implementation, after receiving the trigger signal, the trigger signal generating module 111 outputs an enable signal to the pulse modulation module 112, so that the pulse modulation module 112 starts to perform pulse modulation on the original data to obtain a modulation signal corresponding to the original data. Among them, the trigger signal can be an internal trigger signal trig_in0 or an external trigger signal trig_in1. The configuration information can also include a trigger mode of the signal generating unit 110, including internal triggering and external triggering. If the trigger signal generating module 111 is connected to other modules inside the signal generator 1 (such as a timer timer), the internal trigger signal trig_in0 is received; if the trigger signal generating module 111 is connected to an external device (such as a general purpose input and output port, General Purpose InputOutput, referred to as GPIO), the external trigger signal trig_in1 is received. If the trigger mode is external triggering, the signal generating unit 110 will start signal output after detecting the external trigger signal trig_in1. If the trigger mode is internal triggering, the signal output will start after the internal trigger bit is configured.

[0079] The pulse modulation module 112 can encode the original data into waveform width information and output a modulation signal with a variable duty cycle. When the original data is a string of binary digits, the modulation signal can be a sequence signal. The pulse modulation module 112 supports multiple types of pulse modulation, including but not limited to pulse density modulation (Pulse Density Modulation, referred to as PDM), pulse width modulation (Pulse Width Modulation, referred to as PWM), pulse frequency modulation (Pulse Frequency Modulation, referred to as PFM), pulse phase modulation (Pulse Phase Modulation, referred to as PPM), etc. In actual applications, the pulse modulation module 112 receives mode information, which represents the type of pulse modulation; the pulse modulation module 112 performs pulse modulation of the corresponding mode type on the original data according to the mode information. At any time, the type of pulse modulation represented by the mode information can only be one type, not multiple types; at different times, the type of pulse modulation represented by the mode information can be different, so that the working mode of the pulse modulation module 112 can be flexibly switched.

[0080] In the embodiment of the present application, the mode information can be configured to control the signal generating unit to output a custom type of pulse modulation signal according to the original data, which can effectively improve the flexibility of signal generation.

[0081] In a possible implementation, the trigger signal generating module 111 is specifically used for:

[0082] After receiving the trigger signal, the enable signal is output after a predetermined time delay.

[0083] In a specific implementation, the module receiving the output signal of the signal generating unit 110 may not be in an idle state, so the modulated signal needs to be delayed. The trigger signal generating module 111 can set the enable signal to be output after a preset time, so that the pulse modulation module 112 delays the output of the modulated signal after a preset time, thereby realizing the delay control of the modulated signal.

[0084] It is understandable that the delay accuracy of the trigger signal generating module 111 on the signal depends on the clock frequency used by the current system, so the delay of the signal by the trigger signal generating module 111 is a coarse adjustment. The delay of the signal can be further fine-tuned through the delay interpolation module.

[0085] like Figure 2 As shown, in a possible implementation, the signal generating unit 110 further includes: a delay interpolation module 113; the delay interpolation module 113 includes: a delay chain 113a and a selection module 113b;

[0086] The delay chain 113a is connected to the pulse modulation module 112 and is used to delay the modulation signal to obtain a delayed signal;

[0087] The selection module 113b is connected to the delay chain 113a, and is used to select and output a part of the delayed signal.

[0088] In a specific implementation, the delay chain 113a can delay the modulated signal by delay interpolation, and the delay accuracy of the delay chain 113a is determined by the time accuracy of the structure of the delay chain 113a itself, so that the delay of the modulated signal can be fine-tuned. Furthermore, the selection module 113b can select part of the output delayed signal, and can realize flexible configuration of the output signal without modifying the original data.

[0089] Figure 3 This is a schematic diagram of the structure of the delay interpolation module provided in the embodiment of the present application. Figure 3 As shown, in a possible implementation, the delay chain 113a includes: a plurality of delay units 1131 connected in series; the plurality of delay units 1131 are used to perform multi-stage delay on the modulated signal.

[0090] In a specific implementation, the delay chain 113a may include a plurality of delay units 1131 connected in series, and each delay unit 1131 delays a received signal, so that the delay chain 113a implements multi-stage delay of the modulated signal.

[0091] In a possible implementation, the delay unit 1131 includes an inverter.

[0092] Since there is a delay in the process from the input signal to the output signal of the inverter, the signal can be delayed by the inverter. The modulation signal is delayed by forming a delay chain through an inverter chain. The accuracy of the delay is determined by the delay time of the inverter. Therefore, it is not limited to the clock accuracy of the system, and the signal delay can be finely adjusted, so that it can be output flexibly and accurately.

[0093] Figure 4 Schematic diagram of the signal timing provided by the embodiment of the present application. Figure 3 and Figure 4 As shown, in a possible implementation, the selection module 113b includes a latch 1132, a pulse counter 1133 and a calculation module 1134;

[0094] The latch 1132 receives the start signal (start), the end signal (stop) and the delay signal (pm_out1), and is used to sample the delay signal when the rising edge of the start signal is detected, and stop sampling when the first rising edge of the delay signal is detected, to obtain a first signal segment (b_start); and, sample the delay signal when the rising edge of the end signal is detected, and stop sampling when the second rising edge of the delay signal is detected, to obtain a second signal segment (b_stop);

[0095] The pulse counter 1133 receives the start signal, the end signal and the delay signal, and is used to output a third signal segment (a_start) when the latch 1132 detects a first rising edge of the delay signal, and a fourth signal segment (a_stop) when the latch 1132 detects a second rising edge of the delay signal;

[0096] The calculation module 1134 is connected to the latch 1132 and the pulse counter 1133, and is used to calculate a partial signal (unit_out) in the delayed signal according to the first signal segment, the second signal segment, the third signal segment and the fourth signal segment; wherein the partial signal is the difference between the fourth signal segment and the second signal segment minus the difference between the third signal segment and the first signal segment.

[0097] In a specific implementation, the latch 1132 samples the delay signal when the rising edge of the start signal is detected, and stops sampling when the first rising edge of the delay signal is detected, to obtain a first signal segment (b_start); and samples the delay signal when the rising edge of the end signal is detected, and stops sampling when the second rising edge of the delay signal is detected, to obtain a second signal segment (b_stop). It can be understood that the first rising edge of the delay signal refers to the most recent rising edge of the delay signal after the rising edge of the start signal, and the second rising edge of the delay signal refers to the most recent rising edge of the delay signal after the rising edge of the end signal.

[0098] The modulation signal pm_out serves as a driving clock to control the counting operation of the pulse counter 1133 , which outputs a third signal segment (a_start) when the latch 1132 detects the first rising edge of the delay signal, and outputs a fourth signal segment (a_stop) when the latch 1132 detects the second rising edge of the delay signal.

[0099] The calculation module 1134 obtains the partial signal unit_out according to the output results of the latch 1132 and the pulse counter 1133 as follows: unit_out=(a_stop− b_stop)−(a_start− b_start).

[0100] In a possible implementation, the calculation module 1134 includes: a first calculation unit (Tstart), a second calculation unit (Tstop), and a third calculation unit (Unitout);

[0101] The first calculation unit is connected to the latch 1132 and the pulse counter 1133, and is used to receive the first signal segment and the third signal segment, and calculate the difference between the third signal segment and the first signal segment as the fifth signal segment;

[0102] The second calculation unit is connected to the latch 1132 and the pulse counter 1133, and is used to receive the second signal segment and the fourth signal segment, and calculate the difference between the fourth signal segment and the second signal segment as the sixth signal segment;

[0103] The third calculation unit is connected to the first calculation unit and the second calculation unit, and is used to calculate the difference between the sixth signal segment and the fifth signal segment to obtain a partial signal.

[0104] In a specific implementation, the first calculation unit calculates the fifth signal segment as a_start- b_start, the second calculation unit calculates the sixth signal segment as a_stop- b_stop, and the third calculation unit calculates the partial signal as (a_stop- b_stop)-(a_start- b_start).

[0105] In an embodiment of the present application, by selecting the corresponding partial signal from the delay signal according to the first signal segment, the second signal segment, the third signal segment and the fourth signal segment, the partial signal whose start time is the rising edge time of the start signal and whose end time is the rising edge time of the end signal can be accurately output, so that the output delay signal range can be customized through the start signal and the end signal, without the need to modify, add or delete the original data itself, and the output signal can be flexibly configured conveniently.

[0106] Figure 5This is a schematic diagram of the structure of another signal generating unit provided in an embodiment of the present application. Figure 5 As shown, in a possible implementation, the signal generating unit 1 further includes: a de-jitter module 114;

[0107] The de-jitter module 114 is connected to the delay interpolation module 113 and is used to detect whether the waveform signal has jitter, and if jitter has occurred, an interrupt signal is generated.

[0108] In a specific implementation, the signal generating unit 110 may be abnormal, resulting in jitter in the generated waveform signal. Therefore, a de-jitter module 114 may be provided at the output end of the delay interpolation module 113, and the de-jitter module 114 detects whether the signal unit_out output by the delay interpolation module 113 jitters. If jitter occurs, an interrupt signal is generated to stop the signal generating unit 110 from working.

[0109] It is understandable that the signal generating unit 110 may or may not be provided with a delay interpolation module 113. If the delay interpolation module 113 is not provided, the de-jitter module 114 may be connected to the output end of the signal modulation module 112 to detect whether the modulated signal pm_out output by the signal modulation module 112 has jitter.

[0110] In the embodiment of the present application, a de-jitter module is used to detect whether jitter exists in the signal output by the delay interpolation module, and an interrupt signal is generated when jitter occurs, so that the signal generating unit stops working in time, thereby effectively increasing the reliability of the system.

[0111] In a possible implementation, the de-jitter module 114 includes: a de-jitter circuit 1141 and an interrupt generation module 1142 . Figure 5 This is a schematic diagram of the structure of the de-jitter circuit provided in the embodiment of the present application. Figure 5 As shown, the de-jitter circuit 1141 includes: a single-pole double-throw switch K, a first resistor R1, a second resistor R2 and a NAND gate trigger;

[0112] The common end of the single-pole double-throw switch K is grounded, the first throw end (B end) of the single-pole double-throw switch K is connected to one end of the first resistor R1 and the set end (S end) of the NAND gate trigger, the second throw end (A end) of the single-pole double-throw switch K is connected to one end of the second resistor R2 and the reset end (R end) of the NAND gate trigger, and the other end of the first resistor R1 and the other end of the second resistor R2 receive the waveform signal;

[0113] The interrupt generation module 1142 is connected to the output terminal of the NAND gate trigger, and generates or does not generate an interrupt signal according to the signal value of the output terminal.

[0114] like Figure 2 and Figure 3As shown, in a possible implementation, the signal generating unit 110 further includes: a data buffer 115;

[0115] The data buffer 115 is connected to the pulse modulation module 112 and is used to receive and store the original data;

[0116] The pulse modulation module 112 is further configured to send a read enable signal (rd_en) to the data buffer 115 , and configure the read enable signal to be enabled when receiving an enable signal; and read original data from the data buffer 115 when the read enable signal is enabled.

[0117] In a specific implementation, the received raw data can be cached by the data buffer 115. The pulse modulation module 112 sends a read enable signal to the data buffer 115. When the read enable signal is not enabled, the data buffer 115 does not allow the pulse modulation module 112 to read the raw data. When the pulse modulation module 112 receives the enable signal, it configures the read enable signal to enable, reads the raw data from the data buffer 115, and generates a modulation signal according to the read raw data.

[0118] Exemplarily, the data buffer 115 may be a First Input First Output (FIFO) data buffer.

[0119] In the embodiment of the present application, by setting the data buffer 115 to cache the original data, the data transmission rate can be balanced, the data input and output rates can be matched, the signal delay and jitter can be reduced, and the reliability and stability of the system can be effectively improved.

[0120] In a possible implementation, the signal generating unit 110 further includes: a request module 116;

[0121] The request module 116 is connected to the data buffer 115 and is used to obtain the data amount of the data buffer 115. When the data amount is lower than a preset value, the request module 116 initiates a storage transfer request to a direct memory access (DMA) controller so that the DMA controller transfers the original data to the data buffer 115.

[0122] In a specific implementation, the request module 116 monitors the amount of data in the data buffer 115, and when the amount of data is lower than a preset value, initiates a storage transfer request to the DMA controller, so that the DMA controller directly transfers the original data to the data buffer 115. For example, assuming that the length of the modulated signal output by the signal modulation module 112 is defined as 100 lengths, the request module 116 initiates a DMA operation when the length of the data in the data buffer 115 is lower than 100.

[0123] Figure 7 This is a schematic diagram of the structure of another signal generator provided in an embodiment of the present application. Figure 7 As shown, the interface module 13 receives external received raw data, a buffer address, register data (Reg_data) and a register address (Reg_addr), transmits the raw data and the buffer address to the data buffer 115, and transmits the register data and the register address to the register 12, so that the data buffer 115 stores the raw data according to the buffer address, and the register 12 stores the register data according to the register address. When the data buffer 115 is a FIFO, the raw data received by the interface module 13 may be FIFO_data, and the buffer address may be FIFO_addr.

[0124] In actual applications, a write enable control module can be set in the signal generating module 11. The write enable module receives the buffer address sent by the interface module 13 and sends a write enable signal according to the operating status of the data buffer 115, so that the data buffer 115 writes the original data according to the buffer address when the write enable signal is enabled, thereby controlling the data buffer 115 to write data in an orderly and reliable manner.

[0125] In an embodiment of the present application, the data volume of the data buffer is monitored by the request module, and a DMA operation is automatically initiated when the data volume is lower than a preset value, so that the data in the data buffer is supplemented in time, effectively improving the reliability of the system; and, by supplementing the original data in the data buffer through the DMA operation, the occupancy of CPU resources can be reduced, and the overall operating speed of the system can be improved.

[0126] In a possible implementation, the configuration information also includes the frequency, length, phase, and number of repetitions of the signal; the pulse modulation module 112 is further used to:

[0127] Generate a corresponding modulation signal according to the configuration information.

[0128] In a specific implementation, when the pulse modulation module 112 performs pulse modulation, the frequency, length, phase and number of repetitions of the output modulation signal can be configured according to the configuration information, so that the signal generating unit 110 can flexibly generate various user-defined signals, greatly improving the flexibility of the system.

[0129] like Figure 7 As shown, in a possible implementation, the signal generator 1 further includes: a combining module 14;

[0130] The combining module 14 is used to combine the signals output by at least one signal generating unit 110 .

[0131] In a specific implementation, there is a situation where the signal to be generated is long. If only one signal generating unit 110 is used to generate the signal, the speed of signal generation is difficult to meet the requirements. Therefore, multiple signal generating units 110 can be used, each signal generating unit 110 generates a part of the signal, and the signals generated by multiple signal generating units 110 are spliced ​​through the combination module 14, so that a long signal can be generated quickly, which can not only improve the efficiency of signal generation, but also facilitate the data transmission and operation of the system, and also facilitate the load balancing of the signal generating unit 110.

[0132] In practical applications, such as Figure 1 and Figure 2 As shown, when the amount of data in the data buffer 115 is insufficient, the request module 116 initiates a storage transfer request to the DMA controller. The DMA controller moves the original data from the storage module 2 to the data buffer 115 according to the storage transfer request, so that the signal generating unit 110 can obtain the original data in the storage module 2 and generate a corresponding signal.

[0133] In a possible implementation, the register data also includes a channel enable signal, and the register module 12 is further used to:

[0134] Sending a channel enable signal to at least one signal generating unit 110 respectively;

[0135] The signal generating unit 110 is further configured to output a signal to the combining module 14 when the received channel enabling signal is enabled.

[0136] In a specific implementation, the register module 12 can send a channel enable signal to at least one signal generating unit 110 according to factors such as the length of the signal to be generated and whether each signal generating unit 110 is idle, so that the signal generating unit 110 enabled by the channel enable signal outputs a signal to the combination module 14, and the combination module 14 combines and outputs the received signals, so that some or all of the signal generating units 110 can be flexibly selected to jointly generate a signal. The signal generating unit 110 that is not enabled by the channel enable signal directly outputs the signal.

[0137] Taking the example that the signal generating module 11 includes 8 signal generating units 110 including unit0 . . . unit7 , the register module 12 can send channel enable signals to the 8 signal generating units 110 respectively, and flexibly configure the signal generating units 110 to collaboratively generate signals.

[0138] In the embodiment of the present application, a channel enable signal is sent to at least one signal generating unit 110 through the register module 12, and multiple signal generating units 110 are flexibly configured to jointly generate a long signal. This can not only improve the efficiency of signal generation, facilitate the data transmission and operation of the system, but also facilitate the load balancing of the signal generating units.

[0139] Figure 8 FIG. 1 is a schematic diagram of the structure of another signal generator provided in an embodiment of the present application. Figure 8 As shown, in a possible implementation, the signal generator 1 further includes: an interrupt module 15;

[0140] The interrupt module 15 is used to detect the number of signals output by at least one signal generating unit 110 within a predetermined time, and output an interrupt signal after the number of signals reaches a set upper limit.

[0141] In a specific implementation, the interrupt module 15 can detect the total number of signals output by at least one signal generating unit 110 within a predetermined time, and output an interrupt signal after the number of signals reaches a set upper limit value to stop the signal generator 1 from working; it can also detect the number of signals output by each signal generating unit 110 within a predetermined time, and output an interrupt signal after the number of signals reaches a set upper limit value to stop the signal generating unit 110 whose number of signals reaches the set upper limit value, thereby protecting the signal generator 1 and avoiding overload.

[0142] In practical applications, the upper limit value may also be set to no upper limit, and the signal generator 1 will continue to work until the system forcibly stops the signal generator 1, or the data buffer 115 is continuously empty, and the signal generator 1 will return an error message to the system.

[0143] In an embodiment of the present application, by setting an interrupt module, when the number of signals output by the signal generating unit reaches a set upper limit value, an interrupt signal can be automatically output to the system without relying on the system's active query, which can effectively protect the signal generator and improve the reliability of the system.

[0144] On the other hand, an embodiment of the present application provides a signal generating method. When the data amount of the signal transmitted by the interface module received by the signal generating module is less than a preset value, the preset data in the storage module is transmitted to the signal generating unit to realize automatic handling of the waveform generating data and form an output signal of a custom waveform; when the data amount of the signal transmitted by the interface module received by the signal generating module is greater than or equal to the preset value, the signal generating unit in the signal generating module performs delay adjustment on the signal transmitted by the interface module to obtain an output signal; the delay adjustment includes controlling the enable signal to delay a preset effective time to realize coarse delay control and / or realizing fine delay control through delay interpolation; transmitting configuration information to the signal generating module, the configuration information is stored in the register module, including a trigger mode; when the signal generating unit receives a trigger signal matching the trigger mode, the output signal is output.

[0145] Taking the generation of a specific PWM waveform as an example, first you need to configure the mode in the register to PWM, specify the period, sequence length, and phase information, assign the channel number, set the trigger mode, and set the delay length. If you need to use the high-precision delay control function, you need to calibrate the delay unit through IODELAYCTRL before configuring the delay length.

[0146] After completing the configuration, you can trigger the sequence signal generator according to the corresponding trigger mode. If the trigger mode is external trigger, the sequence signal output will start after the external trigger signal is detected. If the trigger mode is internal trigger, the sequence signal output will start after the internal trigger bit is configured.

[0147] For PWM, the data obtained from the FIFO is encoded as waveform width information, and a sequence signal with a variable duty cycle is output. When the amount of data in the FIFO is lower than a specific value, the sequence generator will automatically initiate a DMA operation to move the data from the system memory to the FIFO through DMA. When the amount of data in the FIFO is greater than or equal to a specific value, the signal generation unit in the sequence generator delays the signal transmitted by the interface module to obtain an output signal. The delay adjustment includes controlling the enable signal to delay the preset effective time to achieve coarse delay control and / or achieve fine delay control through delay interpolation.

[0148] When the sequence signal generator detects that the sequence signal output reaches the set upper limit, the sequence signal generator will stop working and return a signal to the system indicating that the work is completed. However, the upper limit can also be set to no upper limit, and the sequence signal generator will continue to work until the system forcibly stops the sequence signal generator or the FIFO is empty. At this time, the sequence signal generator will return an error message to the system.

[0149] The embodiment of the present application also provides an integrated circuit chip, which includes the signal generator as described above. It is understandable that the integrated circuit chip includes but is not limited to a control module, a digital signal processor (DSP), a field programmable gate array (FPGA), a microprocessor (MPU), a micro CPU, and other micro central control chips and system-on-chip chips that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions.

[0150] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0151] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A signal generator, characterized in that: include: Interface module, register module, signal generation module and storage module; The interface module is connected to the register module and the signal generating module, and is used to receive configuration information and original data outside the signal generator, transmit the configuration information to the register module, and transmit the original data to the signal generating module; The register module is connected to the signal generating module, and is used to store configuration information and provide the configuration information to the signal generating module; The signal generating module includes at least one signal generating unit; the signal generating unit is used to perform pulse modulation and / or delay processing on the original data according to the original data and the configuration information, and output a waveform signal corresponding to the original data.

2. The signal generator according to claim 1, characterized in that: include: Trigger signal generating module, pulse modulation module and delay interpolation module; The trigger signal generating module is used to receive a trigger signal and output an enabling signal according to the trigger signal; The pulse modulation module is connected to the trigger signal generating module and receives configuration information and original data. The pulse modulation module is used to, according to the configuration information, perform pulse modulation of a corresponding mode type on the original data after receiving the enabling signal to obtain a modulation signal corresponding to the original data; wherein the configuration information includes the type of pulse modulation; The delay interpolation module is connected to the pulse modulation module and is used to perform delay processing on the modulation signal to obtain a waveform signal corresponding to the original data.

3. The signal generator according to claim 2, characterized in that: The delay interpolation module includes: a delay chain and selection module; The delay chain is connected to the pulse modulation module and is used to delay the modulation signal to obtain a delayed signal; The selection module is connected to the delay chain and is used to select and output a part of the delayed signal.

4. The signal generator according to claim 3, characterized in that: The selection module receives a start signal and an end signal, the start time of the partial signal is the same as the rising edge time of the start signal, and the end time of the partial signal is the same as the rising edge time of the end signal.

5. The signal generator according to claim 4, characterized in that: The selection module includes a latch, a pulse counter and a calculation module; The latch receives a start signal, an end signal and the delay signal, and is used to sample the delay signal when a rising edge of the start signal is detected, and stop sampling when a first rising edge of the delay signal is detected, so as to obtain a first signal segment; and, sample the delay signal when a rising edge of the end signal is detected, and stop sampling when a second rising edge of the delay signal is detected, so as to obtain a second signal segment; The pulse counter is used to receive the start signal, the end signal and the delay signal, and is used to count the delay signal according to the start signal and the end signal when a first rising edge of the delay signal is detected to obtain a third signal segment and a fourth signal segment; The calculation module is connected to the latch and the pulse counter, and is used to calculate a partial signal in the delayed signal as the waveform signal based on the first signal segment, the second signal segment, the third signal segment and the fourth signal segment; wherein the partial signal is the difference between the fourth signal segment and the second signal segment minus the difference between the third signal segment and the first signal segment.

6. The signal generator according to claim 2, characterized in that: The signal generating unit further comprises: a de-jitter module; The de-jitter module is connected to the delay interpolation module and is used to detect whether jitter occurs in the waveform signal. If jitter occurs, an interrupt signal is generated.

7. The signal generator according to claim 2, characterized in that: The signal generating unit further includes: a data buffer; The data buffer is connected to the pulse modulation module and is used to receive and store original data; The pulse modulation module is further used to send a read enable signal to the data buffer, and configure the read enable signal to be enabled when the enable signal is received; and read original data from the data buffer when the read enable signal is enabled.

8. The signal generator according to claim 7, characterized in that: The signal generating unit further includes: a request module; The request module is connected to the data buffer and is used to obtain the data volume of the data buffer. When the data volume is lower than a preset value, a storage transfer request is initiated to a direct memory access controller so that the direct memory access controller transfers original data to the data buffer.

9. The signal generator according to claim 2, characterized in that: The configuration information also includes the frequency, length, phase and number of repetitions of the signal; the pulse modulation module is also used for: A corresponding modulation signal is generated according to the signal configuration information.

10. The signal generator according to claim 1, characterized in that: The signal generator further comprises: a combination module; The combining module is used to combine the signals output by the at least one signal generating unit.

11. The signal generator according to claim 10, characterized in that: The register data also includes a channel enable signal, and the register module is further used for: Sending a channel enable signal to the at least one signal generating unit respectively; The signal generating unit is further configured to output a signal to the combining module when the received channel enabling signal is enabled.

12. The signal generator according to any one of claims 1 to 11, characterized in that: The signal generator further comprises: an interrupt module; The interrupt module is used to detect the number of signals output by the at least one signal generating unit within a predetermined time, and output an interrupt signal after the number of signals reaches a set upper limit.

13. A signal generating method, characterized in that: include When the data volume of the signal transmitted by the interface module is less than the preset value, the signal generating module transmits the preset data in the storage module to the signal generating unit, realizes automatic handling of the waveform generating data, and forms an output signal of a custom waveform; When the data volume of the signal transmitted by the interface module received by the signal generating module is greater than or equal to a preset value, the signal generating unit in the signal generating module performs delay adjustment on the signal transmitted by the interface module to obtain an output signal; The delay adjustment includes controlling the enable signal to delay a preset effective time to achieve coarse delay control and / or achieving fine delay control by delay interpolation; Transmitting configuration information to the signal generation module, wherein the configuration information is stored in the register module, including the trigger mode; When the signal generating unit receives a trigger signal matching the trigger mode, it outputs the output signal.

14. An integrated circuit chip, characterized in that: Comprising the signal generator according to any one of claims 1-12.

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