Chip timing sequence processing method and chip
The timing configuration information and working mode information of chip application scenarios are obtained through the timing processor and the timing signals are output, which solves the problem of different requirements of different signal transceivers and receiver devices, and improves the flexibility and cost-effectiveness of chip output timing.
Patent Information
- Application Number
- CN202311037134.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-25
AI Technical Summary
There are differences in the input control timing and number of interfaces required for different types of signal transceivers and receivers, which leads to the fact that when the internal hardware logic of the chip is fully used to generate timing, it may not be able to meet the requirements of all device types, resulting in the output timing not meeting the requirements and causing losses.
The timing processor obtains the timing configuration information and working mode information of the chip's current application scenario from the central processor CPU, and outputs timing signals based on these information to achieve flexible timing adjustment.
It improves the flexibility of chip output timing, avoids the problem of timing not meeting the needs due to inadequate consideration of usage scenarios or changes in chip rear-level docking modules, and reduces development cycle and product costs.
Smart Images
Figure CN119514435A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of communications, and in particular, to a chip timing processing method and a chip. Background Art
[0002] As the application of application-specific integrated circuit (ASIC) chips becomes more and more widespread, the same chip is used in more and more scenarios. For chips that support multiple scenarios, have complex functions, and have long development cycles, it is often necessary to connect chips from different manufacturers and specifications to meet different product requirements in order to reduce costs.
[0003] For example, the digital intermediate frequency processing chips of the Radio Remote Unit (RRU) of the wireless communication system and the active indoor coverage solution Qcell product are used in different antenna / channel scenarios. In order to reduce product costs, they will be connected to signal transceiver devices with different manufacturers and total antenna numbers. However, different types of signal transceiver devices require different input control timings and numbers of interfaces. If the timing is generated entirely by the hardware logic inside the chip, there is a risk of incomplete consideration of the connected device types. Summary of the invention
[0004] The embodiments of the present invention provide a chip timing processing method and chip, so as to at least solve the problem that different types of signal transceiver devices in the related art require different input control timings and numbers of interfaces, and that completely using the hardware logic inside the chip to generate timings has the risk of incomplete consideration of the docking device type.
[0005] According to an embodiment of the present invention, a timing processing method of a chip is provided, comprising:
[0006] The timing processor obtains the timing configuration information and working mode information of the current application scenario of the chip from the central processing unit CPU; wherein the working mode information includes at least one working mode;
[0007] The timing processor outputs a timing signal according to the timing configuration information and the working mode information.
[0008] According to another embodiment of the present invention, a chip is provided, comprising: a timing processor and a central processing unit (CPU),
[0009] The timing processor is used to obtain the timing configuration information and working mode information of the current application scenario of the chip from the CPU; wherein the working mode information includes at least one working mode; and output a timing signal according to the timing configuration information and the working mode information.
[0010] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.
[0011] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
[0012] The embodiment of the present invention obtains the timing configuration information and working mode information of the current application scenario of the chip from the central processing unit CPU through the timing processor, and outputs the timing signal according to the timing configuration information and the working mode information, thereby avoiding the problem of chip output timing not meeting the requirements and causing losses due to inadequate consideration of the usage scenario during chip planning or changes in the chip's back-end docking module in the next few years. The output timing can be changed in real time according to the timing configuration information and the working mode information, which greatly improves the flexibility of the chip output timing, shortens the development cycle, and reduces product costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a hardware structure block diagram of a mobile terminal according to a timing processing method of a chip according to an embodiment of the present invention;
[0014] Figure 2 is a system architecture diagram according to an embodiment of the present invention;
[0015] Figure 3 is a flowchart of the steps of a timing processing method of a chip according to an embodiment of the present invention;
[0016] Figure 4 is a schematic diagram of a flow chart of timing signal output according to an embodiment of the present invention;
[0017] Figure 5 is a schematic diagram of the TX_EN timing of the output of modes 1 and 2 according to an embodiment of the present invention with a timing accuracy of the first-level time slice;
[0018] Figure 6 is a schematic diagram of the TX_EN timing of the output of mode 1 according to an embodiment of the present invention with a timing accuracy of the second-level time slice;
[0019] Figure 7 Schematic diagram of TX_EN timing with a timing accuracy of the output of mode 2 according to an embodiment of the present invention being a second-level time slice
[0020] Figure 8 is a structural block diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION
[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.
[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0023] In view of the differences in input control timing and number of interfaces required for different types of signal transceiver devices in related technologies, and the risk of incomplete consideration of docking device types when completely using the hardware logic inside the chip to generate timing, the technical concept of the embodiment of the present invention is that the timing processor processes the basic timing and outputs the timing signal according to the timing configuration information and working mode information of the current application scenario of the chip, thereby avoiding the problem of chip output timing not meeting the requirements and causing losses due to incomplete consideration of the usage scenario or changes in the chip's back-end docking module in the next few years during chip planning. The output timing can be changed in real time according to the timing configuration information and working mode information, which greatly improves the flexibility of the chip output timing, shortens the development cycle, and reduces product costs.
[0024] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 1 is a hardware structure block diagram of a mobile terminal according to a timing processing method of a chip according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.
[0025] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the timing processing method of the chip in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.
[0026] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.
[0027] Figure 2 is a system architecture diagram according to an embodiment of the present invention. The embodiment of the present application can be run on Figure 2 In the network architecture shown in Figure 2 As shown, the system architecture includes: a main control central processing unit (CPU), a basic information module, an event trigger module, a timing processor, a hardware processing module, and a timing mapping module, wherein the functions of each module are as follows:
[0028] Main control CPU: The central controller of the system. It is used to complete the parameter configuration of the entire system, the configuration of basic timing data, the initialization of the timing processor, and the download of program instructions. During system operation, the main control CPU can also update the timing data online.
[0029] Basic information module: It is composed of several basic information modules and is used to store all basic timing information required for output timing signals.
[0030] Event trigger module: It is used to send an interrupt signal to the timing processor at a specific time (such as a periodic synchronization signal) or when an event that cannot be predicted in advance (such as an alarm) occurs according to the output timing requirements of the chip, so as to interrupt the current timing processing of the timing processor and generate a new timing.
[0031] Timing processor: A simplified processor core that supports software programmability. It can implement basic Reduced Instruction Set Computer (RISC) instructions such as data loading (load), data storage (store), data comparison (compare, cmp), branch jump (jump), and wait (wait) through control programs (such as assembly instructions), and can respond to interrupt signals sent by event trigger modules. In normal operation, the timing processor can execute program instructions downloaded in advance, and generate flexible and variable timing under different conditions and time periods based on basic timing data. For timing that is relatively simple, or periodic and has no special requirements, the timing information can also be directly stored, and directly read and output according to certain rules.
[0032] Hardware processing module: used to use the underlying hardware to perform secondary processing on the timing generated by the timing processor to eliminate timing jitter and improve timing accuracy. For example, align the timing output by the timing processor to a certain point in time, or align or differ the timing outputs of several timing processors by a fixed number of clock cycles to meet the requirements of the subsequent timing. The hardware processing module is suitable for scenarios with high requirements for output timing accuracy. When the requirements for output timing accuracy are not high, such as the clock timing of the serial inter-integrated circuit (I2C), a strictly fixed clock cycle is not required, and the hardware timing processing module may not be required when generating the clock.
[0033] Timing mapping module: used to complete the mapping of output timing signals to output pins, making the timing of chip output pins more flexible. For example, in a certain scenario, when the input pins of the selected subsequent chip change, we can use the redundant pins of the previous chip to generate and output timing to the subsequent stage. The timing mapping module can meet more flexible output timing requirements.
[0034] In the embodiment of the present invention, the main control CPU, basic information module, timing processor, event trigger module and other hardware and software can jointly complete the flexible output of timing signals.
[0035] In this embodiment, a timing processing method for a chip running on the above system architecture diagram is provided. Figure 3 is a flowchart of the timing processing method of a chip according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:
[0036] Step S301, the timing processor obtains the timing configuration information and working mode information of the current application scenario of the chip from the central processing unit CPU; wherein the working mode information includes at least one working mode.
[0037] In an embodiment of the present invention, the timing processor may obtain timing configuration information and working mode information of the current application scenario of the chip from the main control CPU, wherein the working mode information may include one working mode or multiple working modes.
[0038] In an optional embodiment, before obtaining the timing configuration information and working mode information of the current application scenario of the chip, it also includes: analyzing the current application scenario of the chip to obtain the timing information and the working mode information required to be output by the chip, and configuring the timing information for the chip to obtain the timing configuration information.
[0039] As an example, the main control CPU can analyze one or more timings that the chip needs to output according to the current application scenario of the chip, obtain one or more working mode information that affects the output timing signal, as well as the timing information under each working mode, and configure the timing information for the chip to obtain timing configuration information.
[0040] Step S302: the timing processor outputs a timing signal according to the timing configuration information and the working mode information.
[0041] In the embodiment of the present invention, the timing processor can flexibly output the timing signal according to the timing configuration information and the working mode information.
[0042] As an example, the timing processor can read the basic timing information in the timing configuration information starting from the moment a certain trigger event occurs according to the chip output timing requirements, and output the timing signal according to the corresponding working mode.
[0043] In an optional embodiment, during the process of outputting the timing signal, the timing processor interrupts the current working mode and switches to the next working mode when receiving an interrupt signal sent by the CPU.
[0044] As an example, during the process of outputting a timing signal, when an interrupt signal sent by the main control CPU is received, the timing processor can interrupt the output of the current timing signal and switch to the next working mode, and output the timing signal according to the timing information corresponding to the next working mode.
[0045] In an optional embodiment, the working mode is a combination of different time slices, and the timing processor interrupts the current working mode and switches to the next working mode, including: the timing processor interrupts the current working mode and switches to the next working mode in the next time slice of the current working mode time slice.
[0046] In the embodiment of the present invention, the working mode information may include one or more working modes. The working modes are combinations of different time slices, and different working modes have different combinations of time slices.
[0047] As an example, when an interrupt signal is received, the timing processor may first complete the output of the time slice timing of the current working mode, and then switch to the next working mode in the next time slice of the current working mode.
[0048] As an example, the interrupt signal and the working mode can be set to correspond one to one. The timing processor can switch to the working mode corresponding to the interrupt signal in the next time slice of the current working mode time slice according to the interrupt signal and the corresponding relationship between the interrupt signal and the working mode.
[0049] In an optional embodiment, if the timing processor does not receive the interrupt signal during the process of outputting the timing signal, it sends a query request to the CPU after a preset cycle of outputting the timing signal to inquire whether the current working mode has changed; if the current working mode has changed, the timing processor switches to the changed working mode.
[0050] As an example, in the process of outputting the timing signal, if the timing processor does not receive an interrupt signal, it can send a query request to the CPU after outputting the timing signal of the current working mode for a preset cycle to inquire whether the current working mode has changed.
[0051] As an example, if the working mode changes, for example, when the chip updates the application scenario, the CPU can analyze the new application scenario of the chip to obtain the new timing information and new working mode information that the chip needs to output. The timing processor can then obtain the new working mode and switch to the new working mode.
[0052] As an example, the CPU may configure new timing information for the chip to obtain new timing configuration information.
[0053] In an optional embodiment, the timing processor outputs a timing signal according to the timing configuration information and the working mode information, including: the timing processor obtains the timing information corresponding to the changed working mode, and outputs the timing signal according to the timing information corresponding to the changed working mode and the changed working mode.
[0054] As an example, the timing processor may obtain the timing information corresponding to the changed working mode from the current timing configuration information, and output the changed timing signal according to the timing information corresponding to the changed working mode and the changed working mode.
[0055] In an optional embodiment, after outputting the timing signal corresponding to the working mode, the method further includes: the CPU mapping the output timing signal to an output pin.
[0056] As an example, according to the application scenario of the chip, the main CPU can map the output timing signal to the output pin, so that the output timing of the chip pin is more flexible. Therefore, when the output timing needs to be changed online, the main CPU can change the timing configuration information online to enable the timing processor to output the changed timing signal according to the changed timing configuration information.
[0057] In the embodiment of the present invention, the timing processor obtains the timing configuration information and working mode information of the current application scenario of the chip from the central processing unit CPU, and outputs the timing signal according to the timing configuration information and the working mode information, thereby avoiding the problem of chip output timing not meeting the requirements and causing losses due to inadequate consideration of the usage scenario during chip planning or changes in the chip's back-end docking module in the next few years. The output timing can be changed in real time according to the timing configuration information and the working mode information, which greatly improves the flexibility of the chip output timing, shortens the development cycle, and reduces product costs.
[0058] In order to facilitate those skilled in the art to better understand the present invention, the present invention is further described below by an example:
[0059] Example 1:
[0060] When the digital intermediate frequency chip is connected to the signal transceiver device at the subsequent stage, the output (TransmitEnable, TX_EN) of the enable signal timing signal to the subsequent signal transceiver device is taken as an example to illustrate the output process of the timing signal. Figure 4 is a flow chart of timing signal output according to an embodiment of the present invention, referring to Figure 4 , the process is implemented through the following steps:
[0061] S400, initialization. The main control CPU initializes the timing processor; after initialization, the timing processor can wait for the main control CPU to download the timing control instruction.
[0062] S401, analyzing the output timing generation mechanism. According to the current application scenario, the main control CPU can analyze several timings that the chip needs to output, obtain several working modes that affect the output timing, and analyze and extract the timing information under the several working modes.
[0063] Figure 5 1 is a schematic diagram of the TX_EN timing of the output of modes 1 and 2 according to an embodiment of the present invention with a timing accuracy of the first-level time slice. Assuming that the timing of the TXEN output in the current application scenario of the chip is as follows: Figure 5 As shown, the output timing is cycled according to M level 1 time slices, each level 1 time slice is divided into N level 2 time slices, M and N are positive integers, and M and N can be set according to the current application scenario of the chip. This example does not limit the length of the level 1 time slice or the level 2 time slice.
[0064] In addition, the output timing is different in different working modes. The main control CPU sends the mode switching signal to the timing processor according to the application scenario. After the timing processor receives the mode switching signal from the main control CPU, according to the needs of the subsequent chip, the timing processor can respond to the mode switch at a specific position of the next level 1 or 2 time slice of the current working mode and generate timing.
[0065] In mode 1 and 2, the output timing is as follows:
[0066] Mode 1:
[0067] In the 1st level time slice 1 to (R-1), all the 2nd level time slices output the timing constant 1 signal;
[0068] In the 1st level time slice R, in the 2nd level time slice 1~(S1-1), the output timing is always 1 signal;
[0069] In the 2-level time slice S1, a 1 (duration t1) signal is output first, and then a 0 (duration t2) signal is output, where t1+t2 is equal to the length of one 2-level time slice;
[0070] In the 2nd level time slice (S1+1)~N, the output is always 0 signal;
[0071] In the 1st level time slice (R+1)~M, all the 2nd level time slices output a constant 0 signal.
[0072] Mode 2:
[0073] In the 1st level time slice 1 to (R-1), all the 2nd level time slices output a constant 1 signal;
[0074] In the 1st level time slice R, in the 2nd level time slice 1~(S2-1), the output timing is always 1 signal;
[0075] In the second-level time slice S2, a 1 (duration t3) signal is output first, and then a 0 (duration t4) signal is output, where t3+t4 is equal to the length of one second-level time slice;
[0076] In the 2nd level time slice (S2+1)~N, the output is always 0 signal;
[0077] In the 1st level time slice (R+1)~M, all the 2nd level time slices output a constant 0 signal.
[0078] S402, the user writes and downloads program instructions. The user can analyze the software and hardware interaction process according to the timing generation principle in various working modes and the switching mechanism between modes, write the program instructions of the timing processor, and download them to the timing processor.
[0079] For example, the software code of the timing processor can be composed of three segments: the main program code segment, the timing generation code segment of mode 1, and the timing generation code segment of mode 2. The main program can determine whether the working mode has changed by querying the working mode from the main control CPU, or interrupt the current working mode by receiving the interrupt signal of the main control CPU, complete the interaction with the main control CPU, and complete the program jump according to the latest working mode. The main program can also output the timing generation code segment of the next mode when receiving an external interrupt (such as a timer interrupt of a time slice cycle), and cyclically output the timing information of TX_EN under each 2-level time slice. The main program can respond to queries or interrupts and update the mode after the main control CPU sends the instruction.
[0080] Figure 6 is a schematic diagram of the TX_EN timing of the output of mode 1 according to an embodiment of the present invention with a timing accuracy of the second-level time slice, Figure 7 1 is a schematic diagram of the TX_EN timing of the output of mode 2 according to an embodiment of the present invention with a timing accuracy of the second-level time slice, such as Figure 6 , Figure 7 As shown, the timing corresponding to each level 2 time slice can be regarded as a timing generation instruction. A maximum of M*N instructions are required to represent the timing generation of one large cycle. The number of repetitions can also be increased by the instruction content to reduce the number of instructions.
[0081] According to the timing description of step S401, according to the order of the level 2 time slice under the level 1 time slice, taking mode 1 as an example, M*N instructions can be generated in sequence:
[0082] 1~(R-1): Output (R-1)*N instructions representing constant 1;
[0083] R: Output S1-1 indicates instructions that are always 1, 1 indicates instructions that are 1 (duration t1)->0 (duration t2), and N-S1 indicates instructions that are always 0;
[0084] (R+1)~(M-1): Output (MR-1)*N instructions representing constant 0;
[0085] M: Output N-2 instructions indicating constant 0, 1 instruction indicating 0 (duration t3)->1 (duration t4), and 1 instruction indicating constant 1;
[0086] In mode 2, the instruction generation method is the same as that in mode 1, and this example will not be repeated here.
[0087] S403, the main control CPU configures basic timing information. After extracting the basic timing information, the main control CPU can configure the chip with the necessary basic data for generating timing. The basic timing data can be stored in the basic information module.
[0088] For example, after determining the application scenario of the chip, the basic timing can be determined as the timing under the 2-level time slice: there are 6 types in total: always 1, always 0, 1 (duration t1) -> 0 (duration t2), 0 (duration t3) -> 1 (duration t4), 1 (duration t5) -> 0 (duration t6), 0 (duration t7) -> 1 (duration t8).
[0089] S404, the timing processor outputs a timing signal. According to the chip output timing requirements, the timing processor can read the basic timing information from the moment a certain trigger event occurs, process it, and output the timing according to a certain rule. During the output process, if the preset interrupt trigger event is met, the timing output of the current mode of interruption can be triggered. After the interruption, different timing signals are output according to the new mode.
[0090] For example, after a delay from the start of the first level time slice, an external interrupt is generated to notify the timing processor to output timing according to a new mode. According to steps S401 and S402, starting from the first level 1 time slice, the timing signals of the level 2 time slices under each level 1 time slice are output in sequence.
[0091] S405, hardware processing timing. If the timing accuracy of the timing processor output cannot meet the system requirements, such as the strict clock alignment relationship or the difference of several clock cycles between multiple output signals, in this scenario, the output signal can be processed by hardware synchronization to generate a timing with a clock cycle accuracy.
[0092] For example, each time the timing processor responds to the timing interrupt of the level 1 time slice, there may be jitter of several clock cycles, so the timing generated based on the interrupt will also jitter. In this case, the timing can be synchronized through the cycle header of the level 1 time slice, thereby eliminating the timing offset caused by the jitter of the interrupt response of the timing processor and improving the timing accuracy to 1 clock cycle.
[0093] S406, the main control CPU maps the output timing signal to the pin IO: the main control CPU can map the output timing to the output pin according to the application scenario, so that the output timing signal of the chip pin is more flexible; when outputting the timing signal, if the timing needs to be changed online, the main control CPU can change the basic timing information online, and the timing processor can generate the changed timing.
[0094] The implementation method of this example improves the flexibility of chip output timing, solves the disadvantage that the hardware-generated timing cannot be changed arbitrarily during chip use, improves the chip usage scenarios, reduces the chip development cycle and development costs, and also reduces product costs.
[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.
[0096] In this embodiment, a chip is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.
[0097] Figure 8 is a block diagram of a chip according to an embodiment of the present invention. Figure 8 As shown, the chip 80 includes a timing processor 801 and a central processing unit CPU 802.
[0098] The timing processor 801 is used to obtain the timing configuration information and working mode information of the current application scenario of the chip from the CPU 802; wherein the working mode information includes at least one working mode; and output a timing signal according to the timing configuration information and the working mode information.
[0099] In an optional embodiment, the timing processor is used to interrupt the current working mode and switch to the next working mode when receiving an interrupt signal sent by the CPU during the process of outputting the timing signal.
[0100] In an optional embodiment, the working mode is a combination of different time slices.
[0101] The timing processor is used to interrupt the current working mode and switch to the next working mode in the next time slice of the current working mode time slice.
[0102] In an optional embodiment, the timing processor is also used to send a query request to the CPU after a preset cycle of outputting the timing signal if the interrupt signal is not received during the process of outputting the timing signal, so as to inquire whether the current working mode has changed; if the current working mode has changed, switch to the changed working mode.
[0103] In an optional embodiment, the timing processor is used to obtain timing information corresponding to the changed working mode, and output a timing signal according to the timing information corresponding to the changed working mode and the changed working mode.
[0104] In an optional embodiment, the CPU is used to analyze the current application scenario of the chip before acquiring the timing configuration information and working mode information of the current application scenario of the chip, obtain the timing information and the working mode information required to be output by the chip, and configure the timing information for the chip to obtain the timing configuration information.
[0105] In an optional embodiment, the CPU is further configured to map the output timing signal to an output pin after outputting the timing signal corresponding to the working mode.
[0106] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.
[0107] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
[0108] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.
[0109] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
[0110] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.
[0111] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.
[0112] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.
[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A timing processing method for a chip, characterized in that: include: The timing processor obtains the timing configuration information and working mode information of the current application scenario of the chip from the central processing unit CPU; wherein the working mode information includes at least one working mode; The timing processor outputs a timing signal according to the timing configuration information and the working mode information.
2. The method according to claim 1, characterized in that Also includes: In the process of outputting the timing signal, the timing processor interrupts the current working mode and switches to the next working mode when receiving the interrupt signal sent by the CPU.
3. The method according to claim 2, characterized in that The working mode is a combination of different time slices, and the timing processor interrupts the current working mode and switches to the next working mode, including: The timing processor interrupts the current working mode and switches to the next working mode in the next time slice of the current working mode time slice.
4. The method according to claim 2, characterized in that: Also includes: If the timing processor does not receive the interrupt signal during the process of outputting the timing signal, then after a preset cycle of outputting the timing signal, a query request is sent to the CPU to query whether the current working mode has changed; When the current working mode changes, the timing processor switches to the changed working mode.
5. The method according to claim 4, characterized in that The timing processor outputs a timing signal according to the timing configuration information and the working mode information, including: The timing processor obtains timing information corresponding to the changed working mode, and outputs a timing signal according to the timing information corresponding to the changed working mode and the changed working mode.
6. The method according to claim 1, characterized in that Before obtaining the timing configuration information and working mode information of the current application scenario of the chip, it also includes: The CPU analyzes the current application scenario of the chip to obtain the timing information and the working mode information required to be output by the chip, and configures the timing information for the chip to obtain the timing configuration information.
7. The method according to claim 1, characterized in that After outputting the timing signal corresponding to the working mode, it also includes: The CPU maps the output timing signal to the output pin.
8. A chip, characterized in that: include: Timing processor and central processing unit CPU, The timing processor is used to obtain the timing configuration information and working mode information of the current application scenario of the chip from the CPU; wherein the working mode information includes at least one working mode; and output a timing signal according to the timing configuration information and the working mode information.
9. The chip according to claim 8, characterized in that: The timing processor is used to interrupt the current working mode and switch to the next working mode when receiving an interrupt signal sent by the CPU during the process of outputting the timing signal.
10. The chip according to claim 9, characterized in that: The working mode is a combination of different time slices. The timing processor is used to interrupt the current working mode and switch to the next working mode in the next time slice of the current working mode time slice.
11. The chip according to claim 9, characterized in that: The timing processor is further configured to send a query request to the CPU after a preset cycle of outputting the timing signal if the interrupt signal is not received during the process of outputting the timing signal, so as to query whether the current working mode has changed; When the current working mode changes, switch to the changed working mode.
12. The chip according to claim 11, characterized in that: The timing processor is used to obtain timing information corresponding to the changed working mode, and output a timing signal according to the timing information corresponding to the changed working mode and the changed working mode.
13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.
14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.