Method and system for extracting parameters of small-signal equivalent circuit

Abstract

The embodiment of the invention discloses a parameter extraction method and system for a small-signal equivalent circuit. The method comprises the following steps: removing parasitic capacitance and parasitic inductance of a test structure of a to-be-tested device by using an open-short circuit test structure; calculating and stripping electrode resistance by using an open set test method; calculating an intrinsic scattering parameter according to the parasitic capacitance, the parasitic inductance, the electrode resistance and the scattering parameter; and extracting intrinsic parameters of the small-signal equivalent circuit model by using a particle swarm optimization algorithm according to the intrinsic scattering parameters. The problems of low parameter extraction speed, inaccurate parameter extraction result and inaccurate fitting at high frequency in the extraction process in the prior art are solved, and the extraction efficiency and precision of the small-signal equivalent circuit model parameters are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic devices, and in particular to a parameter extraction method and system for a small signal equivalent circuit. Background Art

[0002] The HBT (Heterojunction Bipolar Transistor) device is a heterojunction bipolar transistor composed of two or more semiconductor materials. It uses a heterostructure of narrow bandgap materials and wide bandgap materials, and has the characteristics of high frequency, high power and low noise. HBT devices operate in the RF and microwave frequency ranges and are widely used in high-frequency circuits such as power amplifiers, mixers and oscillators in wireless communication systems. Due to its excellent high-speed operation capability, high power handling capability and low noise characteristics, HBT devices achieve high-efficiency power amplification and driving, and play a key role in applications such as low-noise amplifiers and receiver preamplifiers. In general, HBT devices are an important electronic component with the advantages of heterogeneous structure, high frequency, high power and low noise, and are widely used in modern electronic devices.

[0003] Modeling of HBT devices is very important for designing and optimizing device performance. It can help engineers understand the physical behavior and characteristics of the device and perform simulation analysis to guide the design and manufacturing process of the device. Through modeling, device performance can be predicted, structural parameters can be optimized, device efficiency and reliability can be improved, and product development cycle can be accelerated.

[0004] At present, many extraction techniques have been reported and applied to HBT devices. There are two main methods, including direct extraction and algorithm optimization. The direct extraction method establishes physical formulas and performs analytical calculations on the embedded measurement data. The parameters of each component in the small signal model are obtained without the need for additional information or manual parameter settings. However, the direct extraction method is easily affected by measurement errors and usually requires manual adjustment to improve accuracy. The optimization-based method dynamically adjusts the value of each parameter through an iterative optimization algorithm to minimize the difference between the measured data and the simulated data. This may lead to results that lack physical meaning or inaccurate extraction due to falling into a local optimal solution, and the algorithm is sensitive to the initialization parameters. Summary of the invention

[0005] To this end, an embodiment of the present application provides a method and system for extracting parameters of a small signal equivalent circuit, which solves the problems of slow parameter extraction speed, inaccurate parameter extraction results, and inaccurate fitting at high frequencies in the prior art, and improves the parameter extraction efficiency and accuracy of the small signal model.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] According to a first aspect of an embodiment of the present application, a method for extracting parameters of a small signal equivalent circuit is provided, which is applicable to a small signal equivalent circuit model, and the method includes:

[0008] Use open-short structure to remove parasitic capacitance and parasitic inductance of the test structure of the device under test;

[0009] Calculate and strip the electrode resistance using the open collector test method;

[0010] Calculating intrinsic scattering parameters according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters;

[0011] According to the intrinsic scattering parameters, a particle swarm optimization algorithm is used to extract the intrinsic parameters of the small signal equivalent circuit model.

[0012] Optionally, according to the intrinsic scattering parameters, using a particle swarm optimization algorithm to extract the intrinsic parameters of the small signal equivalent circuit model includes:

[0013] Use the particle swarm optimization algorithm to initialize the position and speed, inertia weight and learning factor of the particle population, establish the objective function and iterative adjustment mechanism, and calculate the next position based on the current position of the particle swarm and the global optimal position;

[0014] All particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

[0015] Optionally, the traversing of all particles, whereby the particles continuously update their positions to approach an ideal solution, includes:

[0016] The error function characterizing the error between the scattering parameters and the intrinsic scattering parameters is used as the fitting target of the particle swarm optimization algorithm;

[0017] Determine the fitting error of each particle according to the error function, take the fitting error of a single particle as the individual optimal position of the single particle, and take the minimum value of the fitting errors of all particles as the global optimal position;

[0018] All particles are traversed, and after the individual optimal position and global optimal position of a single particle are updated each time, the updated position and velocity of the particle are input into the small signal equivalent circuit model again.

[0019] Optionally, the small signal equivalent circuit model includes parasitic elements and intrinsic elements;

[0020] Parasitic components include base emitter parasitic capacitance C pbe , base collector parasitic capacitance C pbc, collector emitter capacitance C pbe , base parasitic inductance L b , emitter parasitic inductance L e , collector parasitic inductance L c , electrode parasitic resistance, base resistance R b , emitter resistance R e , Collector resistance R c ;

[0021] The intrinsic components include the base internal resistance R bi , base emitter capacitance C be , base emitter resistance R be , base collector capacitance C bc , base collector resistance R bc , base collector distributed capacitance C bcx , and the current-controlled current source CCCS, the common base current transfer coefficient α0 under DC conditions, and the base region transit time τ B , collector region transit time τ C ;

[0022] Base emitter parasitic capacitance C pbe Connecting the base external node and the emitter external node; base collector parasitic capacitance C pbc Connect the base external node and the collector external node; collector emitter parasitic capacitance C pbe Connecting the collector external node and the emitter external node; base parasitic inductance L b and base resistor R b After series connection, the base external node and the base internal node are connected; the emitter parasitic inductance L e and emitter resistor R e After series connection, the emitter external node and the emitter internal node are connected; the collector parasitic inductance L c and collector resistor R c After connecting in series, the collector external node and the collector internal node are connected; the base collector distributed capacitance C bcx Connect the base internal node and the collector internal node; the base internal resistor R bi Connect the base internal node and the base intrinsic node; base emitter capacitor C be and the base emitter resistor R be After parallel connection, the emitter internal node and the base intrinsic node are connected; the base collector capacitor C bc , base collector resistance R be The collector internal node and the base intrinsic node are connected in parallel with the current controlled current source CCCS.

[0023] Optionally, the removing parasitic capacitance and parasitic inductance of the test structure of the device under test by using an open-short structure includes:

[0024] Testing the scattering parameter S of the open circuit de-embedded structure of the small signal equivalent circuit model device O , the scattering parameter S O Converted into admittance parameter Y S , according to the admittance parameter Y S Get the base emitter parasitic capacitance C pbe , base collector parasitic capacitance C pbc and collector emitter capacitance C pbe ;

[0025] Testing the scattering parameter S of the short-circuit de-embedding structure of the small signal equivalent circuit model device S , the scattering parameter S S Transformation group impedance parameter Z S , according to the impedance parameter Z S Get the base parasitic inductance L b , emitter parasitic inductance L e and collector parasitic inductance L c .

[0026] Optionally, calculating the intrinsic scattering parameter according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameter includes:

[0027] The complete scattering parameters are measured at the bias point to be extracted according to the small signal equivalent circuit model, and the parasitic capacitance and parasitic inductance are stripped off by addition and subtraction operations and parameter changes to obtain the intrinsic scattering parameters.

[0028] According to a second aspect of an embodiment of the present application, a parameter extraction system for a small signal equivalent circuit is provided, which is applicable to a small signal equivalent circuit model, and the system includes:

[0029] A parasitic parameter extraction module for removing parasitic capacitance and parasitic inductance of a test structure of a device under test using an open-short structure;

[0030] Resistance stripping module, used to calculate and strip electrode resistance using the open collector test method;

[0031] An intrinsic scattering parameter module, used to calculate intrinsic scattering parameters according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters;

[0032] A parameter extraction module is used to extract the intrinsic parameters of the small signal equivalent circuit model using a particle swarm optimization algorithm according to the intrinsic scattering parameters.

[0033] Optionally, the parameter extraction module is specifically used to:

[0034] Use the particle swarm optimization algorithm to initialize the particle population, inertia weight and learning factor, establish the objective function and iterative adjustment mechanism, and calculate the next position based on the current position of the particle swarm and the global optimal position;

[0035] All particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

[0036] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect above.

[0037] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. The computer-readable instructions can be executed by a processor to implement the method described in the first aspect above.

[0038] In summary, the embodiment of the present application provides a method and system for extracting parameters of a small signal equivalent circuit, which removes the parasitic capacitance and parasitic inductance of the test structure of the device under test by using an open short circuit test structure; uses an open set test method to calculate and strip the electrode resistance; calculates the intrinsic scattering parameters based on the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters; and uses a particle swarm optimization algorithm to extract the intrinsic parameters of the small signal equivalent circuit model based on the intrinsic scattering parameters. The method solves the problems of slow parameter extraction speed, inaccurate parameter extraction results, and inaccurate fitting at high frequencies in the prior art, and improves the parameter extraction efficiency and accuracy of the small signal equivalent circuit model. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the implementation methods of the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings described below are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0040] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the embodiments of the present application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the embodiments of the present application, should still fall within the scope of the technical contents disclosed in the embodiments of the present application.

[0041] Figure 1 A schematic flow chart of a method for extracting parameters of a small signal equivalent circuit provided in an embodiment of the present application;

[0042] Figure 2 A structural diagram of the HBT small signal equivalent circuit topology provided in an embodiment of the present application;

[0043] Figure 3 A flow chart of a parameter extraction method for an HBT small signal model provided in an embodiment of the present application;

[0044] Figure 4 An equivalent circuit diagram of an open circuit de-embedding structure provided in an embodiment of the present application;

[0045] Figure 5 An equivalent circuit diagram of the short-circuit de-embedding structure provided in an embodiment of the present application;

[0046] Figure 6 The equivalent circuit diagram under the open collector condition provided in the embodiment of the present application;

[0047] Figure 7 The intrinsic equivalent circuit diagram provided by the embodiment of the present application;

[0048] Figure 8 The optimal convergence curve and the average convergence curve when the algorithm provided in the embodiment of the present application is run 20 times;

[0049] Fig. 9 A comparison chart of the actual test results provided in the embodiment of the present application and the S parameters extracted from the small signal model results;

[0050] Fig.10 A parameter extraction system block diagram of a small signal equivalent circuit provided in an embodiment of the present application;

[0051] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown;

[0052] Fig.12 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0053] The following is a specific embodiment to illustrate the implementation of the embodiment of the present application. People familiar with this technology can easily understand other advantages and functions of the embodiment of the present application from the content disclosed in this specification. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the embodiments in the embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiment of the present application.

[0054] Particle Swarm Optimization (PSO) is a heuristic optimization algorithm inspired by the foraging behavior of bird flocks. PSO finds the optimal solution by simulating the search and collaboration of particles in space. Each particle represents a potential solution to the problem, and gradually searches for the optimal solution through iterative updates of position and velocity. The Particle Swarm Optimization algorithm is simple and easy to implement, does not require derivative information, and is applicable to continuous and discrete optimization problems. It has global search capabilities and multi-peak optimization capabilities, and is widely used in many fields such as engineering optimization, machine learning, and data mining. The use of this algorithm can significantly improve the efficiency and accuracy of parameter extraction.

[0055] HBT is a three-port device that can be biased at many different voltages. The small signal equivalent circuit model fits the electrical performance of the device under a fixed bias.

[0056] Figure 1 A method for extracting parameters of a small signal equivalent circuit provided in an embodiment of the present application is shown, which is applicable to a small signal equivalent circuit model, and the method includes:

[0057] Step 101: using an open-short circuit test structure to remove parasitic capacitance and parasitic inductance of a test structure of a device under test;

[0058] Step 102: Calculate and strip the electrode resistance using an open collector test method;

[0059] Step 103: Calculating intrinsic scattering parameters according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters;

[0060] Step 104: extracting intrinsic parameters of the small signal equivalent circuit model using a particle swarm optimization algorithm according to the intrinsic scattering parameters.

[0061] In a possible implementation, in step 101, removing the parasitic capacitance and parasitic inductance of the test structure of the device under test by using the open-short circuit test structure includes:

[0062] Testing the scattering parameter S of the open circuit de-embedded structure of the small signal equivalent circuit model device O , the scattering parameter S O Converted into admittance parameter Y S , according to the admittance parameter Y S Get the base emitter parasitic capacitance C pbe , base collector parasitic capacitance C pbc and collector emitter capacitance C pbe ;

[0063] Testing the scattering parameter S of the short-circuit de-embedding structure of the small signal equivalent circuit model device S , the scattering parameter S S Transformation group impedance parameter Z S , according to the impedance parameter Z S Get the base parasitic inductance L b , emitter parasitic inductance L e and collector parasitic inductance L c .

[0064] In a possible implementation, in step 103, calculating the intrinsic scattering parameter according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameter includes:

[0065] The complete scattering parameters are measured at the bias point to be extracted according to the small signal equivalent circuit model, and the parasitic capacitance and parasitic inductance are stripped off by addition and subtraction operations and parameter changes to obtain the intrinsic scattering parameters.

[0066] In a possible implementation, in step 104, extracting the intrinsic parameters of the small signal equivalent circuit model using a particle swarm optimization algorithm according to the intrinsic scattering parameters includes:

[0067] A particle swarm optimization algorithm is used to initialize the position and velocity, inertia weight and learning factor of the particle population, establish an objective function and an iterative adjustment mechanism, and calculate the next position according to the current position of the particle swarm and the global optimal position; all particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

[0068] In a possible implementation, traversing all particles and continuously updating the positions of particles to approach an ideal solution includes:

[0069] The error function characterizing the error between the scattering parameter and the intrinsic scattering parameter is used as the fitting target of the particle swarm optimization algorithm; the fitting error of each particle is determined according to the error function, the fitting error of the particle is used as the individual optimal position of the particle, and the minimum value of the fitting error of all particles is used as the global optimal position; all particles are traversed, and after each update of the individual optimal position and the global optimal position of the particle, the updated position and velocity of the particle are input into the small signal equivalent circuit model again.

[0070] In a possible implementation manner, the small signal equivalent circuit model includes parasitic elements and intrinsic elements;

[0071] Parasitic components include base emitter parasitic capacitance C pbe , base collector parasitic capacitance C pbc , collector emitter capacitance Cpbe , base parasitic inductance L b , emitter parasitic inductance L e , collector parasitic inductance L c , electrode parasitic resistance, base resistance R b , emitter resistance R e , Collector resistance R c ;

[0072] The intrinsic element includes the base internal resistance R bi , base emitter capacitance C be , base emitter resistance R be , base collector capacitance C bc , base collector resistance R bc , base collector distributed capacitance C bcx , and the current-controlled current source CCCS, the common base current transfer coefficient α0 under DC conditions, and the base region transit time τ B , collector region transit time τ C ;

[0073] Base emitter parasitic capacitance C pbe Connecting the base external node and the emitter external node; base collector parasitic capacitance C pbc Connect the base external node and the collector external node; collector emitter parasitic capacitance C pbe Connecting the collector external node and the emitter external node; base parasitic inductance L b and base resistor R b After series connection, the base external node and the base internal node are connected; the emitter parasitic inductance L e and emitter resistor R e After series connection, the emitter external node and the emitter internal node are connected; the collector parasitic inductance L c and collector resistor R c After connecting in series, the collector external node and the collector internal node are connected; the base collector distributed capacitance C bcx Connect the base internal node and the collector internal node; the base internal resistor R bi Connect the base internal node and the base intrinsic node; base emitter capacitor C be and the base emitter resistor R be After parallel connection, the emitter internal node and the base intrinsic node are connected; the base collector capacitor C bc , base collector resistance R be The collector internal node and the base intrinsic node are connected in parallel with the current controlled current source CCCS.

[0074] The equivalent circuit used in the embodiment of the present application is a T-type topology, which is closer to the physical structure of the HBT device. The parameter improvement process is: use the open-short structure to remove the parasitic capacitance and parasitic resistance brought by the test structure, use the opencollector test method to calculate and strip the electrode resistance, and obtain the intrinsic scattering parameters. Use the PSO particle swarm algorithm to initialize the particle population, initialize the inertia weight and learning factor, and establish the objective function and iterative adjustment mechanism. The population is evolving in the search, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the predicted goodness of fit is reached, and the algorithm's parameter improvement results are output.

[0075] The embodiment of the present application has the advantages of accurate and fast parameter extraction. The simulation results show that the small signal model results extracted by the embodiment of the present application can well fit the scattering parameters of the actual device test results, and can be used for circuit design and large signal model modeling.

[0076] The present application embodiment provides a HBT transistor small signal model, whose structure is as follows: Figure 2 As shown in FIG. 1 , the model of the HBT small signal model includes parasitic elements and intrinsic elements.

[0077] Parasitic components include: base emitter parasitic capacitance C pbe , base collector parasitic capacitance C pbc , collector emitter capacitance C pbe . Base parasitic inductance L b , emitter parasitic inductance L e , collector parasitic inductance L c Electrode parasitic resistance, base resistance R b , emitter resistance R e , collector resistance R c .

[0078] Intrinsic components include: base internal resistance R bi , base emitter capacitance C be , base emitter resistance R be , base collector capacitance C bc , base collector resistance R bc , base collector distributed capacitance C bcx , and the current-controlled current source CCCS, the common base current transfer coefficient α0 under DC conditions, the base region transit time τ B , collector region transit time τ C .

[0079] Base emitter parasitic capacitance C pbe The base external node and the emitter external node are connected.

[0080] Base collector parasitic capacitance Cpbc The base external node and the collector external node are connected.

[0081] Collector emitter parasitic capacitance C pbe The collector external node and the emitter external node are connected.

[0082] Base parasitic inductance L b and base resistor R b The base outer node and the base inner node are connected in series.

[0083] Emitter parasitic inductance L e and emitter resistor R e After series connection, the emitter outer node and the emitter inner node are connected.

[0084] Collector parasitic inductance L c and collector resistor R c After series connection, the collector external node and the collector internal node are connected.

[0085] Base collector distributed capacitance C bcx Connect the base internal node and the collector internal node.

[0086] Base internal resistance R bi Connect the base intrinsic node and the base intrinsic node.

[0087] Base emitter capacitance C be and the base emitter resistor R be After parallel connection, the emitter internal node and the base intrinsic node are connected.

[0088] Base collector capacitance C bc , base collector resistance R be The collector internal node and the base intrinsic node are connected in parallel with the current controlled current source CCCS.

[0089] The embodiment of the present application provides a parameter extraction method of an HBT small signal equivalent circuit model, which is applicable to the above-mentioned HBT small signal equivalent circuit model. Figure 3 The flow chart of the HBT equivalent circuit model parameter extraction method is shown, including:

[0090] Step 1: Use an open-short structure to remove parasitic capacitance and parasitic resistance caused by the test structure; specifically, extract the parasitic capacitance based on the scattering parameters of the open-circuit de-embedding structure of the HBT device; extract the parasitic inductance based on the scattering parameters of the short-circuit de-embedding structure of the HBT device;

[0091] In the test, the specific connection method is: test instrument -> connecting line -> test probe -> device lead part -> device under test, and the test structure refers to all the structures before the device under test.

[0092] Step 2: Calculate and strip the electrode resistance using the open collector test method, and extract the parasitic resistance based on the scattering parameters under the open collector condition of the HBT device.

[0093] Step 3: Obtain intrinsic scattering parameters based on the parasitic capacitance, parasitic inductance, parasitic resistance, and scattering parameters of the HBT device tested on-wafer: On-wafer testing is to measure the prepared device using the above method, rather than post-packaging testing.

[0094] Step 4: Based on the intrinsic scattering parameters, establish a particle swarm optimization algorithm to extract the intrinsic parameters. Use the PSO particle swarm algorithm to initialize the particle population, initialize the inertia weight and learning factor, and establish the objective function and iterative adjustment mechanism. According to the error function, the fitting error of each particle is evaluated. The population is searching and evolving, and the particles continuously update the optimal position of the particles and the global optimal position until the maximum number of iterations is met or the predicted goodness of fit is reached, and the algorithm's parameter extraction results are output.

[0095] In the above step 1, the parasitic capacitance is extracted according to the scattering parameters of the open circuit de-embedded structure of the HBT device.

[0096] Figure 4 1 is an equivalent circuit diagram of an open circuit de-embedding structure provided in an embodiment of the present application. Testing the scattering parameter S of the open circuit de-embedding structure of the HBT device O , which is converted into the admittance parameter Y according to circuit theory S , according to the admittance parameter, the base emitter parasitic capacitance C is obtained pbe , base collector parasitic capacitance C pbc , collector emitter capacitance C pbe .

[0097]

[0098]

[0099]

[0100] Among them, Y O11 Indicates the input admittance when the output is short-circuited, Y O21 Indicates the forward output admittance when the output is short-circuited, Y O12 Indicates the reverse output admittance when the input is short-circuited, Y O22 It represents the output admittance when the input is short-circuited, ω represents the angular frequency, and Imag represents the imaginary part.

[0101] In the above step 2, the parasitic inductance is extracted according to the scattering parameters of the short-circuit de-embedding structure of the HBT device.

[0102] Figure 5: is an equivalent circuit diagram of an open circuit de-embedding structure provided in an embodiment of the present application, and the scattering parameter S of the short circuit de-embedding structure of the HBT device is tested. S , according to the circuit theory conversion group impedance parameter Z S , according to the impedance parameters, the base parasitic inductance L is obtained b , emitter parasitic inductance L e , collector parasitic inductance L c .

[0103]

[0104]

[0105]

[0106] Among them, Z S11 Indicates the input impedance when the output is short-circuited, Z S21 It represents the forward output impedance when the output is short-circuited, Z S12 Represents the reverse output impedance when the input is short-circuited, Z S22 It represents the output impedance when the input is short-circuited, ω represents the angular frequency, and Imag represents the imaginary part.

[0107] In step 3 above, the external resistance is extracted based on the scattering parameters under the open collector condition of the HBT device.

[0108] Specifically, Figure 6 : is an equivalent circuit diagram of an open collector provided in an embodiment of the present application, and the scattering parameters of the HBT device under the collector open circuit condition are tested. According to the impedance parameters, the base resistance R is obtained. b , emitter resistance R e , collector resistance R c .

[0109]

[0110]

[0111]

[0112] Among them, Real means taking the real part, I b represents the base current.

[0113] The step S3 includes: performing addition and subtraction operations and parameter changes to remove parasitic capacitance and parasitic inductance.

[0114] At the bias point to be extracted, measure the complete scattering parameters, remove the parasitic parameters, and obtain the intrinsic scattering parameters S in .

[0115] Y MO =Y mea -Y O

[0116] Y SO =Y short -Y O

[0117]

[0118]

[0119] Z deem =Z MO -Z SO

[0120] The impedance parameter Z after stripping off the parasitic parameters deem Subtract the external resistance described in S3 to obtain the intrinsic parameter Z in .

[0121]

[0122] Among them, R b is the base resistance, R e is the emitter resistance, R c is the collector resistance.

[0123]

[0124] Then, according to circuit theory, the impedance parameters are converted into scattering parameters to obtain the intrinsic scattering parameters.

[0125] In this embodiment, the mutual conversion among S parameters, Y parameters and Z parameters, and the removal of the values ​​of the parasitic capacitance, the parasitic inductance and the parasitic resistance are all common methods in the art and will not be described in detail here.

[0126] In step 4, according to the scattering parameters of the HBT at the bias point to be extracted, according to the scattering parameters of the short-circuit de-embedding structure in S1, S2 and S3, the scattering parameters of the open-circuit de-embedding structure, and the scattering parameters under the open collector condition, addition and subtraction operations and parameter changes are performed to obtain the intrinsic scattering parameters.

[0127] In step 5, according to the intrinsic scattering parameters, a particle swarm optimization algorithm is used to extract the intrinsic parameters of the small signal equivalent circuit model during the HBT.

[0128] According to the intrinsic S parameters, a particle swarm optimization algorithm is established to extract the intrinsic parameters. The movement rules of the particles are established, and the next position is calculated according to the current position of the particle swarm and the global optimal position.

[0129] x i+1 =x i +v i

[0130] v i+1 =ω·v i +c1×r1×(Pbest i -x i )+c2×r2×(Gbest i -x i )

[0131] Where i represents the number of iterations, x i and v i Represent the current position and velocity of the particle respectively. ω is the iteration weight. c1 and c2 are two constants used to control the behavior of particles during the search process. They are often called acceleration constants, corresponding to the individual experience and social experience of particles, respectively. r1 and r2 are independent random numbers between 0 and 1. This ensures that the search direction and speed of each particle are random, thereby increasing the diversity and global search capability of the algorithm.

[0132] P best and G best They represent the individual best position and the global best position respectively.

[0133] The HBT small signal equivalent circuit model parameter extraction method, the particle dimension in PSO is set to 9, corresponding to the base internal resistance R in the topological structure bi , base emitter capacitance C be , base emitter resistance R be , base collector capacitance C bc , base collector resistance R bc , base collector distributed capacitance C bcx , common base current transfer coefficient α0 under DC conditions, base region transit time τ B , collector region transit time τ C .

[0134] The particle positions and velocities are initialized by random numbers. The boundaries of the positions and velocities of particles in PSO are given based on experience. Through random methods, the positions and velocities of all particles are given independently within the boundaries.

[0135] X=Xmin+rand()*(Xmax-Xmin)

[0136] V=Vmin+rand()*(Vmax-Vmin)

[0137] Among them, Xmin and Xmax are the defined position boundary ranges, Vmin and Vmax are the defined position boundary ranges, and rand() is a random number between 0 and 1.

[0138] Figure 7 The intrinsic equivalent circuit diagram provided in the embodiment of the present application; according to the topological structure and circuit theory, the impedance parameter expression of the intrinsic two-port network is calculated as follows:

[0139]

[0140]

[0141]

[0142]

[0143] in

[0144]

[0145]

[0146]

[0147]

[0148] Where j is the imaginary unit and ω is the angular frequency.

[0149]

[0150] Convert the calculated Z parameter into S parameter, which is S mod .

[0151] The scattering parameters and mixing parameters are considered comprehensively and used as the fitting targets of the algorithm. in As the fitting target, the error function Err characterizes the modeling scattering parameter S in the algorithm. mod and the intrinsic scattering parameter S in The error of is used as the fitting target of the algorithm, and its expression is:

[0152]

[0153] Among them, N represents the number of frequency points, S in is the intrinsic scattering parameter after the parasitic parameters are stripped off from the test data, Smod It is the scattering parameter obtained by simulation calculation of the current position of the particle in the algorithm.

[0154] In this example, the test range is 0.1GHz-50GHz, the test step is 0.1GHz, and there are 500 frequency points in total, so N = 500. At the same time, the fitting error Err is also the fitting target of PSO, and it is expected to obtain the smallest possible fitting error. The smaller the error, the better the fitting.

[0155] The fitting error Err of all particles is taken as the P of the particle. best , traverse all particles and take the minimum fitting error as G best After completing a particle position update, the particle is input into the circuit model again and P is updated. best and G best .

[0156] Determine whether the particle swarm optimization algorithm meets the end condition: reaching the maximum number of iteration steps, or the global optimal fitting result meets the preset goodness. If the end condition is not met, the next iteration will start; if the end condition is met, the iteration will end, the optimal particle position will be output, and the algorithm will end. The output particle position is the intrinsic parameter extracted by the particle swarm optimization algorithm. The intrinsic parameters and the previously extracted parasitic parameters together constitute a complete small signal model.

[0157] In this embodiment, the maximum number of iterations is 150, and the preset goodness of fit is 1%. When the number of algorithm iterations is greater than 150, or the error Err<4%, the algorithm stops iterating, outputs the result, and obtains the intrinsic parameters extracted using the particle swarm optimization algorithm.

[0158] Substitute the parasitic parameters and intrinsic parameters proposed in the above steps into the small signal equivalent circuit to obtain a complete small signal model of the HBT transistor, which is then used for circuit design and establishment of a large signal model of the HBT transistor.

[0159] The effect of the parameter extraction method provided in the embodiment of the present application can be further illustrated by the following simulation example.

[0160] The device used in the embodiment of the present application is an InP-based HBT transistor designed and taped out by the Microwave Integrated Circuit Laboratory of the Institute of Microelectronics, Chinese Academy of Sciences, with an emitter area of ​​0.8×7μm.

[0161] Test conditions: After on-wafer SOLT calibration, measured using an Agilent E8363B vector network analyzer (0.1–50 GHz), emitter-collector voltage V ce =1.7V, base current I b =180uA. All tests are on-chip tests and the test software is ICCAP.

[0162] Parameter extraction results: This method is used to extract parameters of the InP-based HBT transistor small signal model. The extracted intrinsic parameters and parasitic parameters are shown in Table 1.

[0163] Table 1 InP HBT extraction parameters

[0164] Parasitic parameters Numeric Intrinsic parameters Numeric <![CDATA[C pbc / fF]]> 3.97 <![CDATA[R bi / Oh]]> 27.63 <![CDATA[C pbe / fF]]> 21.57 <![CDATA[R bc / kΩ]]> 229.28 <![CDATA[C pce / fF]]> 22.18 <![CDATA[R be / Oh]]> 4.07 <![CDATA[L b / pH]]> 54.03 <![CDATA[C bc / fF]]> 1.64 <![CDATA[L c / pH]]> 53.99 <![CDATA[C be / fF]]> 601.5 <![CDATA[L e / pH]]> 3.06 <![CDATA[C bcx / fF]]> 11.13 <![CDATA[R b / Oh]]> 2.7 <![CDATA[α0]]> 0.983 <![CDATA[R c / Oh]]> 26.28 <![CDATA[τ B / ps]]> 0.27 <![CDATA[R e / Oh]]> 2.28 <![CDATA[τ C / ps]]> 0.31

[0165] The parameters are combined with the InP HBT small signal model equivalent circuit to obtain the small signal equivalent circuit model of the InP HBT device of this embodiment.

[0166] Regarding the modeling results, Figure 8 The optimal convergence curve and the average convergence curve in 20 runs of the algorithm in the embodiment of the present application are shown in Figure 1. The measured results of the embodiment of the present application accurately fit and predict within the millimeter wave frequency range, indicating that the method proposed in the embodiment of the present application can accurately and quickly extract the parameters of the InP-based HBT transistor small signal model.

[0167] Fig. 9 A comparison chart of the actual test results and the S parameters extracted from the small signal model results provided in the embodiment of the present application; a comparison chart of the actual test results of the InP HBT device at the bias point of voltage Vce=1.7V and Ib=180uA in the range of 0.1-50GHz and the S parameters extracted from the small signal model results in the embodiment of the present application.

[0168] The small signal equivalent circuit model parameter extraction method provided in the embodiment of the present application overcomes the problems of slow parameter extraction speed, inaccurate parameter extraction results, and inaccurate fitting at high frequencies in the prior art. The equivalent circuit adopted is a T-type topology, which is closer to the physical structure of the HBT device. The simulation results show that the scattering parameters that can well fit the actual device test results can be used for circuit design and large signal model modeling.

[0169] In summary, the embodiment of the present application provides a method for extracting parameters of a small signal equivalent circuit, by using an open-short structure to remove the parasitic capacitance and parasitic inductance of the test structure of the device to be tested; using an open collector test method to calculate and strip the electrode resistance; calculating the intrinsic scattering parameters based on the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters; and using a particle swarm optimization algorithm to extract the intrinsic parameters of the small signal equivalent circuit model based on the intrinsic scattering parameters. This method solves the problems of slow parameter extraction speed, inaccurate parameter extraction results, and inaccurate fitting at high frequencies in the prior art extraction process. It improves the extraction efficiency and accuracy of small signal models.

[0170] Based on the same technical concept, the embodiment of the present application also provides a parameter extraction system for a small signal equivalent circuit, which is applicable to a small signal equivalent circuit model, such as Fig.10 As shown, the system comprises:

[0171] A parasitic parameter extraction module 1001 is used to remove the parasitic capacitance and parasitic inductance of the test structure of the device under test using an open-short structure;

[0172] The resistance stripping module 1002 is used to calculate and strip the electrode resistance using an open collector test method;

[0173] An intrinsic scattering parameter module 1003, used to calculate intrinsic scattering parameters according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters;

[0174] The parameter extraction module 1004 is used to extract the intrinsic parameters of the small signal equivalent circuit model using a particle swarm optimization algorithm according to the intrinsic scattering parameters.

[0175] In a possible implementation, the parameter extraction module 1004 is specifically configured to:

[0176] Use the particle swarm optimization algorithm to initialize the particle population, inertia weight and learning factor, establish the objective function and iterative adjustment mechanism, and calculate the next position based on the current position of the particle swarm and the global optimal position;

[0177] All particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

[0178] The present application also provides an electronic device corresponding to the method provided in the above embodiment. Fig.11 , which shows a schematic diagram of an electronic device provided by some embodiments of the present application. The electronic device 20 may include: a processor 200, a memory 201, a bus 202 and a communication interface 203, wherein the processor 200, the communication interface 203 and the memory 201 are connected via the bus 202; the memory 201 stores a computer program that can be run on the processor 200, and the processor 200 executes the method provided by any of the aforementioned embodiments of the present application when running the computer program.

[0179] The memory 201 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one physical port 203 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0180] The bus 202 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs, and the processor 200 executes the programs after receiving execution instructions. The method disclosed in any implementation of the aforementioned embodiment of the present application may be applied to the processor 200, or implemented by the processor 200.

[0181] The processor 200 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 200. The above processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a readily available programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor can be combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the above method in combination with its hardware.

[0182] The electronic device provided in the embodiment of the present application and the method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects as the method adopted, operated or implemented by them.

[0183] The present application also provides a computer-readable storage medium corresponding to the method provided in the above embodiment. Fig.12The computer-readable storage medium shown is a CD 30 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, the method provided in any of the aforementioned embodiments is executed.

[0184] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0185] The computer-readable storage medium provided in the above-mentioned embodiments of the present application and the method provided in the embodiments of the present application are based on the same inventive concept and have the same beneficial effects as the method adopted, run or implemented by the application program stored therein.

[0186] It should be noted that:

[0187] The algorithm and display provided herein are not inherently related to any particular computer, virtual device or other equipment. Various general purpose devices can also be used together with the teachings based on this. According to the above description, it is obvious to construct the structure required for this type of device. In addition, the application is not directed to any specific programming language. It should be understood that the content of the application described herein can be realized using various programming languages, and the description of the specific language above is to disclose the best mode of implementation of the application.

[0188] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0189] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the claims below, the inventive aspects are less than all the features of the single embodiment disclosed above. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0190] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0191] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0192] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some or all components in the creation device of the virtual machine according to the embodiment of the present application. The application can also be implemented as a device or device program (e.g., computer program and computer program product) for executing part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0193] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "a" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0194] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for extracting parameters of a small signal equivalent circuit, applicable to a small signal equivalent circuit model, characterized in that: The method comprises: Using an open-short test structure to remove parasitic capacitance and parasitic inductance of a test structure of the device under test; Calculate and strip the electrode resistance using the open collector test method; Calculating intrinsic scattering parameters according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameters; According to the intrinsic scattering parameters, a particle swarm optimization algorithm is used to extract the intrinsic parameters of the small signal equivalent circuit model.

2. The method according to claim 1, characterized in that According to the intrinsic scattering parameters, the intrinsic parameters of the small signal equivalent circuit model are extracted using a particle swarm optimization algorithm, including: Use the particle swarm optimization algorithm to initialize the position and speed, inertia weight and learning factor of the particle population, establish the objective function and iterative adjustment mechanism, and calculate the next position based on the current position of the particle swarm and the global optimal position; All particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

3. The method according to claim 2, characterized in that The process of traversing all particles and continuously updating the positions of particles to approach the ideal solution includes: The error function characterizing the error between the scattering parameters and the intrinsic scattering parameters is used as the fitting target of the particle swarm optimization algorithm; Determine the fitting error of each particle according to the error function, take the fitting error of a single particle as the individual optimal position of the single particle, and take the minimum value of the fitting errors of all particles as the global optimal position; All particles are traversed, and after the individual optimal position and global optimal position of a single particle are updated each time, the updated position and velocity of the particle are input into the small signal equivalent circuit model again.

4. The method according to claim 1, characterized in that The small signal equivalent circuit model includes parasitic elements and intrinsic elements; The parasitic elements include base-emitter parasitic capacitance, base-collector parasitic capacitance, collector-emitter capacitance, base parasitic inductance, emitter parasitic inductance, collector parasitic inductance, electrode parasitic resistance, base resistance, emitter resistance, collector resistance; Intrinsic elements include base internal resistance, base emitter capacitance, base emitter resistance, base collector capacitance, base collector resistance, base collector distributed capacitance, and current controlled current source, common base current transfer coefficient under DC conditions, base region transit time, collector region transit time; The base-emitter parasitic capacitor connects the base external node and the emitter external node; the base-collector parasitic capacitor connects the base external node and the collector external node; the collector-emitter parasitic capacitor connects the collector external node and the emitter external node; the base parasitic inductance and the base resistor are connected in series and then connected to the base external node and the base internal node; the emitter parasitic inductance and the emitter resistor are connected in series and then connected to the emitter external node and the emitter internal node; the collector parasitic inductance and the collector resistor are connected in series and then connected to the collector external node and the collector internal node; the base-collector distributed capacitor connects the base internal node and the collector internal node; the base internal resistor connects the base internal node and the base intrinsic node; the base-emitter capacitor and the base-emitter resistor are connected in parallel and then connected to the emitter internal node and the base intrinsic node; the base-collector capacitor, the base-collector resistor and the current-controlled current source are connected in parallel and then connected to the collector internal node and the base intrinsic node.

5. The method according to claim 1, characterized in that The method of using an open-short circuit test structure to remove parasitic capacitance and parasitic inductance of a test structure of a device under test comprises: Testing the scattering parameters of the open circuit de-embedded structure of the small signal equivalent circuit model device, converting the scattering parameters into admittance parameters, and obtaining the base emitter parasitic capacitance, the base collector parasitic capacitance and the collector emitter capacitance according to the admittance parameters; The scattering parameters of the short-circuit de-embedding structure of the small-signal equivalent circuit model device are tested, the scattering parameters are converted into impedance parameters, and the base parasitic inductance, the emitter parasitic inductance and the collector parasitic inductance are obtained according to the impedance parameters.

6. The method according to claim 1, characterized in that The calculating the intrinsic scattering parameter according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameter comprises: The complete scattering parameters are measured at the bias point to be extracted according to the small signal equivalent circuit model, and the parasitic capacitance and parasitic inductance are stripped off by addition and subtraction operations and parameter changes to obtain the intrinsic scattering parameters.

7. A parameter extraction system for a small signal equivalent circuit, applicable to a small signal equivalent circuit model, characterized in that: The system comprises: A parasitic parameter extraction module, used to remove parasitic capacitance and parasitic inductance of a test structure of a device under test using an open-short circuit test structure; Resistance stripping module, used to calculate and strip electrode resistance using open collector test method; An intrinsic scattering parameter module, used to calculate the intrinsic scattering parameter according to the parasitic capacitance, parasitic inductance, electrode resistance and scattering parameter; A parameter extraction module is used to extract the intrinsic parameters of the small signal equivalent circuit model using a particle swarm optimization algorithm according to the intrinsic scattering parameters.

8. The system according to claim 7, characterized in that The parameter extraction module is specifically used for: Use the particle swarm optimization algorithm to initialize the particle population, inertia weight and learning factor, establish the objective function and iterative adjustment mechanism, and calculate the next position based on the current position of the particle swarm and the global optimal position; All particles are traversed, and the particles continuously update their positions to approach the ideal solution until the maximum number of iterations is met or the preset goodness of fit is reached, and the optimal particle position is output as the intrinsic parameter of the small signal equivalent circuit model.

9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and the computer-readable instructions can be executed by a processor to implement the method according to any one of claims 1-6.

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